2. Fabrication techniques. KNU Seminar Course 2015 Robert Mroczyński

Transcription

1 2. Fabrication techniques KNU Seminar Course 2015 Robert Mroczyński

2 Technological layers used in the course of the IC fabrication Semiconductors Fundamental part of each IC, active material of semiconductor device channel of the MOS transistor (also as the amorphous semiconductor layer in TFTs) Dielectrics Isolation between metallization levels, passivation of semiconductor devices, implantation/diffusion masks, gate dielectrics! Conductive materials Pads, contacts, conductive paths 2

3 The division of fabrication techniques Two fundamental techniques for layers fabrication Direct chemical reaction between semiconductor substrate and reactive gases e.g., thermal oxidation, thermal nitridation, plasma oxidation; the fabricated layer is a derivative of the semiconductor substrate e.g., silicon oxynitride; only few materials can be obtained on the particular substrate Semiconductor substrate acts only as the passive component during particular layer fabrication e.g., chemical vapor deposition, physical vapor deposition; the freedom of choice of the obtained layer and semiconductor substrate 3

4 Fundamental techniques Direct chemical reaction Thermal oxidation RTP (Rapid Thermal Processing) The layer is deposited on the substrate CVD Chemical Vapor Deposition (APCVD, LPCVD, PECVD, MOCVD) ALD Atomic Layer Deposition PVD Physical Vapor Deposition (Thermal Evaporation, Ion Sputtering, Magnetron Reactive Sputtering) 4

5 Silicon dioxide (SiO 2 ) fabrication Silicon is consumed 44 %!! Silicon dioxide h 1 SiO 2 Si h 1 h 2 Silicon substrate h 2 5

6 Thermal oxidation of silicon SiO 2 Si Quartz furnace with heating system furnace zone C O 2 Ar N 2 Gas distribution system 6

7 Oxide thickness [mm] Process parameters Doering R., Nishi Y.: Handbook of semiconductor technology Temperature Time Pressure Reactive gases composition and flows Semiconductor substrate s orientation Type of the process ( wet <-> dry ) 10,0 1,0 0,1 20 atm 10 atm 5 atm 1 atm 0, Oxidation time[min] Huff H.R., Gilmer D.C.: High dielectric constant materials 7

8 Dry <-> wet oxidation DRY WET Fabricated in pure oxygen (sometimes with H addition in order to improve electrophysical properties and kinetics control Very slow growth Low amount of defects on the silicon/silicon dioxide interface (Q it ) Fabricated in the mixture of oxygen and water vapors Fast growth Bigger amount of defects on the silicon/silicon dioxide interface (Q it ), as well as the dielectric layer bulk in comparison to dry oxide A. Javey, Berkeley Univ., EECS143 8

9 Vertical furnaces Lower amount of semiconductor wafers batch -> higher process versatility Lower area occupation by the equipment, i.e., foot-print The better control of reactive gases flow around the semiconductor wafers -> the better homogeneity of silicon dioxide thickness across the each wafer The possibility for introduction of additional rotation of silicon wafers during the process -> better homogeneity Smaller temperature gradient onto the wafer Higher automation of processing The easier change of quartz furnace 9

10 Ultra-thin oxide layers formation In ultra-thin regime the oxidation time is very short from several minutes down to few seconds it is hard to control the thermal process -> lack of process repeatability! 10

11 and thus RTP reactors have been designed Rapid Thermal Processing The huge of thermal power is focused onto a very small area -> the possibility to obtain a very rapid and precise temperature changes Small volume of the reactive chamber -> the full change of the reactive gases in few seconds 11

12 Heating Neutral gases Process Reactive gases Cooling Neautral gases Heating Neutral gases Stage 1 Stage 2 Other reactive gases Cooling Neautral gases Typical RTP process flow Temp. Temp. 25 s 1 min Time Time 12

13 Applications of RTP Fabrication of ultra-thin dielectric layer (RTO Rapid Thermal Oxidation, RTN Rapid Thermal Nitridation) The densification of layers The annealing of layers: dielectric (fabricated by different methods) in order to improve electro-physical properties, conductive in order to improve contact properties Post implantation annealing in order to electrical activation of dopants Reflow of Phospho-Silicate- and Phospho-Boron-Silicate Glass (PSG and BPSG) Silicide formation (TiSi 2 ) 13

14 Thermal oxidation <-> RTP Thermal Oxidation RTP 14

15 Silicon oxide applications Field Oxide Serves as an isolation barrier between individual transistors to isolate them from each other Field oxide Transistor site p + Silicon substrate Common field oxide thickness range from Å to Å Wet oxidation is the preferred method Quirk M., Serda J.: Semiconductor Manufacturing Technology, Prentice Hall

16 Silicon oxide applications Gate Dielectric Serves as a dielectric between the gate and source-drain parts of MOS transistor Gate oxide Source Gate Transistor site Drain p + Silicon substrate Growth rate at room temperature is 15 Å per hour up to about 40 Å Common gate oxide film thickness range from about 30 Å to 500 Å Dry oxidation is the preferred method Quirk M., Serda J.: Semiconductor Manufacturing Technology, Prentice Hall

17 Silicon oxide applications masking material Masking material when implanting dopant into wafer Dopant barrier spacer oxide Ion implantation Gate Spacer oxide protects narrow channel from high-energy implant Dopants diffuse into unmasked areas of silicon by selective diffusion Quirk M., Serda J.: Semiconductor Manufacturing Technology, Prentice Hall

18 Silicon oxide applications Pad Oxide Provides stress reduction for Si 3 N 4 Silicon oxynitride Nitride oxidation mask Bird s beak region Selective oxidation Pad oxide Silicon dioxide Silicon substrate Thermally grown and very thin Quirk M., Serda J.: Semiconductor Manufacturing Technology, Prentice Hall

19 LOCOS Local Oxidtion of Silicon The decrease of field oxide height and window shape in comparison to classical isolation The possibility of further easier processing steps, e.g. dielectric and conductive layers deposition Better isolation of adjacent devices 19

20 Plummer J.D., Deal M.D., Griffin P.B.: Silicon VLSI technology 20

21 Step coverage φ The layer growth kinetics depends on the angle which allows to access of deposited materials The profile is a very important, but not independent parameter The homogeneity of step coverage is temperature dependent the higher temperature, the better particles allocation more convenient places from the energetic point of view 21

22 Examples of covering failures Plummer J.D., Deal M.D., Griffin P.B.: Silicon VLSI technology 22

23 Shallow Trench Isolation (STI) Much better isolation of adjacent devices in comparison to LOCOS 23

24 STI with CMP CMP Chemical-Mechanical Polishing modified version of STI which is commonly used in nowadays ICs technologies 24

25 How it is in the reality? Doering R., Nishi Y.: Handbook of semiconductor technology 25

26 Silicon oxide applications Screen Oxide Sometimes referred to as sacrificial oxide, screen oxide, is used to reduce implant channeling and damage Assists creation of shallow junctions Ion implantation Screen oxide p + Silicon substrate High damage to upper Si surface + more channeling Low damage to upper Si surface + less channeling Dry oxide Quirk M., Serda J.: Semiconductor Manufacturing Technology, Prentice Hall

27 Silicon oxide applications Intermetal Oxide Serves as protective/isolation layer between metal lines Passivation layer Interlayer oxide Bonding pad metal M-4 ILD-5 ILD-4 M-3 This oxide is not thermally grown, but is deposited (see further part of this lecture!) Quirk M., Serda J.: Semiconductor Manufacturing Technology, Prentice Hall

28 Chemical Vapor Deposition (CVD) processes Atmospheric Pressure CVD (APCVD) Low Pressure CVD (LPCVD) Plasma Enhanced CVD (PECVD) Metalo-Organic CVD (MOCVD) Atomic Layer Deposition (ALD) Doering R., Nishi Y.: Handbook of semiconductor technology 28

29 APCVD Gases inlet Nitrogen courtain Process parameters: Reactive gases composition Wafer transportation speed Temperature Transport belt To pumps Heater Plummer J.D., Deal M.D., Griffin P.B.: Silicon VLSI technology 29

30 LPCVD Pressure meter Loadlock Quartz furnace with heaters Process parameters: Reactive gases composition Temperature Pressure Time To pumps Si 2 H 2 N 2 SiH 4 Gas distribution system 30

31 PECVD R.F. generator Gas inlet ~ To pumps Process parameters: Reactive gases composition Temperature Pressure Power PLASMA Electrodes Time Electrode geometry Heated table 31

32 The comparison of CVD reactors PROCESS ADVANTAGES DISADVANTAGES APPLICATION APCVD ( C) simplicity of reactor fast deposition rate low temperature processing poor step coverage impurities passivation and isolation oxides (doped, as well as un-doped) cleanliness of deposited high temperature gate and tunneling dielectrics LPCVD ( C) materials homogeneity conformal step coverage a large batch processing processing low deposition rate isolation oxides (doped, as well as un-doped) silicon nitrides poly-silicon PECVD ( C) low temperature processing fast deposition rate good step coverage impurities passivation and isolation oxides M(O)EMS! 32

33 Atomic Layer Deposition (ALD) ALD is a self-limiting, sequential surface chemistry that deposits conformal thin-films of materials onto substrates of varying compositions ALD is similar in chemistry to CVD, except that the ALD reaction breaks the CVD reaction into two half-reactions, keeping the precursor materials separate during the reaction ALD film growth is self-limited and based on surface reactions, which makes achieving atomic scale deposition control possible By keeping the precursors separate throughout the coating process, atomic layer control of film grown can be obtained as fine as ~0.1 angstroms per monolayer 33

34 Exemplary ALD process scheme hafnium dioxide (HfO 2 ) deposition Hf Hf H H H H O O O O M. Godlewski: Technologia Osadzania Warstw Atomowych zastosowania w elektronice, fotowoltaice i optoelektronice Si Si Si Si Si Si Si Si 34

35 Exemplary ALD process scheme hafnium dioxide (HfO 2 ) deposition Hf Hf H H H H O O O O M. Godlewski: Technologia Osadzania Warstw Atomowych zastosowania w elektronice, fotowoltaice i optoelektronice Si Si Si Si Si Si Si Si 35

36 Exemplary ALD process scheme hafnium dioxide (HfO 2 ) deposition H O H H O H H O H Hf Hf O O O O M. Godlewski: Technologia Osadzania Warstw Atomowych zastosowania w elektronice, fotowoltaice i optoelektronice Si Si Si Si Si Si Si Si 36

37 Exemplary ALD process scheme hafnium dioxide (HfO 2 ) deposition Hf Hf H H H H O O O O Hf O Hf O Hf O Hf O O O O M. Godlewski: Technologia Osadzania Warstw Atomowych zastosowania w elektronice, fotowoltaice i optoelektronice Si Si Si Si Si Si Si Si 37

38 Exemplary ALD process scheme hafnium dioxide (HfO 2 ) deposition Hf O Hf O Hf O Hf O O O O Hf O Hf O Hf O Hf O O O O M. Godlewski: Technologia Osadzania Warstw Atomowych zastosowania w elektronice, fotowoltaice i optoelektronice Si Si Si Si Si Si Si Si 38

39 ALD applications High-k dielectric materials HfO 2, Al 2 O 3, TiO 2, ZrO 2 Barrier layers or metal gates: TiN, TaN Huff H.R., Gilmer D.C.: High dielectric constant materials 39

40 Physical Vapor Deposition (PVD) processes Thermal evaporation Ion sputtering Radio Frequency (R.F) magnetron sputtering 40

41 Thermal evaporation Vacuum chamber Support wih wafers Material evaporated Thermal evaporation -> only selected materials, such as: Al, Au, Ag Very high vacuum -> mean particles free path Resistor and evaporated material can react with each other -> impurities To pumps Cheap and easy technology! 41

42 Conductive materials Material Melting temperature [ C] Resistivity [µωcm] Silicon 1412 ~ 10 9 Polysilicon (poly-si) Aluminum (Al) Copper (Cu) Tungsten (W) Titanium (Ti) Tantalum (Ta) Molibdenum (Mo) Platinum (Pt)

43 Thermal evaporation with e-gun Magnets Focused high energy electron beam (>4 kw) High magnetic field which deflects the electron flux -> mass separation and control Target Cooling system -> no impurities from crucible material BUT Problems with the evaporation of compound materials different vapor pressure Cooling system E-gun (hot filament) X-Rays Porosity of layers due to the high energy ions which introduce clusters deposition on the surface 43

44 Evaporation failures The problem with the ensure of homogeneity of evaporated materials on the large surface simultaneously with high layer growth rate Shadow zones Thickness The only option -> to increase the source-substrate lenght BUT reactor geometry/size, as well as high vacuum necessity issues Wafers rotation Increase the area of evaporated material 44

45 Sputtering process In order to glow discharge (plasma ignition) the vacuum cannot be as high as in the case of thermal evaporation Low vacuum -> impurities + low mean free path Small differences of compound materials in comparison to target composition Better process control -> more controllable process parameters BUT optimization Very high equipment cost Increase of ion density -> magnetic field use (magnetron sputtering process) Radio frequency (R.F.) sputtering -> in order to dielectric layers fabrication PLASMA anode cathode electrons + ions - Si wafer Target 45

46 Magnetron sputtering Magnetic field can trap the electrons in the vapor phase Electrons more effectively ionize the gas particles -> ion bombardment of target is increased Lower process temperatures Higher sputtered area Magnets Target N S N PLAZMA Si wafers 46

47 The most common problem Electromigration effect Sze S.M.: Semiconductor devices physics and technology Javey A.: EE143 Characteristic for ALL materials Electrons transfer theirs momentum to material s atom - > atoms flow Critical condition current density At the negative potential possible open At the positive potential possible shortage 47

48 Aluminum and copper materials commonly used for conductive patterns Al Cu Resistivity [µωcm] Electromigration resistance Corrosion resistance Low Low High Medium CVD fabrication Yes No CMP processing Yes Yes 48

49 Copper metallization There are no effective methods for patterns definition by using classical lithography methods (no possibility for dry etching) Damascene technology is the only option Necessity for using barrier layers which eliminate the migration of copper atoms into adjacent semiconductor and dielectric layers There are also needed layers which improve the adhesion level and special layers for copper electroplating (copper fabrication) Plummer J.D., Deal M.D., Griffin P.B.: Silicon VLSI technology 49

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51 Thank you for attention! 51