TSV Processing and Wafer Stacking. Kathy Cook and Maggie Zoberbier, 3D Business Development

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1 TSV Processing and Wafer Stacking Kathy Cook and Maggie Zoberbier, 3D Business Development

2 Outline Why 3D Integration? TSV Process Variations Lithography Process Results Stacking Technology Wafer Bonding technology and process results Micro-bumping SUSS Product Offerings for 3D

3 3D Benefits Die size reduction (higher yield due to smaller die size leads to lower cost) Source: Prismark presentation, 3-D Wafer Bonding, November Performance improvement (shortened signal lines reduce latency) Use of best native process nodes (eg. digital 65nm, analog 180nm) - optimize power consumption Heterogeneous integration of different substrate materials (Silicon and III-V)

4 3D Integration Drivers These are all potential 3D drivers: Image sensors and memory stacking (for mobile applications) are two mass volume applications for TSVs with short time-tomarket

5 Through Silicon Via Wafer Processing Create Etch Mask Coat Exposure Develop Etching Insulation CVD, TEOS Via Filling Material: Copper, Tungsten Different Materials require different deposition processes (electroplating, CVD, LPCVD) Cu is the most widely used material today Wafer Stacking Cu diffusion, adhesive or fusion bonding Micro-bumping 25 x 155 microns (6:1) CVD TiN (60 nm) Oxide (150 nm) Image Courtesy of Nexx Systems

6 Trends in TSV Manufacturing VIA-FIRST Vias created early in the device manufacturing process Issues with temperature compatibilty of subsequent CMOS steps Materials must be CMOS compatible Only known good wafers are used Lower cost than via-last Image Courtesy of Amkor

7 Trends in TSV Manufacturing VIA-LAST No thermal stress issues Via location must be considered during design phase Potentially lower yield Creates a supply chain issue Image Courtesy of Amkor

8 TSV Process Variations

9 3D IC Process Sequence Variations Process IC Wafer Step #1 Step #2 Step #3 A FEOL TSV (vias first) Wafer Thinning (temp. handle) "face-up" Bond (metal bonding) B FEOL TSV (vias first) "face-down" Bond (metal bonding) Wafer Thinning (on 3D stack) C BEOL TSV (vias first) Wafer Thinning (temp. handle) "face-up" Bond (metal bonding) D BEOL TSV (vias first) "face-down" Bond (metal bonding) Wafer Thinning (on 3D stack) E No TSV TSV from front (vias first) "face-down" Bond (metal bonding) Wafer Thinning (on 3D stack) F No TSV TSV from front (vias first) Wafer Thinning (temp. handle) "face-up" Bond (metal bonding) G No TSV "face-down" Bond (all methods) Wafer Thinning (on 3D stack) TSV from back (vias last) H No TSV Wafer Thinning (temp. handle) "face-up" Bond (all methods) TSV from front (vias last) I No TSV Wafer Thinning (temp. handle) TSV from back (vias first) "face-up" Bond (metal bonding)

10 3D IC Process Variations Process A & C Steps 3 and 4. Align and Bond CBC200 or CBC300 Step 1. Coat and exposure of pads ACS200 or ACS300 MA200Compact or MA300 Step 2. Carrier wafer technology Source: Phil Garrou, MCNC 2008

11 3D IC Process Variations Process B & D Step 3. Coat and exposure for redistribution ACS200 or ACS300 MA200 Compact or MA300 Steps 2 and 4. Align and bond CBC200 or CBC300 Source: Phil Garrou, MCNC 2008

12 3D IC Process Variations Process E Step 2. Top-side align (TSA), exposure and coat ACS200 or ACS300 MA200 Compact or MA300 Step 4. Back-side align (BSA), exposure and coat ACS200 or ACS300 MA200 Compact or MA300 Step 3. Align and bond CBC200 or CBC300 Source: Phil Garrou, MCNC 2008

13 3D IC Process Variations Process F Step 4. Back-side align (BSA), exposure and coat ACS200 or ACS300 MA200 Compact or MA300 Step 2. Top-side align (TSA), exposure and coat ACS200 or ACS300 MA200 Compact or MA300 Step 5. Align and bond CBC200 or CBC300 Step 3. Carrier wafer technology Source: Phil Garrou, MCNC 2008

14 3D IC Process Variations Process G Step 4. Top-side align (TSA), exposure and coat ACS200 or ACS300 MA200 Compact or MA300 Steps 2 and 4. Align and bond CBC200 or CBC300 Source: Phil Garrou, MCNC 2008

15 3D IC Process Variations Process H Step 4. Align and bond CBC200 or CBC300 Step 3. Carrier wafer technology Source: Phil Garrou, MCNC 2008

16 3D IC Process Variations Process I Step 4. Back-side align (BSA), exposure and coat ACS200 or ACS300 MA200 Compact or MA300 Step 5. Align and bond CBC200 or CBC300 Step 3. Carrier wafer technology Source: Phil Garrou, MCNC 2008

17 Lithography Process Results

18 TSV Process Results: Etch Mask Exposure Via openings: Results based on MA200, UV400 proximity exposure

19 TSV Process Results: Via hole Exposure Via holes with sidewall angle of 80 Reliable coating using AltaSpray Contact pad opening Contacts of 10 µm diameter, 80 µm deep vias are clearly resolved Spray Coat on Gamma AltaSpray Exposure on MA200compact Spray Develop on Gamma

20 TSV Process Results: Spray Coating Resist: AZ4999 Positive Resist 140µm SUSS AltaSpray Coater 93µm 85µm 65µm

21 Stacking Technology

22 TSV size roadmap >2014 CIS 75-50µm µm Memory 35-25µm µm... <5µm

23 TSV ~ 75%

24 Bonder Post-bond Alignment Accuracy Roadmap >2014 CIS 75-50µm µm Memory 35-25µm µm... <5µm Alignment Accuracy 9-5µm 4-3µm 1.75µm 0.6µm

25 Primary Bonding Technology Categories SiO 2 fusion bonding Metal Bonding Metal (Cu) diffusion bonding Metal Eutectic bonding ( Cu/Sn) Polymer adhesive bonding Chip 1 Chip 1 Chip 1 Metal Metal Adhesive Adhesive Chip 2 Chip 2 Chip 2 Image Courtesy of MCNC

26 Comparison of Bonding Methods Metal to Metal Direct Bonding Adhesive Bonding Mechanical / Electrical Mechanical and electrical Mechanical Mechanical nm flat Roughness (nm) ca. 250 C Requirements Clean Oxide free Planarity Clean Treated surface for low Temp. Bonding Survive post cure processing Pros / Cons High surface roughness and flatness requirements High bond strength Sensitive to particles Topography tolerant Low temperature process Poor mechanical properties

27 25 Cu-Cu 3D TSV Aligned Pairs Average Aligner Overlay Accuracy 0.6 ±0.3 µm sqrt (x 2 +y 2 ) Before Bond and Anneal 25 Aligned Pairs IR Alignment on BA200 Average Post Bond Overlay Accuracy 1.4 ±0.7 µm sqrt (x 2 +y 2 ) After Bond and Anneal 25 Bonded Pairs Bonded 425C

28 BCB Pairs -Post-bond IR Images Misalignment vs. position along horizontal wfr diameter, notch down misalignment (um) position (mm) Waf 1 Y Waf 1 X Waf 2 Y Waf 2 X Waf 3 Y Waf 3 X

29 Post Bond Alignment Data using Direct Bonding Post Bond Final Alignment Accuracy Wafer # dxl " dyl dxr dyr Accuracy dx dy dr dt Alignment in Pixels in Pixels in Pixels in Pixels in Pixels in Pixels in Pixels in Pixels in Pixels in µm Average µm St Dev µm Max µm Min µm

30 Example: Au-Ge Eutectic Bonding 200mm Au-SiGe Eutectic forms at 361 C for Au 28% and Ge 72% Simple Eutectic Diagram Can be driven from diffusion reaction or melted from alloy layer. Other systems Cu-Sn, Au-Sn, Au-Si, Al-Ge Appl. Phys. Lett 64(6)1994p772.

31 Applications for MicroBumping MicroBumping for 3D Packaging & Integration Bumps are smaller than traditional packaging sizes (<50um) Large number of bumps (>10M per wafer) All chip-sizes (often large compared to traditional bumped chips) Heterogeneous Devices (Logic, Memory, Sensors, etc.) Bump yield extremely critical Chip on Chip, Chip on Si-Substrate, Substrate, Chip on Wafer, Wafer on Wafer Main reason for 3D: Performance, Integration 200&300mm

32 MicroBumping for 3D

33 MicroBumping for 3D

34 C4NP Bumping Process Flow Wafer with passivation Any Size C4NP Mold Std. Size (13x14 ) UBM Deposition & Patterning Solder Fill Molten solder injection Mold Clean Recycle Wafer Inspection Mold Inspection Failed Insp. Process Merge Point Empty Mold Solder Transfer Final Packaging (Dice / Sort / Pick)

35 SUSS Product Offerings for 3D Lithography: 1x Exposure tools for TSV patterning Large Gap Optics to expose inside TSV Resist coaters: spin on and spray coating processes for standard lithography (etch mask) and TSV processing Permanent Bonding for 3D stacking Inspection tools (DSM - front to backside measurement) 3D Packaging/Micro-bumping with C4NP Equipment

36 3D Integration - Our Solutions Set Standards

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