Effect of High Pressure Deuterium Annealing on Performance and Reliability of MOSFETs with High-k Gate Dielectrics and Metal Gate

Transcription

1 Effect of High Pressure Deuterium Annealing on Performance and Reliability of MOSFETs with High-k Gate Dielectrics and Metal Gate H. Park, M. Chang, H. Yang, M. S. Rahman, M. Cho, B.H. Lee*, R. Choi*, and H. Hwang Gwangju Institute of Science and Technology,, *SEMATECH

2 Outline A. Effects of high pressure annealing on Hf-based gate dielectrics Improvement of device performance Effect of deuterium concentration Device reliability with subsequent N 2 annealing Effect of fluorine annealing B. Effects of high Pressure H 2 annealing on SOI MOSFETs Improvement of bottom Si/ interface quality C. Effects of high Pressure annealing on Metal gate MOSFET Metal electrode dependent interface trap generation Mobility improvement with high pressure annealing

3 Motivations High interface trap density at high-k/si significantly degrades MOSFET mobility To completely passivate interface traps, high temperature FG PDA (45 o C~6 o C) is introduced recently* high thermal budget increases interfacial layer thickness not compatible with PMA high pressure pure H 2 / PMA *References K. Onishi et al. Effects of high-temperature forming gas anneal on HfO 2 MOSFET performance, at Proc. of Symp. VLSI Tech., 21 R. J. Carter et al. Passivation and interface state density of /HfO 2 -based/polycrystalline-si gate stacks, at Applied Physics Letter., 23 H. Hwang, US Patent 6,913,961

4 8-inch, single wafer high pressure annealing system AFTER Gas inlet Gas outlet H 2 N 2 or gas Pressure control unit High pressure annealing chamber Temperature controller Process control PC Pressure Monitor BEFORE

5 Process details MOS capacitor process flow (GIST) Wafer clean 6nm HfO 2 deposition in ALD system Photolithography Gate electrode formation Post metallization anneal Forming gas anneal -4 o C, 3min - Atmospheric pressure High pressure(h 2 or ) anneal -4 o C, 3min. - Process pressure : 5-6atm MOSFET Process flow (SEMATECH) Wafer clean Surface nitridation Gate dielectric deposition : Hf-silicate and HfAlO : HfSiON w/o surface nitridation Post Deposition Anneal Electrode deposition : TiN & a-si LDD & Halo implantation Thin nitride layer deposition Oxide spacer formation S/D implantation & activation anneal Ti silicide formation Pre-metal dielectric layer formation W plug with Ti/TiN liner formation Al metal pattern Post Metallization Anneal FG anneal 48 o C 3min (SEMATECH) High pressure anneal 4 o C 3min annealing pressure : 5-2atm

6 HPA effect : mobility improvement Before Anneal After Anneal Surface Pretreatment Film PDA Peak Mobility % Universal E-high Mobility % Universal Peak Mobility % Universal E-high Mobility % Universal NO 7C 2S HFSiO 4A NONE % % % % NO 7C 2S HFSiO 4A O2 5C 3s % % % % Before Anneal After Anneal Film PDA Peak Mobility % Universal E-high Mobility % Universal Peak Mobility % Universal E-high Mobility % Universal % % % % HfO2 RTNO % % % % % % % % HfSiO RTNO % % % % % % % % 1% 1MV mobility achieved for high pressure annealed RTNO HfSiO sample Part A

7 HPA effect : Annealing gas dependency Mag. of g m improvement [%] HfAlO/HfSiO nmosfet After 2atm preesure anneal 4 o C, 3min HP N 2 HP FG HP H 2 HP Mag. of g m improvement [%] HfSiON nmosfet After 2atm preesure anneal 4 o C, 3min HP N 2 HP FG HP H 2 HP Negligible improvement of transconductance is observed after high pressure N 2 or FG annealing. Significant g m improvement is achieved by high pressure pure hydrogen or deuterium annealing. Part A

8 HPA Effect : Surface & PDA treatment dependency Mag. of g m Improvement [%] HfSiO HfO 2 HfAlO Chemical Oxide NO gas Anneal 2atm H 2 or 4 o C, 3min Surface prep. method NH 3 gas Anneal Mag. of g m Improvement [%] HfSiO HfO 2 None O 2 PDA method 2atm H 2 or 4 o C, 3min RTNO NH 3 Compared with FG annealing (48 o C 3min), improved G m was observed after high pressure annealing. Surface nitrided sample and RTNO PDA sample showed significant transconductance improvement after high pressure annealing. Part A

9 Lifetime extrapolation lifetime [sec] Vth 1mV shift monitored year lifetime Close : nfet Open : pfet FG anneal 5atm V 1year nfet pfet 1.31V 1.8V 1.44V 1.95V l1/v d l [V -1 ] Magnitude of improvement [ % ] H 2 5atm H 2 1atmH 2 2atm 5atm nfet Id Dit nfet ΔVth pfet ΔVth 1atm improve ΔV th [mv] degrade By optimizing the annealing gas ( ) and pressure (5atm), improved performance as well as longer device lifetime were achieved. Part A

10 Electrical characteristics after 1, 3, 1% annealing (1atm) Safety issue of pure deuterium gas for mass production system Capacitance [pf] Å ALD HfSiO/1Å ALD TiN Frequency: 1 KHz Size: 1*1 μm 2 EOT: 15.3Å V th :.52V V FB : -.52V Control 1% 3% 1% V g [V] improvement rate [%] NMOSFET 4 o C 3min Control 1% 3% ΔG m,max ΔI d,max 1% There is no change of EOT after annealing. Improvement of G m, I d.max after 1, 3, 1% annealing Part A

11 Charge pumping characteristics & Device reliability study N it [1 1 /Cycle*cm 2 ] Freqency: 5KHz Control 1% 3% 1% - ΔN it /N it,initial at max [%] % 3% 1% V Base [V] ΔV th [mv] Constant gate bias NMOSFET W/L=1/.4 2V 1.8V 1.5V Control Device 1% 3% 1% Stress Time [sec] Part A

12 Motivations of subsequent N 2 annealing Improvement of I d and g m,max observed after high pressure anneal However, degraded reliability characteristics observed in higher pressure annealed device. Excess hydrogen and deuterium in oxide play as a device degradation source To improve reliability characteristics after high pressure anneal, we employed subsequent annealing. Part A

13 Mobility & N it Mobility [cm 2 /Vsec] 2 HfO2 12Å L / W =.5μm / 1μm FG aneal H 2 1atm H 2 1atm + N 2 anneal N it [/cycle*cm 2 ] 3.x x x x x x1 1 V amplitude = 1.2V Freq. = 1MHz Duty 5% FG Anneal 1atm 1atm + 4 o C N 2 Anneal 1atm + 5 o C N 2 Anneal. 3.x1 5 6.x1 5 9.x x1 6 Effective field [V/cm] V base [V] After subsequent annealing, Improved I d and mobility does not changed. Subsequent annealing does not increase N it values. Subsequent annealing does not degrade device performance. Part A

14 Hot carrier degradation 1 FG Anneal HP Anneal HP + N 2 Anneal NMOSFET 5 4 Vth shift [mv] Gm/Gm [%] ΔV th [mv] L/W=.4μm/1μm HCI V g =V d Condition Stress Time [Sec] 1 Only HP N 2 4C N 2 5C After subsequent N 2 annealing, high pressure deuterium annealed sample showed significantly reduced V th shift. Part A

15 Model for hot carrier degradation TiN HfO 2 P-Sub. H-H H-H H-H H-H Before electron electron After : Passivated interface trap Concentration(atoms/cm 3 ) or near interface trap site by Hydrogen or Deuterium HfO 2 SIMS analysis: Charles Evans H-H : Remained hydrogen Before annealing Si After annealing O 2 D Depth(nm) after high pressure annealing Count per second Part A

16 Effect of fluorine annealing on High-k oxide nmosfet PMA/PDA F 2 annealing Appropriate F incorporation Excess F incorporation Poly-Si F F F F F F F F Diffusion into gate-oxide Reaction with Si-O bonds & Release oxygen atoms High-k O O F O F Reaction with Si Sidangling bond & Bonding Si-F at at Si/ Oxidize Si/ interface Si Sub. Si Si Strained Si-O Bond Si Si Strain Release Si Si Re-Oxidation (Wright et al.) F(Fluorine) effect Improvement of leakage current, breakdown voltage and hysteresis.< SSDM, pp , 24 > Improvement of the BT instability.< SSDM, pp2-21, 24 > Improvement of Q BD -distribution tails and reduction of the strained Si-O bond. < TED, VOL 5, NO 11, 23 > Part A

17 XPS analysis Spectra of F1s / XPS Depth profiling 1 HfO 2 Si substrate 1 F-Si: 685.5eV Atomic percent [ % ] O1s as HfO 2 Hf4f as HfO 2 Si2p as Si F1s by F 2 annealing Intensity [a.u.] Si-HfO 2 interface Si HfO Etch Time [ sec ] Binding Energy [ev] Conventional FGA was performed at 48 C for 3 min F 2 annealing at 4 C for 15 min (.7atm) Based on XPS spectra, we clearly observed fluorine related peak at Si-HfO 2 interface, which indicate fluorine incorporation. Part A

18 EOT & Mobility after F 2 annealing Capacitance [F] 16p 12p 8p 4p EOT 16.9Å N it [1E1/cm 2 ] NMOSFET W/O F 2 annealing F 2 annealing NMOSFET W/L = 1/ V base [V] V g [V] ΔV th [ mv ] ΔG/G mmax degradation [%] HCI stress / V g =V d NMOSFET W/L = 1/.25 Closed symbol: W/O F 2 annealing Open symbol: F 2 annealing F 2 annealing W/O F 2 annealing After 1sec HCS 1.5 Stress Voltage(V g =V d ) [V] V g =V d =2.V V g =V d =1.5V Stress Time [ sec ] 2 No change of equivalent oxide thickness after F 2 annealing. Fluorine treated sample showed improvement of HC reliability Improvement can be explained by Si-F bond which is stronger than Si-H bond. Part A

19 PBTI characteristics ΔV th [ mv ] o C 85 o C 25 o C Lifetime [sec] Closed symbol: W/O F 2 annealing Open symbol: F 2 annealing FN stress V g =1.5V W/L = 1/1. F 2 annealing W/O F 2 annealing E a =1.128 ev E a =.454 ev /kT [ev -1 ] Stress Time [ sec ] The incorporation of fluorine in the oxide effectively reduces the positive BTI effect. Activation energy (E a ) of HfSiO with additional fluorine annealing is significantly higher than that of control sample. Part A

20 Conclusions-part A Effects of high pressure annealing on Hf-based gate dielectrics Device performance improvement Significant mobility improvement was observed after HP anneal. Deuterium HP annealing improved hot carrier reliability. Device reliability with subsequent N 2 annealing. No change of I d, G m, interface trap density was observed. Improved device reliability by out-diffusion of bulk H 2. Effect of fluorine annealing Improved PBTI characteristics was observed. Part A

21 Outline A. Effects of high pressure annealing on Hf-based gate dielectrics Improvement of device performance Effect of deuterium concentration Device reliability with subsequent N 2 annealing Effect of fluorine annealing B. Effects of high Pressure H 2 annealing on SOI MOSFETs Improvement of bottom Si/ interface quality C. Effects of high Pressure annealing on Metal gate MOSFET Metal electrode dependent interface trap generation Mobility improvement with high pressure annealing Part B

22 Motivations Front Front interface (gate (gate oxide/si interface) Back Back interface (Si/Buried-Oxide interface) Poor Poor back back interface of of FDSOI FDSOI degrades electrical properties [1] [1] High Pressure hydrogen anneal [2] Reduce Reduce interface trap trap densities in in both both front front and and back back interface *References [1] J. Koga et al. atieee trans. Electron Devices 22 [2] H. Park et al. at IEEE Electron Device Letter 25 source PolySi channel e - Buried Oxide Si (back gate) drain - Front interface Improve electrical characteristics of of FDSOI FDSOI - Back interface Part B

23 GIST SOI MOSFET Process FGA HPHA 8 forming gas annealing 7 metallization Al Al n+ Si n+ BOX 1 cleaning 2 Active region define Si BOX Source BOX poly Si BOX Drain Ultra-thin body Silicon substrate 3 gate oxide & electrode deposition Si BOX 4 Gate patterning /Poly Si High-k (HfO 2 )/metal 6 High-k etching 5 PLAD + activation Si BOX Photo litho. E-beam litho. n+ Si n+ BOX n+ Si n+ BOX RTA Laser annealing Part B

24 IV characteristics of FDSOI (I) In the coupled condition (silicon film is fully depleted) I D [ μa ] 5nm SOI /PolySi nmosfet - W/L = 2um/2um 3. HP 25. FGA I D [ A ] 1E-3 1E-5 1E-7 1E-9 V D =.1V HP anneal 3 o C 2min 1atm FG anneal 4 o C 2min W/L = 2μm/2μm G m [ S ] 2.5x1-5 2.x x1-5 1.x V D [ V ] 1E-11 5.x V G [ V ] Driving current (at V G = 1.5V) Subthreshold slope G m_max Before HP 213μA 72mV/dec 5.36E-6 After HP 27 μa 63mV/dec 6.18E-6 Part B

25 IV characteristics of FDSOI (II) In the decoupled condition (back or front interface is in accumulation condition) 1E-4 1E-6 Decoupled condition : V BG = -3V W/L = 2μm/2μm V D =.1V 1E-5 1E-6 1E-7 Decoupled condition : V G = -2.V W/L = 2μm/2μm V D =.1V I D [ A ] 1E-8 I D [ A ] 1E-8 1E-9 1E-1 HPA 3 o C 2min 1atm FGA 4 o C 2min 1E V G [ V ] Front channel subthreshold characteristics 1E-1 1E-11 HPA 3 o C 2min 1atm FGA 4 o C 2min 1E V BG [ V ] Back channel subthreshold characteristics kt Cs + C fit kt Cs + Cbit S f = (ln1) [ 1+ ] S q C b = (ln1) [ 1+ ] q C f The effect of HP annealing on back interface is higher than that on front interface b Part B

26 Improved effective electron mobility (μ eff ) 1 T si = 5nm W/L = 2μm/2μm High Pressure annealing μ n_eff ( cm 2 V -1 s -1 ) HPA 3 o C 2min H 2 1atm FGA 4 o C 2min 1x1 5 2x1 5 3x1 5 E eff Field [ V/cm ] Reduced interface state density, front interface as well as back interface Reduction of coulomb scattering Mobility improvement Part B

27 Conclusion-part B High pressure annealing improves electrical characteristics of fullyf ully-depleted SOI MOSFETs FD SOI MOSFETs showed significant subthreshold slope improvement after high pressure annealing (63mV/dec ). The improvement of back side interface after high pressure annealing was confirmed with decoupled condition. Electron mobility is significantly improved because of reduction of coulomb scattering by high pressure hydrogen passivation. Part B

28 Outline A. Effects of high pressure annealing on Hf-based gate dielectrics Improvement of device performance Effect of deuterium concentration Device reliability with subsequent N 2 annealing Effect of fluorine annealing B. Effects of high Pressure H 2 annealing on SOI MOSFETs Improvement of bottom Si/ interface quality C. Effects of high Pressure annealing on Metal gate MOSFET Metal electrode dependent interface trap generation Mobility improvement with high pressure annealing Part C

29 Motivations Electrode dependent mobility characteristics Mobility [cm 2 /Vsec] Å Universal Ru TiN TaSiN 3Å μ Peak N it x1 5 1x1 6 2x1 6 Effective field [V/cm] 1 1 Ru TaSiN TiN Electrode Comparing with TiN, TaSiN and Ru electrode showed significant mobility degradations. Mobility characteristics are inversely proportional with interface trap density. Part C

30 Thickness dependent D it characteristics (Pure metal) D it [1 1 ev -1 cm -2 ] Mo electrode Ru electrode Poly Poly 2nm 2nm 4nm 6nm 8nm T SiO2 [Å] -d(c ox /C) 2 /dt Zerbst plot 6nm τ gen. Poly ~ 2.2 μsec Ru ~ 1.2 μsec Mo <.1 μsec C final /C-1 Strong electrode dependent D it characteristics are observed. Minority carrier generation time of Mo is significantly shorter than Ru or Poly electrode: Zerbst plot SIMS measurement on Mo electrode capacitor showed Mo atom diffusion into Si-substrate. Counts [sec] Depth [nm] Part C

31 Additional electrode material dependent D it C/Cox Ti TiN TiSiN TiAlN D it [1 1 ev -1 cm -2 ] Q bd [C/cm 2 ] 1 4 2nm TiN 2nm 6nm TiSiN V g [V] Poly TiN TiAlN TiSiN Electrode G p /ω [pf] TiN electrode 6nm 5x1-4 cm 2 -.2V V TiAlN electrode -.2V.5V Frequency [Hz] Comparing TiN, TiSiN, TiAlN showed CV curve stretch-out and single metal showed significant CV degradation. Conductance loss peak of TiAlN capacitor is higher than that of TiN capacitor. Part C

32 Additional annealing effect on D it C g [μf/cm 2 ] p.3 2p.2 As fabricated D it = 4.2x p Additional 8 o C 1min anneal d(c ox /C) 2 /dt Part C TiAlN / 6nm τ gen. <.1μs V g [V] τ gen. ~.53μs D it = 1.2x1 11 5p 4p C final /C-1 τ gen. ~ 2μs TiAlN/ 6Å Initial Additional 8 o C 9 o C 1min Gp /ω [F] D it [1 1 ev -1 cm -2 ] Counts [sec] 25 2nm As fabricated After 8 o C 1min anneal Poly TiN TiAlN TiSiN Electrode As Fab. Al Ti 9 o C 1min 8 o C 1min Counts [sec] 1 3 count 5nm As fab. 8C 9C Depth [nm] 1min anneal Al Ti

33 High pressure annealing effect I C g [μf/cm 2 ] TiSiN/ 2nm Open : FG anneal Close : HP 1atm anneal 1KHz.5 1KHz 1MHz V g [V] D it [1 1 ev -1 cm -2 ] FG Anneal HP 1atm Anneal Close : 2nm TiN TiSiN TiAlN Mo Electrode Open : 6nm G p /ω [pf] V FG anneal -.2V TiAlN electrode 6Å Area : 5E-4cm 2 HP 1atm anneal.5v -.2V After high pressure annealing, significant improvement of CV characteristics and conductance loss peak were observed Frequency [Hz] Part C

34 High pressure annealing effect II Mag. of μ improvement [%] Chem ox/ HfO 2 3nm Ru TaSiN TiN TaN TaSiN TiSiN Electrode Mobility [cm 2 /Vsec] Mobility [cm 2 /Vsec] TaSiN/ 2nm Ru/ 3nm FG Anneal L/W = 1μm/1μm HP 1atm anneal Effective field [MV/cm] Chem Ox./HfO 2 3nm TiSiN TaSiN 4 FG Anneal L/W = 1μm/1μm HP 1atm anneal Effective field [MV/cm] After high pressure annealing, both and HfO 2 showed mobility improvement. Part C

35 Conclusion-part C Effects of high Pressure annealing on Metal gate MOSFET Metal electrode dependent interface trap generation. Minority carrier lifetime (Zerbst plot) are measured to investigate the interaction between metal gate and gate dielectric Pure and ternary metal electrode showed high density of D it & significant mobility degradations Metal penetration into silicon substrate Mobility improvement with high pressure annealing. Metal induced N it generation can be cured by HP annealing. Part C

36 Thank you very much!!