2-inch polycrystalline silicon thin film transistor array. using field aided lateral crystallization

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1 2-inch polycrystalline silicon thin film transistor array using field aided lateral crystallization JAE HOON JUNG, MYEONG HO KIM, YOUNG BAE KIM a, DUCK-KYUN CHOI, Division of Materials Science and Engineering, Hanyang university, a Information Display Research institute, Hanyang university 17 Haengdang-Dong, Seongdong-Ku, Seoul KOREA Tel : , Fax : Abstract : This study presents a technique for fabricating polycrystalline silicon (poly-si) thin film transistors (TFTs) array from amorphous silicon (a-si) by field-aided lateral crystallization (FALC) method which utilizes Ni-catalyst and electric field during crystallization. We could uniformly crystallize a-si channels of 240 x 120 transistor array on 2-inch glass substrate by designing a unique common electrode connected to sources and drains. In order to enhance the uniformity, the current density flowing each cell was simulated. Raman analysis was done on the entire 2-inch array to confirm the crystallinity after the crystallization and it showed the identical Raman peak at 521cm -1 which is the characteristic value of crystalline silicon. The electrical properties of TFTs array turned out to be very uniform with the threshold voltage of 4.03V±0.25 and the subthreshold voltage slope of 1.18V/dec±0.45. Key-word : Low-temperature polycrystalline silicon (LTPS), field aided lateral crystallization(falc), thin film transistors(tfts), common electrode, uniformity, active matrix organic light emitting diode(amoled) 1. Introduction Low-temperature polycrystalline silicon (poly-si) thin film transistors (LTPS-TFTs) has been widely used as panel switching elements, panel array and peripheral driving circuit for System-On-Panel (SOP) due to its high field effect mobility (μ fe ), low threshold voltage (V th ), and low sub-threshold swing (S)[1]. Poly-Si TFTs integrated on the glass substrate permit high resolution, low power, low cost, reliable display such as liquid crystal display (LCD) and active matrix organic light emitting diode (AMOLED)[2]. In case of AMOLED, it is essential to acquire a low standard deviation of device parameters such as stability of threshold voltage and uniformity of crystallization in TFTs array. Many techniques have been studied during the last two decades to get poly-si having good qualities [3-4]. Among various techniques, we employed Ni-catalyst field aided lateral crystallization for fabricating 2-inch poly-si array. In this study, we applied uniform electric field to each pixel transistors through the judicious design of common electrode connected to sources and drains. After the fabrication of 2-inch TFT array, we measured device parameters such as field effect mobility(μ fe ), threshold voltage(v th ), sub-threshold slope(v/dec), onoff ratio and the positional deviation of properties was ISSN: Page 60 ISBN:

2 evaluated. In addition, the confirmation of crystallization of amorphous region and microstructural analysis of poly-si were performed. 2. Problem formulation The electrical field and Ni-catalyst are the crucial requirements for the crystallization for amorphous silicon (a-si) in field aided lateral crystallization (FALC) process. The schematic of FALC process is presented in Fig.1. The poly-si by FALC process resulted in good qualities such as high crystallinity, elongated grains along the transistor channel due to the directional crystallization, and smooth surface. Moreover, the poly-si thin film transistor fabricated by FALC process exhibits good device properties in many aspects, particularly in high field effect mobility (200.5 cm 2 /Vs)[5]. In order to fabricate poly-si TFTs (240 х 120) array on 2-inch glass substrate by the FALC process, the careful consideration has to be focused on the way to achieve uniform crystallization. In many cases, the resistance of metal common electrode lines connected to sources or drains can be a problem in applying a uniform electric field on channel region of the transistors in large panel. The inhomogeneity in the applied electric field to individual transistors, which will in turn cause non-uniform current density in each TFT cell, results in non-uniform crystallization of pixel transistor channels on 2-inch array. Therefore, it is essential to design a geometry of common electrode enabling a uniform voltage (uniform current) across the channel region.. 3. Problem solution. The design of metal line (common electrode) for FALC process has to be followed by the thorough understanding of total resistance of current path in the panel. MATHCAD program was employed to simulate the effect of the design parameters like geometry of electrode or number of the constituent cells. Total resistance of the current path is a sum of the resistance of a-si (channel) and that of metal line. By increasing the number of cells, total resistance decreased and the total resistance was dominated by the resistance of a-si. If the size of array is larger than 3 х 3, the connection of cells cannot be considered as a simple parallel circuit model because there exists two inputs and two outputs in the current path. Thus, a special transformation is needed to calculate the total resistance. In addition, we also took account the physical dimension of metal line and a-si in the simulation. After finding the total resistance, we calculated the current density per each cell on 2-inch array to design geometry of metal line. It is known that the current density should be higher than a critical current density to induce the crystallization of a-si by FALC process, and the critical current density was evaluated as 1.64х 10 3 A/cm 2 from the preliminary experiments. Fig. 1 Schematic of field aided lateral crystallization process. (500 4hr 30min, Ni-catalyst 10Å) ISSN: Page 61 ISBN:

3 Fig. 2 Configuration of common electrode and magnified image of crystallization showing the directional behavior. In order to reveal the directionality in crystallization by FALC, the photo image was taken from the partially crystallized transistor channel. Figure 2 shows the optimized geometry of metal line. Molybdenum was selected as a common electrode metal in the array. In Fig.2, the unique behavior of directional crystallization in FALC process is also shown. After the completion of the crystallization, the boundary between poly- Si and a-si will be driven to the + electrode side. Figure 3 presents the simulation result of the current density of individual cells in the array by MATHCAD. We can know that the current density depends on the location of the cell on 2-inch array, and the deviation can be less than 1%. By using optimized design of common electrode through simulation by MATHCAD, we could fully spectroscope (NRS-3100). Figure 4 shows the result of Raman peaks from the transistor channels at various locations on 2-inch array. All the peaks are identical in terms of the peak height and the peak position at 521 cm -1 which indicates the characteristic Raman shift peak of poly-si. This result reveals a uniform crystallization of a-si on 2-inch array. Figure 5(a) and 5(b) shows optical microscope image of the fabricated 2-inch poly-si TFTs array. All the TFTs have a channel geometry of 20μm /20μm (channel length/channel width) and transfer curve measured by semiconductor parameter analyzer (Agilient E5270B) implies that the properties of the transistors are quite similar and the deviation is not significant although the gate oxide quality is rather unsatisfactory. crystallize 240 х 120 cells on 2-inch array. And we fabricated polycrystalline-si TFTs of 240 х 120 array using FALC process. (a) (b) Fig.3 3-dimension simulation result of current density of each cell as a function of the position in the array. (By MATHCAD) After the crystallization of a-si layer (active layer) in array transistors, we carried out Raman analysis to confirm uniform crystallization using Raman Raman shift( cm -1 ) (c) (d) Fig. 4 Raman spectra reveal the uniform crystallization of channels on 2-inch poly-si array: locations of transistors evaluated are (a) top - left (b) top - right (c) bottom - left (d) bottom - right in array. ISSN: Page 62 ISBN:

4 Drain crruent(a) 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 (a) Gate voltage ( V g ) ( Row XColumn) 10X10 10X20 110X10 110X20 60X10 60X120 60X130 60X230 10X220 10X X X230 (b) Fig. 5 (a) Optical microscope image of 2-inch poly-si TFTs array, (b) transfer curves of poly-si TFTs array fabricated on 2-inch substrate. In Table 1, the summary of device parameters and deviation is presented. We could obtain uniform electrical properties such as field effect mobility of Conclusion In order to apply field aided lateral crystallization process to the next generation display like AMOLED device, it is essential to supply a uniform current density to each cell in the panel with the value higher than the critical one (1.64х10 3 A/cm 2 ). We could achieve this goal by employing common electrode with an optimized geometry after the simulation of current density at each cell on 2-inch array of 240 х 120. The poly-si crystallized by FALC process exhibits the identical Raman shift peak at 521 cm -1 regardless of the location in 2-inch TFTs array panel. The field effect mobility at the drain voltage of 0.5 V was 26.3cm 2 /Vs and standard deviation was less than 10%. We also confirmed the other electrical characteristics of TFTs are reasonably good in terms of the uniformity. Therefore, as a conclusion, we could demonstrate the FALC process is suitable for applying to AMOLED. cm 2 /Vs ± 3.3, threshold voltage of 4.03V ± 0.25, subthreshold voltage slope of 1.18V±0.45, and on/off ratio of 10 5 from transfer curves. The deviation deduced from the device parameters ensures that the values we realized meet the specification of the TFTs for the application to AMOLED since it requires V th variation of +/- 0.3V and the mobility variation of 10% [6]. Table 1. Summary of device parameters and deviation on 2-inch poly-si (240 х 120) array Device parameters Value deviation Field effect mobility (cm 2 /Vs) 26.3 ± 3.3 (9.7%) Threshold voltage (V th) 4.03 ±0.25 Subthreshold voltage (V/dec.) 1.18 ±0.45 On/off ratio 10 5 Reference [1] B.Y. Lee, Y. Hirayama, Y. Kubota, S. lmai, A. Imaya, M. Katayama, K. Kato, A. Ishkawa, T. Ozaki, K. Mutaguchi, and S. Yamazaki, A CPU on a Glass Substrate Using CG-silicon TFTs ISSCC 03, 2003, pp164~165. [2] Yue Kuo, Thin film transistors Materials and processes. Vol 2, p420,. [3] K.H. Kim, S.J. Park, K. S. Cho, W.S. Sohn, and J. Jang, Large-area poly-si on glass by UV can heating in SID Tech. Dig. 2002, pp150~153. [4] R.B. Inverson and R. Reif, Recrystallization of amorphized polycrystalline silicon films SiO 2 : temperature dependence of the crystallization parameters. J.Appl.Phys., vol 62, pp.1675~1681, [5] Hyun-woong chang, Hyun-chul Kim, Yu-hang Wang, and Duck-Kyun Choi, Fabrication of low temperature poly-si thin film transistor using field aided lateral crystallization process, Revista Mexicana de fisica S53(1), ISSN: Page 63 ISBN:

5 [6].Woo-Jin Nam, Jae-Hoon Lee, Sung Hwan Choi, Jae Hong Jeon and Min-Koo Han. New Voltage programming LTPS pixel scaling down Vth variation for AMOLED display, in SID. Dig. 2006, pp399~402. ISSN: Page 64 ISBN:

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