SURFACE MICROMACHINING

Transcription

1 SURFACE MICROMACHINING Features are built up, layer by layer on the surface of a substrate. Surface micromachined devices are much smaller than bulk micromachined components. Nature of deposition process height of features. LPCVD poly-si films can be only a few microns high. So surface micromachining cannot be useful in some sensors eg : accelerometers, since small proof mass, but ADLX05 accelerometer-( commercial) fabricated by surface micromachining. It has a proof mass of 0.3µg. LPCVD poly Si requires high temp annealing at 580 C to convert amorphous to poly. Mechanical properties of thin films Adhesion. Low residual stress. Low pin hole density. Good mechanical strength and chemical resistance. Film characteristics depends upon Deposition process. Growth conditions Post-deposition thermal processing (annealing). Orientation of the substrate. (surface, crystallinity ). Definitions: Structural layer: the layer of thin film material with which the microstructures are made of. Should have physical and chemical properties that are suitable for the desired application Mechanical properties such as high yield and fracture stresses, minimal creep and fatigue, and good wear resistance Sacrificial Layer: The layer of material used during the fabrication process to deposit microstructures. These are removed towards the end of the fabrication. So, the layer has no role in the operation of the device. Good mechanical properties so that device does not fail while fabrication Good adhesion Low residual stresses Polysilicon is usually used as a structural material. Disadvantages of poly Si (over single crystal Si) Lower yield strength (2 to 10*less) Lower piezo resistivity (less useful in sensors) Significant variation in the Young s modulus(& hence the performance of the device) Stiction. Advantages: Non-crystallinity o simpler design, o less of dimensional uncertainities. Note : Thin films have very high surface to volume ratio. Therefore properties are influenced more by surface properties.

2 Comparison of Bulk micromachining with surface micromachining Bulk Micromachining Large Surface Micromachining Small Size, thickness (and mass) of features Use of wafers Both sides Multiple layers on one side Vertical dimensions One or more wafer thickness Limited by thickness of deposited layers (~2µm) Wafer bonding Required Usually not used Common sensing mechanism Piezoresistive/capacitive Resonant/capacitive Criticality towards end of Thinned wafers may be process fragile Integration with IC technology Not very much Can be made IC compatible Utmost cleanliness required to protect the structure Comparison of bulk micromachined and surface micromachined absolute pressure sensors equipped with piezoresistive elements. ( Top ) Bulk micromachining in single-crystal Si. (Bottom ) Surface micromachining with poly-si.

3 Process sequence for a cantilever by surface micromachining Basic surface micromachining process sequence. ( A ) Spacer layer deposition ( the thin dielectric layer is not shown ). (B) Base sputtering with mask 1. (C) Microstructure layer deposition. (D) Pattern microstructure with mask 2. (E) Selective etching of spacer layer. 1. Sacrificial layer ( spacer layer/ base) is deposited on Si substrate coated with a dielectric buffer/ isolation layer. Phosphosilicate glass ( PSG ) is a good choice for sacrificial layer.(etches faster than SiO 2 in HF) 2. Mask 1 Base is patterned with a mask, windows are opened up in the sacrificial layer. 3. Structural thin film ( poly/metal/alloy ) is conformably deposited. 4. Poly Si is annealed in a furnace at 1050 C in N2 for 1 hr to reduce stress. (RTA can also be used.) 5. Mask2 Structural layer is patterned.( dry etching is CF 4 +O 2 or CF 3 Cl +Cl 2 plasma ) 6. Selective wet etching of sacrificial layer is 49% HF Free standing micromechanical structure. Fabrication steps details 1. Pattern transfer to SiO 2 buffer layer. 1. Blanket n+ diffusion of the Si substrate to define a ground plane. 2. Passivation of the substrate with a 0.15µm thick LPCVD nitride on a 0.5µm thermal oxide. 3. To pattern thin layer : ( for contact pads ) a. 1µm thick resist. b. Isotropic etch with buffered HF ( 5 parts NH 4 F + 1 part HF )SiO nm/min, c. etch process is monitored optically by observing hydrophobic / hydrophilic nature. d. Contact pad will have dimension L m +2 t SiO 2 Lm = mask dimension Resist is stripped 2. Base layer ( sacrificial ) deposition and etching 1. LPCVD of PSG 2µm. 2. PSG by adding phosphorous to SiO 2 improved etch rate Controlled window taper. Easier to make poly layer.

4 3. PSG is densified at 950 C for 30min Conductive ( phosphorous goes up as dopant ) Windows in the base layer for anchoring structures. 3. Deposition of structural material by CVD.(or sputtering PVD) Poly Si : LPCVD ( Pa) in a furnace at 600 C from pure Silane. SiH 4 Si+2H 2 Typical process conditions are 605 C, 73 Pa ( 550 mtorr ). Flow rate : 125 sccm 100Å/min. To make the structure conductive, dopants are introduced (along with Silane) or by ion implantation. Other structural materials : Al, SiO 2, Si 3 N 4, Silicon oxynitride, polyimide, diamond, SiC, sputtered Si, GaAs, Tungsten, α-si:h, Ni, W. 4. Structures are patterned by RIE in SF 6 plasma. 5. Selective etching of spacer material. Structures are freed from substrate by undercutting of the sacrificial layer. Immersed in HF solution to remove sacrificial layer, PSG is removed by concentrated/ dilute / buffered HF. To shorten etch time, extra apertures are usually provided in the structure. Thicker layers etch faster. Material combination for etchant / spacers /structures Etch rates in 1:1 HF: HCl for various types SiO 2 Thin film properties to be considered Adhesion ~ Very important requirement, for performance and reliability of IC s. Tests: Scotch tape test Abrasion method.

5 Scratching. Pulling. Bending. Factors affecting adhesion: Cleanliness of the substrate. Surface roughness more surface area. A layer of an oxide forming element improves adhesion since Cr, Ti, Al etc are used as anchors for subsequent metallization. Stress in thin film It causes Film cracking. Delamination. Void formation. due to mismatch of thermal expansion itself. Non-uniform plastic deformation. Substitutional / interstitial impurities. Growth process. Al films are usually stress free. Tungsten accumulates more stress when sputter deposited. Common Material Systems Poly-Si/SiO 2 LPCVD deposited poly as structural layer Thermal or LPCVD oxide as sacrificial layer Oxide dissolves in HF, and not poly. Both materials are used in IC fabrication. So deposition and etching technologies are matured Poly has good mechanical properties. Its electrical properties can be improved by doping Material systems are compatible with IC processing Along with these, nitride can be used for insulation Silicon Nitride/Poly-Silicon LPCVD nitride is used as structural layer; Poly Si as sacrificial layer Anisotropic etchants such as EDP r KOH can dissolve poly. Tungsten/SiO 2 CVD tungsten as the structural layer; Oxide as sacrificial layer HF for etchant Polyimide/Aluminum Polyimide as structural layer, aluminum as sacrificial layer Acid based etchants to etch aluminum Polyimide has small elastic modulus Can take large strains Both can be fabricated at low temperatures <400 C Stiction during release Large area structures tend to deflect through stress gradients or surface tension induced by liquids and attach to the substrate / isolation layer during the final rinsing and drying step. Stiction may be related to o hydrogen bonding. o Residual contamination. o Vander waal s forces.

6 Solutions : Creating stand-off bumps on the underside of Poly Si. Use of sacrificial polymer columns ( along with oxide ) use isotropic oxygen plasma to etch the polymer after oxide etch. Reduce surface tension of the final rinse solution. Freeze drying. Super critical drying CO 2 at 35 C, 1100 psi. In-use stiction Attempted solutions By forming bumps. Roughening opposite surface faces. Making Si surface hydrophobic. Sacrificial wet etch systems for III-V compound heterostructures Stopping Layer Sacrificial Layer Etchant Selectivity, etch rates a [µm/min] GaAs Al x Ga 1 x As, x 0.5 HF:H 2 O cs b and high etch rates Al 0.5 In 0.5 P HCl:H 2 O cs and high etch rates In 0.5 Ga 0:5 P HCl:H 2 O cs and high etch rates Al 0.5 Ga 0.5 P HF:H 2 O cs, 0.3 Al x Ga 1 x As, GaAs NH 4 OH:H 2 O 2 > 100, 5 (spray) x 0.40 Al 0. 3 Ga 0.7 As GaAs succinic acid: NH 4 OH cs, 0.2 GaAs C 6 H 8 O 7 : H 2 O 2 : H 2 O 116, 0.3 In 0.2 Ga 0.8 As C 6 H 8 O7 : H 2 O 2 : H 2 O 121, 0.3 AlAs In 0.53 Ga 0.47 As succinic acid: NH 4 OH > 1100 c, 0.1 In 0.53 Al 0.47 As do > 550 c, 0.06 InP In 0.53 Ga 0.47 As FeCl 3 :H 2 O cs(?), 0.7 C6H 8 O 7 : H 2 O2 : H 2 O 473, 0.2 In 0.53 Al 0.47 As C 6 H 8 O 7 : H 2 O 2 : H 2 O 102, 0.02 GaAs C 6 H 8 O 7 : H 2 O 2 : H 2 O 960, 0.3 Al 0.3 Ga 0.7 As C 6 H 8 O 7 : H 2 O 2 : H 2 O 486, 0.2 In 0.53 Ga 0.47 As HF:H 2 OO 2 :H2O cs(?) and slow etching In 0.53 Ga 0.47 As In 0.53 Ga 0.13 Al 0.34 As, HCl:H 2 O > 329 c, 0.1 In 0:53 Al 0:47 As HCl:H 2 O > 1944 c, 0.6 InP HCl:H 2 O cs and high etch rate InAs AlSb HF cs and high etching rate Al 0.5 Ga 0.5 Sb InAs C 6 H 8 O 7 : H 2 O 2 : H 2 O > 3850 c, 0.1 GaAs C 6 H 8 O 7 : H 2 O 2 : H 2 O > 13,650c, 0.3 GaAs 0.85 Sb 0.15 C 6 H 8 O 7 : H 2 O 2 : H 2 O > 3789 c, 0.1 a The etch rates are most often given for the etch rate down into the {100} plane, and can only serve as guidance. In some cases the anisotropy may be very large. b Here, complete selectivity (cs) means selectivity above In these cases, selectivity may, in practice be regarded as complete in nearly all technological applications. c complete selectivity approached.the measurements were made within this accuracy.

7 Wafer Bonding Bonding can be used to assemble individually micromachined components. This offers the possibility of 3D structures which are even thicker than one wafer. Anodic Bonding Anodic bonding is also called field-assisted thermal bonding, electrostatic bonding, etc. This technique is typically done between a sodium glass and silicon for MEMS. For the anodic bonding, a cathode and an anode are attached to the glass (or silicon with glass thin coating) and silicon wafer, respectively, voltages applied ranged from 200 to 1000 V. At the same time, the anode is put on a heater providing the bonding temperature around C. During the bonding, oxygen ions from the glass migrate into the silicon resulting in the formation of silicon dioxide layer between silicon wafer and glass wafer and form the strong a strong and hermetic chemical bond. The advantage of anodic bonding for MEMS is that the low temperature used can ensure the metallization layer (Aluminum) could withstand this temperature without degradation. Anodic bonding is also used to seal two silicon wafers together by using a thin sputter-deposited glass layer. The equipment used in this case is basically a heat chuck element with an electrode capable of supplying high voltage across the structure to be bonded. The system automatically controls the temperature and power supply during the bonding process. Cathode - V + Glass Silicon Anode (heater) After surface cleaning and polishing, one of the wafers (referred to here as the top wafer) is initially coated with a glass film a few microns thick. The top wafer is placed on top of a second silicon wafer (referred to as the support wafer) for these two wafers to be bonded. The support wafer rests on an aluminum chuck. The two wafers are usually sealed together by anodic bonding at temperatures less than 400 C with an electrostatic DC voltage of 50 to 200 V. The negative electrode is connected to the top sputter-coated wafer. The voltage should be applied over sufficiently long time (10 to 20 minutes) to allow the current to reach a minimum steady state level. This bond process usually takes place in air at atmospheric pressure. Direct Bonding Direct bonding is also called silicon fusion bonding, which is used for silicon-silicon fusion bonding. Direct bonding is based on a chemical reaction between OH-groups present at the surface of native silicon or grown oxides covering the wafers. The direct bonding usually follows three steps: surface preparation, contacting and thermal annealing. The surface preparation step involves cleaning the surfaces of the two wafers to form a hydrate surface. The wafer surface should be mirror smooth, the roughness should be no greater than 10 A, and the bow of a 4 wafer should be less than 5 micron to achieve the necessary flatness. Following this preparation, the wafers are aligned and contacted in a clean room environment by gently pressing the two wafers at the surface central point. The surface attraction of the two hydrated surfaces creates an intimate contact over the entire wafer surfaces. At room temperature, these wafers adhere via hydrogen bridge bonds of chemisorbed water molecules that subsequently react during the annealing process to form Si-O-Si bonds. Consequently wafer pre-treatment procedures such as hydrophilization steps (wet cleaning processes, plasma hydrophilization), assist the bonding process. The final step in direct bonding is to anneal the bonding from the room temperature to 1200 C. This anneal process increases the bond strength by more than one order of magnitude at the temperature as high as C. But the high temperature annealing is not allowed for the metalized wafers. The direct bonding prevails in the high-strength bonding, and the devices dimensions design could be scaled down if direct bonding approaches other than anodic bonding. Some low temperature direct bonding processes are to be further developed. In the last decade several groups have demonstrated that the fusion of hydrophilic silicon wafers is possible for obtaining silicon-on-insulator (SOI) materials. Since then, wafer bonding techniques have found various applications in the field of microelectronics such as in static random access memory (SRAM), CMOS, and

8 power devices. For micromechanical applications, fusion bonding rendered possible the fabrication of complex structures by combining two or more patterned wafers. This section describes the principles and processes of wafer fusion bonding for fabrication of MEMS device. Three ranges of annealing temperature are of interest in wafer bonding: 1. Temperature less than 450 C for post-metallization wafers. 2. Temperature less than 800 C for wafers with diffusion dopant layers (e.g., p+ etch-stop layers). 3. Temperature greater than 1000 C for wafer bonding before processing. According to the reaction mechanism, annealing at temperatures above 1000 C for several hours should result in an almost complete reaction of the interface. A 1000 C anneal for about 2 hours gives sufficiently high bond strength for all subsequent treatments; it is not possible to separate the two bonded Si wafers without breaking the silicon. Although high temperature annealing increases the strength of the bond, this step (usually if the temperature is above 800 C) may introduce problems, such as doping profile broadening, thermal stresses, defect generation and contamination. Annealing also prevents the use of bonding technology for compound semiconductor materials since their dissociation temperature is often low. In addition, post-metallization bonding also requires bonding temperatures that are less than 450 C since most of the common metals used in device fabrication melt below this temperature. Therefore, in order to make full use of the potential provided by wafer bonding for microstructures, low temperature bonding methods have to be developed. A major concern of all bonding processes is the presence of non-contacting areas which are generally called voids. Voids are mainly caused by particles, organic residues, surface defects, and inadequate mating. Therefore both the surfaces being fusion-bonded have to be perfectly smooth and clean since the smallest of particles could cause large voids. Optimized processing includes wafer surface inspection, surface pre-treatment (hydrophilization, cleaning), and mechanically controlled, aligned mating in a particle-free environment. Intermediate layer assisted bonding This type of bonding for MEMS requires an intermediate layer, which can be metal, polymer, solders, glasses, etc., to fulfill the bonding between wafers. One of the earliest wafer bonding eutectic bonding utilized Au as the intermediate layer for Si-Si bonding for pressure senso. The Au-Si eutectic bonding takes place at 363 C, well below the critical temperature of metallized Al layer. But the stress generated during bonding was found significant and introduce the sensor drift. Polymers as intermediate layer for bonding prevails in very low temperature, reasonable high strength, no metal ions present, low stress due to the elastic property of polymers, etc. Usually, UV photoresists such as polyimide, AZ-4000, SU-8, PMMA, and other UV curable cross linked polymer. The disadvantage is that the bonded device with polymer may not hold the hermetic sealing performance due to the relatively high permittivity of polymers. Glasses with low melting temperature as intermediate layer for the bonding is also demonstrated, where a layer of glass frit is usually deposited on the silicon wafer. The flatness of the deposited frit layer is critical to obtaining uniform, strong, low-stress bonding. The screen printing of glass frit was used for pressure sensor bonding and exhibit good performance. Bonding of Silicon-based Materials Fusion bonding of polysilicon, silicon dioxide, or silicon nitride to silicon proceeds in a manner similar to silicon-to-silicon bonding. For examples, to bond polysilicon to silicon, a polishing step for the two surfaces to be bonded is necessary to produce two smooth defect-free surfaces. The bonding mechanism is mostly identical to silicon-to-silicon fusion bonding in that in both cases Si-OH groups are present at the surface. Thus pretreatment (hydrophilization) and annealing conditions are similar. Because of the dissimilar mechanical characteristics of the different bonded materials, the yield of void free wafers can be significantly reduced by wafer bow or defects caused by stress during thermal treatment. Bonding of wafers covered with a thin thermal oxide or a thin silicon nitride results in homogenous bonded wafers, while oxides with thicker oxide (or nitride films) generally developed voids. High Aspect Ratio Processes: LIGA Process Even as miniaturization is immensely increased by silicon surface micromachining, the small sizes/masses created are often insufficient for viable sensors and, particularly, actuators. The problem is most acute in capacitive mechanical micro sensors and capacitively-driven micro actuators because of the low coupling capacitances. Deep etching techniques, such as LIGA, have been developed in order to address this problem.

9 High aspect raio small lateral dimensions compared to thickness Thick structures offer better rigidity in the direction normal to the plane of the substrate. LIGA is a German acronym for Lithographie, Galvanoformung, Abformung (lithography, galvanoforming, molding). This versatile technique was developed by the research Center Karlsruhe (Germany) in 1986 using X- ray lithography for mask exposure, galvanoforming to form the metallic parts and molding to produce microparts with plastic, metal, ceramics, or their combinations. A schematic diagram of the LIGA process flow is shown in figure below. The X-ray LIGA relies on synchrotron radiation to obtain necessary X-ray fluxes and uses X-ray proximity printing. Inherent advantages are its extreme precision, depth of field and very low intrinsic surface roughness. With the LIGA process, microstructures height can be up to hundreds of microns to several millimeters, while the lateral resolution is kept at submicron due the advanced X-ray lithography. X-ray lithography for various feature sizes. Photon energy range Exposable resist (PMMA) thickness Membrane thickness Low aspect ratio nano structures High aspect ratio nano structures High aspect ratio micro structures High aspect ratio cm structures 500 ev 2 kev 2 5 kev 4 15 kev >15 kev <5 µm <50 µm <1 mm <2 cm SiC: 2 µm Diamond: 5 µm Be: 20 µm Be: 50 µm D263: 5 µm Be: 300 µm D263: 15 µm Be: 500 µm D263: 50 µm Absorber (Au, W) nm 500 nm to µm µm thickness 10µm Proximity contrast <10 db db db >20 db Development time s min min h h day days Application Rapid mass production of nanostructures 2D photonic crystals Micromechanics, micro-optics Various materials can be incorporated into LIGA process allowing electric, magnetic, piezoelectric, optic, insulating properties of sensors and actuators with a high-aspect ratio, which are not possible to make with the silicon based processes. Besides, by combining the sacrificial layer technique and LIGA process, advanced MEMS with moveable microstructures can be built (see figure). However, the high production cost of LIGA process due to the fact that it is not easy to access X-ray source limits the application of LIGA. Another disadvantage of LIGA process relies on that fact that structures fabricated using LIGA is not truly three dimensional, because the third dimension is always in a straight feature. The quality of fabricated structures often depends on secondary effects during exposure and effects like resist adhesion. A similar technique, UV- LIGA, relying on thick UV resists is useful fabrication with less precision. Modulating the spectral properties of synchrotron radiation, 3-D components with different size regimes can be fabricated using X-ray lithography. Considerations for these cases are shown in the Table.

10 PMMA is used as the x-ray resist. Wavelength of x-ray ~ 0.2nm Resist layre can be made as thick as 1mm in one exposure. So structures with thickness of several hundred microns, and aspect ratio of 100 can be achieved Synchrotron is a VERY expensive source for high energy x-ray. PMMA is used as a plastic template to plate metal through the opening Subsequest production be replicating cost effective mass production is possible. Plastic microstructures can be fabricated. LIGA Process LIGA based fabrication procedures of various systems for micromechanics, (such as micromotors, microsensors, spinnerets, etc.) and micro-optics, micro-hydrodynamics, microbiology, medicine, biology, and chemistry (microchemical reactors) are under various stages of development. A comparison of LIGA with bulk and surface micromachining technologies used in MEMS is given below.

11 Various technologies used in MEMS fabrication. Bulk (100) Surface LIGA wafer Maximum structure thickness Wafer thickness <50µm <500µm Planar geometry Rectangular Unrestricted Unrestricted Minimum planar feature size 1.4 x depth 1µm 3µm Side-wall features slope Limited by dry etch 0.2µm runout over 400µm Surface and edge definitions excellent Mostly Very good adequate Material properties Very well Mostly Well controlled controlled adequate Integration with electronics Demonstrated Demonstrated Difficult Capital investments and cost Low Medium High Combination of LIGA process and sacrificial layer process.