Vertical Group IV Nanowires: Potential Enablers for 3D Integration and BioFET Sensor Arrays

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1 Vertical Group IV Nanowires: Potential Enablers for 3D Integration and BioFET Sensor Arrays Paul C. McIntyre Department of Materials Science & Engineering Geballe Laboratory for Advanced Materials Stanford University Acknowledgements: H. Adhikari, I. Goldthorpe, H. Jagannathan, H. Kim, and J. Woodruff Prof. s C.E.D. Chidsey and Y. Nishi DARPA 3DIC Program, MARCO MSD Center

2 Ge Nanowire FET with HfO 2 Gate Dielectric Top view SEM ALD HfO 2 Coating of Ge NW SiO 2 Source Drain ~20 nm single crystal Ge wires VLS CVD temperature: 275 C First try depletion mode PMOS showed great promise; µ p > 500 (Wang, Wang, Javey, Tu, Dai, Kim, McIntyre, Krishnamohan, Saraswat, Appl Phys. Lett, 22 Sept. 2003) Promising electrical elements for 3D integration on CMOS Need reproducible, directed NW growth

3 3-D Integration 2D Area = A Very Long Wire 3D A/2 Number of Interconnects A/2 Shorter Wire (Log-Log Plot) Wire-length 2-D IC 3-D IC 2-D System 3-D System Integration of heterogeneous technologies possible, e.g., memory & logic, optical I/O Reduce chip footprint Replace long horizontal wires by short vertical wires Interconnect length and therefore R, L, C Power reduction Delay reduction Slide courtesy of K.C. Saraswat

4 Comparison of 3D Technologies Monolithic Stacking vertical interconnect pitch > 200 nm vertical interconnect density < 25M/mm 2 Use vertical Ge NW diodes and/or FETs as programmable interconnects which transfer single crystal perfection of underlying semiconductor to overlying Ge device layers low temperature VLS growth. Wafer Stacking vertical interconnect pitch > 5µm vertical interconnect density < 40,000/mm 2 Chip Stacking vertical interconnect pitch > 50µm vertical interconnect density < 20/mm or 400/mm 2

5 Low-Temperature, Vapor-Liquid-Solid (VLS) Growth of Ge Nanowires C C Temperature/ C 28 Au Atomic Percent Germanium Ge 361 C eutectic Ge NW s grown by catalyzed chemical vapor deposition from a GeH 4 precursor GeH 4 decomposes preferentially on Au nanoparticle surface; Au catalyst melts forming a Au-Ge eutectic liquid Liquid catalyst stays on NW tip during growth Directed vertical Ge NW growth on HF-last <111> Si (epitaxy) Au Nanoparticle Ge Nanowire Ge Containing Vapor Slide courtesy of J. Woodruff and H. Jagannathan

6 Crystalline Orientation of Vertical Ge-NWs on Ge (111) (a) (311) ( 111) (c) (d) (311) ( 111) (220) (220) (131) (131) (b) (e) 50nm 10nm a) <111> oriented vertical growth of GeNWs, streaking due to finite lateral size of NWs b) Dark field image formed from (111) reflection from the diffraction pattern c) Atomically-abrupt interface between Au catalyst and GeNW after growth d) Microbeam diffraction pattern from a single NWs e) (111) lattice spacing in NW (H. Adhikari et al., Nano Lett., Feb. 2006)

7 Selective Gold Catalyst Removal and Deposition of Si- Shell/Ge-Core Vertical Heterostructure NWs a) High yield of vertical Ge NWs achieved on Si (111) wafers: 400 C wire nucleation followed by 280 C wire growth. b) Iodide-based wet etch to remove Au catalysts from Ge NW tips after CVD c) > 500 C conformal CVD of Si cladding around Ge NW to form core/shell structure d) Promising for high performance PMOS NW devices (I. Goldthorpe et al., to be published.

8 Ideas for a Vertical Surround Gate Transistor with Nanowires *H. T. Ng et al. Nano Lett. 4, 1247 (2004). Salient Features Provides the best gate control A highly scalable device Gate length is independent of lithography, but need controlled placement Compact device; small cell area Enables device design and study of FET devices operating in small dimensions Complicated gating diodes simpler

9 Nanowire FET Sensors Adsorbed molecular charge changes the local conductivity of a semiconductor NW channel Very small semiconducting wires; therefore, small amount of charge can strongly affect conductance Highly sensitive to local charge Si nanowire (5-50 nm dia.) devices have been demonstrated Functionalize with specific capture agents for chemical selectivity horizontal semiconductor NW conductance = G 0 Source Drain charged molecule conductance = G 0 -δg Source Drain local conductance gated by charge of molecule; could increase or decrease depending on doping

10 Silicon Nanowire Bio-FET SiNW s functionalized with biotin Streptavidin (SA) binds to the biotin Plot B: region 1- buffer; region nm SA, region 3- buffer again; about a 3% conductance increase Once bound, SA doesn t come off Plot C: unmodified SiNW; no conductance change with added SA; means little non-specific binding Relatively small changes observed Need to get charges closer to the surface! Electrostatic screening makes distance very important Possible to use an antibody as a capture agent. Cui et al., Science 293, 2001, 1289 Conductance change upon binding SA Ultimate detection limit ~25 pm Strepavidin

11 NW Array Fabrication Concept Grow vertical doped NW array by epitaxial CVD of Si <111> wires - NW length can be varied, as desired: 500 nm to 5 µm Grow RTN Si oxynitride or ALD high-k (e.g. TaOxNy/HfO 2 ) gate insulator conformally around NWs Fill array with LTO, CMP to prepare flat top surface, deposit continuous drain top contact (e.g. Ni) and wet etch to remove LTO through flow channels Extremely high NW sensor surface area for detection continuous drain contact channel containing aqueous solution Si(111) vertical Si NW array heavily-doped Si substrate (source)

12 NW Surface Functionalization Antibody Capture Agents ~20-30 nm Highly specific binding for biomolecule detection Oxide surfaces can be functionalized Large size of antibodies weakens electrostatic interaction of bound biomolecule with Si surface We will investigate both antibodies and smaller nanobodies Passivation of Non-Specific Binding Poly(ethylene oxide) and other molecules can be deposited as self-assembled monolayers that block protein binding on solid surfaces We ll initially study SAM deposition from solution around antibody capture agents on planar Si Bio-FETs - extend this work to NWs subsequently

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14 Sub-400 C Vertical Ge NW Growth for Transfer of Single Crystallinity Au catalyst isolated on Si within 25 nm thick SiO 2 Catalyst such as Au/Ge eutectic in via Single crystalline Ge seed Ge CVD homoepitaxy Liquid phase epitaxy of GOI VLS Growth of Ge or Si SiO 2 Si(111) VLS-Grown Ge or Si NW Si(111)

15 Apparatus for Ge Nanowire Growth Schematics of cold-wall NW growth reactor Thermocouple Reader PID Temp Controller Converted cold-wall SiGe epi reactor to low temperature NW CVD growth system Cold wall, lamp heated CVD reactor a) 11 independent gas flow channels for different gases (SiH 4, GeH 4, B 2 H 6,PH 3, H 2 ). b) accommodate whole wafers (up to ~6 wafers)

16 Synchrotron PES from Ge NWs: Surface Passivation Normaized Intensity Ge 0 3d 5/2Ge 0 3d3/2 oxide shifted Ge peak 13.0hrs 4.3hrs 2.3hrs 1.0hrs no HCl exposure Counts HCl exposure during NW growth After 1hr After 2hrs After 4hrs After 1day 0.6hrs 0.3hrs 0.0hrs Binding Energy(eV) Binding Energy Observations: 1. As grown nanowires have no oxide shifted Ge 3d peak. This suggests that wires are hydrogen terminated immediately after growth. 2. Oxide-shifted Ge peak starts appearing and increases when wires are exposed to atmosphere implying that wires are progressively growing oxide with time. 3. HCl exposure during NW CVD appears to produce a Cl passivation that is more stable than H-termination of cold-wall CVD-grown Ge NWs H. Adhikari et al., APL 2005

17 VLS Nucleation vs. Growth K K Temperature bulk eutectic nucleation (0.28,633K) eutectic growth eutectic Au Au-L Liquid Ge-L Bulk/Bulk NP/NW NP/Bulk X Ge Ge NW epitaxy not observed when deposition initiates at T sub < 350 C Gibbs-Thomson pressure should act on metal catalyst nano-particle and metal-ge liquid droplet for both NW nucleation and growth Capillary pressure may act on Ge only during NW growth - in homoepitaxy, Ge surface is flat as VLS is initiated (as NW nucleates ) Expected result is a lower temperature for single-crystal Ge NW growth than for nucleation, as observed Ge

18 Gate Insulator Stability As-deposited HfO 2 =28Å HfO 2 Chemical oxide Si Chamber wall Quartz view port Wafer holder Resistive heater stage 3 Wafer Pump 12 Quartz tube (30mm diameter) ICP Plasma Source Advanced Energy LB 1501 RF Plasma Generator (~2.4MHz) Remote ICP source for radical-enhanced ALD of TaO x N y gate insulator films Ar,N 2,H 2,O 2 MFC High-k dielectrics (metal oxides and insulating metal nitrides) increase Bio-FET electrostatic sensitivity compared to SiO 2 or Si 3 N 4 dielectrics However, permeability to H 2 O and ions in aqueous solution may be a problem We will explore TaO x N y /HfO 2 /SiON/Si gate insulator stacks to provide high capacitance density with nitride layers that should reduce in-diffusion of species from solution Initial studies on planar Si Bio-FETs and subsequent application to NWs