III-V heterostructure TFETs integrated on silicon for low-power electronics

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1 In the Quest of Zero Power: Energy Efficient Computing Devices and Circuits III-V heterostructure TFETs integrated on silicon for low-power electronics K. E. Moselund, M. Borg, H. Schmid, D. Cutaia and H. Riel IBM Research Zurich, Switzerland

2 The Power Challenge Consumption Transistor 0.4uW Human brain 20 W Smartphone 5 W Solar panel 230W µ-teg 16mW IBM Watson 80 teraflops 80 KW IBM sequoia 16 petaflops 8 MW Pro-cyclist 400W Google s server farms ~600 MW Wind turbine 6 MW Nuclear reactor 1.2 GW Generation Three Gorges Dam: 22.5 GW Energy efficient electronics needed 2

3 Low power electronics P tot V 2 C Vdd f active I Leak Vdd leakage Reduce I Leak, Reduce V dd NEMS CNT 10 µm I D (log) V th = I off Slope = 60mV/dec. DV dd MOSFET Steep Slope Device GNR FET GND In Tunnel FET VDD Out Ferro-FET V th V th V dd V dd V GS III/V FETs InAs Spin Torque Switch Steep subthreshold slope can decrease V th to reduce V dd 100 nm W BCB Domain wall switching 3

4 Role within EU Project - E 2 Switch IBM Goal: Fabricate III-V heterostructure high-performance p- and n-type TFETs integrated on. Use our platform to realize needed scaling of devices sub-20 nm diameter p-type device: /InAs n-type device: Ga(As)Sb/In(Ga)As Tunable effective band gap, latticematched. High on-currents already demonstrated (Lund, Notre Dame, Penn State). SS & I off level still a question mark. Big challenge: Demonstrate co-integration of p- and n-devices n p 4

5 Outline Optimization of the TFET: III-V heterostructures III-V on technologies Templated-assisted InAs NW growth InAs Vertical InAs- NW tunnel FETs Tunnel FET benchmarking Outlook 5

6 How to optimize the TFET Increasing Ion l: Electrostatics NW, high-k, doping profiles E g, m*: materials based Ge/InAs source on, III-V heterostructures GAA Abrupt High-k doping Low thermal budget Late 1990 s 2003 III-V heterostructures InAs No catalyst 6

7 Merits of III-V General benefits High electron mobilities Optically active Tunable bandgap by composition Quantum phenomena start at larger dimensions Particular to tunnel FETs Heterojunctions E G tailoring Staggered or broken gap configurations A. Pethe, et al. IEDM 26.3,

8 Methods for III-V integration on Buffer layers Gradually accommodate strain Bonding Grow on III-V substrate Transfer layer to Czornomaz et al. IEDM 2013 Epitaxial lateral overgrowth Mask the substrate and overgrow the mask with III-V. Aspect ratio trapping (ART) Grow III-V in deep trenches. Threading defects terminate on trench walls. But only in one direction! Nanowire growth Small interface to limits amount of defects and their propagation. Zhou et al. IEDM 2012 Wierzbicka et al. JAP 2009 Waldron et al. ISTDM 2012 Björk et al. JCG

9 III-V nanowire growth techniques Vapor-Liquid-Solid method Selective area epitaxy No Metal impurities Easy position control Small aspect ratio Stacking-faults Limited to [111] Radial overgrowth Nucleation at edge Radial overgrowth High aspect ratio Possible to achieve high crystal quality Sub-10 nm possible Metal impurities Particle diameter and position Radial overgrowth Radial overgrowth 9

10 Outline Optimization of the TFET: III-V heterostructures III-V on technologies Templated-assisted InAs NW growth InAs Vertical InAs- NW tunnel FETs Tunnel FET benchmarking Outlook

11 Template-assisted (selective-area) epitaxy (TAE) Idea: 1. Form dielectric nanotube template with crystalline nucleation point at one end. 2. Refill nanotube with III-V material using selective epitaxy nucleated on. nanotube III-V Potential benefits: Small exposed nucleation site 2D aspect-ratio trapping which limits dislocation threading The geometry is defined by the template High uniformity Freedom to design advanced structures III-V side walls are protected pure axial heterostructures Larger Flexibility in choice of growth parameters and materials Not limited to (111) oriented substrates III-V 11

12 Fabrication process α- O 2 substrate /α- stack Etch out sacrificial NW Deposit conformal O 2 MOVPE growth III-V Open template top α- selective wet etch as-grown Template stripped 12

13 Independent of crystal orientation Borg et al. Nano Lett InAs Conventional nanowire growth is limited to [111]B growth direction. Here: Same vertical morphology irrespective of substrate orientation. It even works on nanocrystalline substrates! First time this has been possible! 13

14 Abrupt heterojunctions InSb O 2 InAs InAs Das Kanungo et al. Nanotechnology 2013 Abrupt InAs/InSb axial heterojunctions possible. The process is scalable. - Down to 25 nm diameter demonstrated. 14

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