Optical interconnect: a back end integration scheme for waveguides and optoelectronic InP components.
|
|
- Noreen Collins
- 6 years ago
- Views:
Transcription
1 Optical interconnect: a back end integration scheme for waveguides and optoelectronic InP components. Fedeli J.M. b Jeannot S a.,jousseaume V. b, Di Cioccio L. b, Kostrzewa M. b Orobtchouk R. c, Maury P. a, Zussy M. b a STMicroelectronics, 850 rue Jean Monnet, Crolles, France b CEA-DRT/LETI, 17 rue des Martyrs, Grenoble Cedex 9, France C INSA/LPM, Bât. Blaise Pascal, 7 avenue Jean Capelle Villeurbanne, France ABSTRACT Photonic on CMOS represents the combination of CMOS technology with integrated optics components. It can bring either a new functionality to the electronic circuit or the driving and the amplifying means to the optical components. In the first case, as global interconnections are expected to face severe limitations in the future, optical interconnects could be an alternative to electrical ones. An integration scheme for an optical signal distribution compatible with a Back End Of the Line microelectronic process is presented. Fabrication of the waveguides on top of Integrated Circuits is followed by the molecular bonding of InP dies, needed to perform the optoelectronic components (sources and detectors). Using PECVD silicon nitride or amorphous silicon coupled to PECVD silicon oxide, optical layers and basic components necessary for an optical distribution were developed. Waveguides with low losses (L<2.5dB@1.3µm with Si 3 N 4, for a:si as long as compact 90 microbends and MultiMode Interferometer Beamsplitters were achieved. The molecular bonding of InP dies on CMOS wafers was studied for the integration of active components. The InP wafers are sawed to form mm 2 square dies and are composed of the epitaxial active layers and especially with a sacrificial, etch-stop layer (InGaAs). Molecular bonding of the dies was performed at room temperature and the thickness of the SiO2 bonding layers ranges up to 1µm. After annealing, the dies can support dicing or other mechanical actions with no degradation of the optical properties. INTRODUCTION In its constant development towards new level of performance and integration, microelectronic components aim to integrate new functions and new technologies. Theses different functions can be realized by a means of different materials monolithically integrated to the IC. Recently, it was also demonstrated that the optical interconnects could increase the IC performances. In the classical IC the communication between the different devices is done thanks to the electrical connections. In the face of the further miniaturization and higher working frequencies this solution can be insufficient for future systems. To overcome theses problems, the optical interconnects could replace at least a part of metallic interconnects and in this way increase the IC features. One of a possible approach allowing the optical interconnect realization is to fabricate a passive optical layer containing waveguides, microbends etc above CMOS IC. The next step is a monolithic integration of III-V optical devices and optical coupling to the passive waveguide layer. Figure 1 presents one of possible configuration of the optical interconnect, the optical signal can be guided from source to receiver which converts the optical signal to the electrical photocurrent. The current is droved by a metallic via to the CMOS receiver which regenerates the electrical, digital output signal. Finally, this signal can then if necessary be distributed over a small zone by a local electrical interconnect network [1]. Indeed, the integration of optical functions compatible with a microelectronic process presents new interesting potentialities for integrated circuits but a monolitic integration of dissimilar functions remains still a difficult technological challenge. However, different ways are still proposed for the integration of optical functions with electronics, like free space optical interconnect [2] or using Silicon On Insulator (SOI) technology [3]. Incorporation of new functionality in a microelectronic process must fulfil technology constraints, leading basically to two kind of possible integration:
2 With a Front End integration scheme, the new components (waveguides, optoelectronic components) are realized at the beginning of the IC process at the same level than the transistors. Using this approach, realization of various process steps are possible, allowing SOI photonic for instance, but this requires an important modification at the level of the electronic design. It requires a totally new technology combining CMOS and photonics constraints and changes the design rules. This scheme represents the long term integration of photonics in microelectronic world. With a Back End approach, a photonic layer is defined above the transistors and the dielectric /metallic levels. This leads to the constraint of using a low temperature technology that must not exceed higher temperature than 400 C. Based on this last approach, we focused on the integration of basic optical functions, waveguides, directions changes and beamsplitters in order to perform optical link on a chip. A 200mm technological platform with high index contrast materials is needed, allowing compact devices with low optical losses. Not to disturb the behavior of the microelectronic components, optical devices are developed in the Near Infra Red (NIR) wavelength range (1.3 or 1.55µm). Silicon nitride and amorphous silicon layers were grown by Plasma Enhanced Chemical Vapor Deposition (PECVD) at low temperature. Optical development and characterization of the materials is presented, as well as characterization of basic components necessary to allow an optical distribution on a chip. The molecular bonding of InP dies on CMOS wafers was performed for the integration of active components and will be developed in the second part of the paper. Figure 1: Cross section of optical interconnect configuration [1]. INTEGRATION OF THE PHOTONIC LAYER As the microelectronic process is very mature, introduction of a new part of the process like the integration of a photonic layer is a difficult issue and the most compatible process steps are preferred. However like the introduction of copper for electrical interconnect, new materials like III-V ones can be introduced on the wafers in a dedicated part of the CMOS clean room. The obvious way to introduce a photonic layer is to treat it as a additional metallic layers on top of most of the layers for the electrical interconnect. The integration of optical component on top of ICs must then fulfil to Back End Of the Line integration constraints, which is mainly to perform all technological steps under 400 C. So, typical monocristalline silicon waveguides cannot be used directly due to the high processing temperature, but by full wafer bonding of an optical SOI, they can be reported on a CMOS wafer[4]. For back-end waveguide, Plasma Enhanced Chemical Vapor Deposited silicon nitride is deposited on low index material like PECVD SiO2 which also acts as the cladding layer. After a CMP planarizing operation, MQW layers on InP dies are then reported on top of the waveguides. The InP substrate of the dies is then removed by chemical etching and further processing steps lead to sources and detectors linked to the metallic interconnects.
3 Si3N4 waveguides Bonding III-V Partially processed CMOS InP Substrate removal Electrodes fabrication of source and photodetectors Figure 2: low temperature process integration scheme. WAVEGUIDE FABRICATION As the area of a CMOS circuit ranges generally from 1cm 2 to 2 cm 2, only medium (0.5) or high (2) index contrast index materials relative to silicon dioxide were considered. So, silicon oxide, silicon nitride, amorphous silicon films were deposited by a capacitively coupled plasma reactor, with a RF excitation frequency (13.56 MHz). The power can be tuned from 30 to 1200W and the operative pressure can vary from 0.2 to few torrs. Films were deposited at temperatures lower than 400 C. TEOS was used as precursor for oxide deposition. Si-H 4 /N2O chemistry was used for nitride deposition and silane/h 2 mixture for amorphous silicon. Films were characterized using a spectroscopic ellipsometer (GESP5 SOPRA) in the range 0.2 to 1.8µm FTIR Analysis was performed on a Biorad QS500 spectrometer. Intrinsic optical guided losses on full wafer during process were measured using a prism coupling technique (METRICON and 1.55µm. Silicon nitride has been widely used as optical layers, nevertheless to avoid light absorption due to N-H bonds, high temperature anneals were performed [5]. In this work, at low temperature, PECVD materials are highly hydrogenated. Monitoring the deposition conditions, we have been able to tune the refractive index between 1.82 and SIMS analysis shown in table 1 suggest that the variation of the refractive index is not only due to the SI/ N ratio, but certainly to the incorporation of hydrogen in the layers. Sample Normalized [Si] content Normalized [N] content Normalized Si/N ratio Normalized [H] content 1.3µm , ,383 0,914 0,4196 0,42 1, ,737 0,734 0,734 2,23 Table 1: evolution of Refractive Index with Silicon nitride composition
4 Fig 3 shows the variation of Refractive Index and optical with the deposition power. Optical layers with low losses are obtained ( L<0.5dB/cm) for refractive index between 1.82 and 2. Due to the large presence of Hydrogen in the layers, rather high losses are obtained at 1.55µm. With FTIR analysis (fig 4), the losses can be correlated to the [N-H] content. 4 2,30 Optical (db/cm) 3,5 3 2,5 2 1,5 1 0,5 2,20 2,10 2,00 1,90 1,80 1,70 Refractive Index 0 1, Deposition power (W) Figure 3: Evolution of the optical losses and the Refractive Index varying with deposition power. 14 Optical (db/cm) ,5 1 1,5 2 2,5 3 3,5 4 [N-H] content (FTIR analysis)( A.U) Figure 4: Optical 1.55µm as a function of [N-H] content. Increasing the refractive index contrast between the cladding and the guiding medium leads to more compact devices. So amorphous silicon deposited by PECVD is a promising candidate. While silicon is still extensively studied in SOI configuration or using high temperature deposition and annealing methods, very few studies reports results on PECVD amorphous silicon used as guiding medium. By optimising the H 2 /Silane ratio in the deposition chamber, silicon films with losses as low as after annealing are achievable (fig 5).
5 optical (db/cm) 0,8 0,6 0,4 0,2 after deposition after a 350 C 4H anneal 0,0-0,5 0,0 0,5 1,0 1,5 2,0 2,5 3,0 3,5 H 2 /SiH 4 Figure 5: Evolution of the optical losses before and after a 350 C anneal during 4 Hours for different H2/SiH4 gaz ratio. Using these materials, basic blocks for optical links like submicronic waveguides, 90 micro bends and MultiModeInterferometer (MMI) beamsplitters have been designed. The modelisation of waveguides with a strong field confinement is performed using a full vectorial finite difference mode solver including symmetries and transparent conditions at the limits [6]. Design of beam splitters and compact directional changes are performed using 2D FDTD associated with the effective index method. Optimisation was performed with more accurate 3D FDTD (Finite difference in Time Domain) calculations. Optical devices were fabricated using a standard CMOS technology on 200mm wafers and diced with a polishing edge technique. Optical characterizations of the components are performed using an integrated optical bench, composed of 3D nano-handlers. Light was injected in the circuit by butt coupling method with a lensed fiber with a waist of 2 µm. The collect was done with a multimode fiber linked to an optical spectrum analyser (Agilent 86140B). The observation was performed using an infrared linear response Hamamatsu video camera. As with monocristalline silicon on SOI, the high index difference allows the simultaneous use of refractive compact components (waveguides 0.2*0.5µm, bends with radius <3µm and MMI 1 to 2 less than 6µm²) and photonic crystals components for wavelength functionality. Preliminary characterisations of 0.3*0.3µm waveguides show loss values of 17 db/cm, which is an encouraging value, at the state of the art with deposited silicon [7]. With SiN deposited films, waveguides with a thickness of 400nm and a wideness of 800 nm were fabricated with a silicon dioxide cladding. They exhibited straight losses of 2.5dB/cm in TE polarization at 1.55µm. Ninety degrees microbends were measured for different radius of curvature. Curves with radius of 5µm showed high losses (1.55dB) while no losses were measured for radius above 30µm. Beamsplitters using MultiModeInterférence (MMI) were simulated and characterized. The division of one input to two inputs and one input to four outputs have been tested and the components showed a good equilibration ( E<0.2dB and respectively (see fig 5) and with low loss (L<0.4 and 0.05dB@1.3µm respectively). The good equilibrium of our component proves the good correlation between simulation and experiment. Figure 7 shows the cross-cut of the SiN waveguide with a SiO2 cladding.these basic blocks were selected to demonstrate the possibility of distribution network for example optical clock distribution for CMOS circuitry. Light were input and output in the optical network via surface gratings. MMI one to two and 20µm microbends formed the optical circuitry.
6 In/I0 (db) λ (nm) Figure 6: FDTD simulation and experimental spectral response of a 1 to 4 MMI device. Figure 7: Cross-cut of a SiN waveguide with SiO2 cladding Fig 7: One to sixteen distribution network DIE TO WAFER BONDING Even the latest development on silicon photonics, III-V components remain more efficient for harnessing light. However the cost of the wafers and the processing on small diameter wafers lead to rather expensive components. Integration of InP components coupled to a distribution network on top of a CMOS required a new approach different from the flip-chip solution. Another objective was to process the InP components in the same way as CMOS transistor in order to reduce the cost of the introduction of III-V components. As passive components can be efficiently developed with SiN or Si technology, only the active components require the InP technology. On large CMOS circuit, a very limited surface would be occupied by the sources, modulators and photodetectors. Moreover high speed operation lead to small size components. So our approach consists in dicing an InP wafer with all the heteroepitaxial layers, bonding the dies at the specific needed spots, subtracting the InP die substrates in order to leave only the active thin films on the CMOS wafer, processing the InP components on a dedicated 200 or 300 mm fabrication line. To report the dies, molecular bonding was selected as a good bonding quality is achieved without any additional adhesive materials [8]-[9]. As a matter of fact, the presence of the bonding material could be harmful for efficient optical coupling. Additionally,
7 the molecular bonding satisfies the requirements in term of thermal conductivity and dissipation, transparency at the device working wavelengths and mechanical resistance. The surface morphology and chemistry are critical to the bonding quality. Prior bonding the die, surface must be flat and uniform. Required flatness and uniformity can be obtained by use of CMP. The additional role of CMP polishing is to adjust the thickness of the silicon dioxide cladding layer in order to satisfy the requirements of optical coupling conditions. The surfaces are carefully cleaned and hydrated in the chemical solution. Bonding can occur spontaneously when the prepared wafers are made of silicon. A complete physical model of such a molecular bonding was proposed and presented by Stengl et al. [10] and Gösele et al. [11]. As the materials are of dissimilar nature, one possible way to their assembly is to deposit a silicon dioxide or a silicon nitride layer on each surface. Using this approach we have succeed in the heterogeneous integration of InP 50 mm wafers on silicon and then the InP dies containing an epitaxial layer stack with multiple quantum wells (MQW). The CMOS wafer with SiO 2 top cladding is polished to reach a low roughness, cleaned in deionized water and then dried. A silicon dioxide layer is deposited and then processed on InP (100) epi-ready substrate using Electron Cyclotron Resonance plasma. Thanks to this preparation, the bonding of the both InP/SiO 2 and CMOS/SiO 2 wafers is similar to the Si/SiO 2 on Si/SiO 2 bonding. More details about InP-on-Silicon wafer bonding was described elsewhere [12]-[13]. In this paper we concentrate on the bonding of InP dies on CMOS silicon wafer. For this purpose, the above wafer-to-wafer bonding procedure was first adapted to InP dies bonding on silicon substrate. The dies are obtained by a mechanical dicing of 360 µm thick InP substrate containing an epitaxial heterostructure and a thin silicon dioxide layer. The minimal die size we have bonded is 1 x 1 mm². A pick&place apparatus can be used to report the InP dies on the Silicon substrate. The bonding itself occurs spontaneously at room temperature; however, an annealing at 200 C during several hours reinforces adhesion. Mechanical dies thinning down to 20 µm was achieved after bonding without degrading the remaining bonded material quality (Figure 8). Next, the remaining InP substrate and the sacrificial InGaAs layer can be chemically and selectively back-etched. The additional post-bonding technological steps as polishing show that the assembled InP dies on the Si substrate can endure many kind of mechanical action without debonding. The bond strength between the die and the substrate was measured using Die Shear testing equipment. The obtained shear strength is of 5 MPa ± 1.4 MPa for 1 mm², 360 µm thick InP dies. Using this approach we bonded a die containing an InAs 0.65 P nm thick Single Quantum Well (SQW) confined between 120 nm thick InP barriers. In this case, the final thickness of the reported die with a SQW is reduced to 256 nm. (a) (b) 300 µm 300 µm Figure 8: SEM image of 360 µm thick InP die bonded on Silicon substrate (a) and of thinned down to 20 µm die after bonding (b). The reported optoelectronic devices kept the optical properties as showed on the Figure 9 which presents the photoluminescence (PL) cartography at µm from the reported die after chemical back etching of the initial substrate and etch-stop layer. The intensity is homogenous on the whole die. The peak intensity at µm and the Full Width at Half Maximum (FWHM) did not change after all the technological process. So these technological procedures do not induce any significant strain or stress in the reported heterostructure.
8 (a) (b) [a.u.] [0.353] [2.569] [4.784] Figure 9: Optical image of a 256 nm thick InP die containing an InAsP quantum well bonded on a silicon substrate (a) and its PL cartography (b). As mentioned above, the bonding is reinforced at 200 C during several hours. When the reported dies are thick, the thermal treatment at higher temperature could favor debonding due to the stress arising from differences between thermal expansion coefficients of silicon and InP. However, when the dies are thin, the stress induced by a thermal treatment is lower and the annealing at higher temperature is possible. Depending on the operating temperature an additional protection of exposed InP surface can be needed in order to prevent the InP from Phosphorous desorption. Using the same technology, we reported the 200 µm thick InP dies with QW on the optical layer transferred on CMOS processed 200 mm of diameter wafer [12]. The optical layer is composed of silicon waveguides. The top oxidized surface was cleaned. Then, InP dies were placed on specific spots. Figure 1a show an optical view from an InP die bonded on CMOS wafer with an optical layer and Figure 1b an in-plane view presenting the optical waveguides on a top of a CMOS wafer. (a) InP (b) CMOS Figure 10: 1.2 x 1.2 mm², 200 µm thick InP die bonded on optical layer on a CMOS substrate (a) and optical waveguides on CMOS (b) CONCLUSION In order to integrate optical functions within microelectronic development, technological platform compatible with Back-End processes is an attractive solution. Waveguides materials presenting a medium to high index contrast with low intrinsic loss were developed. With medium index contrast (0.3 to 0.5) with silicon dioxide, PECVD silicon nitride
9 technology exhibits very low optical with already compact components, i.e. submicronic waveguides of 2.5dB/cm and equilibrated MMI. However, its optical characteristics are less A one to sixteen distribution network was demonstrated with good output equilibrium. To miniaturize even more, amorphous silicon represents an interesting alternative to SOI architecture and preliminary results are encouraging. Aiming the introduction of efficient active components on CMOS, we reported 200 µm thick InP dies with epitaxial stack at specific spots of a 200 mm CMOS processed wafer with an optical layer. The optical layer is composed of silicon waveguides and silicon dioxide cladding. Future work will focus on the 200mm fabrication of InP components coupled to the underneath waveguides. AKNOWLEDGMENT This work is supported by the European community projects FP IST PICMOS and FP6-RII3-CT MNTEurope.. REFERENCES [1] I. O'Connor, F. Gaffiot, "On-chip optical interconnect for low-power", in Ultra Low-Power Electronics and Design, ed. E. Macii, Kluwer, 2004 [2] N. Al-Ababneh, M. Testorf, Optics Communications,Volume 242, Issues 4-6, 8 December 2004, P [3] Y.A Vlasov, S.J. McNab, Optics Express,.Vol 12, N 8 (2004) [4] M. Kostrzewa, L. Di Cioccio, M. Zussy, J. C. Roussin, J. M. Fedeli, N. Kernevez, P. Regreny, Ch.Lagahe- Blanchard, B. Aspar, InP dies transferred onto silicon substrate for optical interconnects application, Sensors and Actuators, submitted, 2005 [5] Zhang et al. Material Letters, 12 (1991) [6] Worhoff and al. Sensors and actuators 74 (1999) 9-12 [7] L.Liao Low loss Polysilicon Waveguides for silicon Optics MIT report(1995) [8] Q.-Y. Tong, U. Gösele, Semiconductor Wafer Bonding, The Electrochemical Society Series, INC, Pennington, New Jersey, 1999 [9] U. Gösele, Q.-Y. Tong, A. Schumacher, G. Krauter, M. Reiche, A. Plößl, P. Kopperschmidt, T.-H. Lee, W.-J. Kim, Wafer Bonding for Microsystems Technologies, Sensor and Actuators 74, , 1999 [10] R. Stengl, T. Tan, U. Gosele, A Model for the Silicon Wafer Bonding Process, Jpn J. Appl. Phys. 28, 1735, 1989 [11] U. Gösele, Y. Blum, G. Kästner, P. Kopperschmidt, G. Kräuter, R. Scholz, A. Schumacher, St. Senz, Q.-Y. Tong, L.-J. Huang, Y.- L. Chao, T. H. Lee, Fundamental Issues In Wafer Bonding, J. Vac. Sci; Technol. A17 (4), Jul/Aug 1999 [12] M. Kostrzewa, P. Regreny, M. P. Besland, J. L. Leclercq, G. Grenet, P. Rojo-Romeo, G. Hollinger, E. Jalaguier, P. Perreau, H. Moriceau, O. Marty, High Quality Epitaxial Growth on New InP/Si Substrate, IPRM 2003, Santa Barbara, USA 2003 [13] M. Kostrzewa, L. Di Cioccio, J. M. Fedeli, M. Zussy, P. Regreny, J. C. Roussin, N. Kernevez, Die-to-Wafer molecular bonding for optical interconnects and packaging, EMPC 2005, June 12-15, Brugge, Belgium 2005
Hybrid III-V/Si DFB laser integration on a 200 mm fully CMOS-compatible silicon photonics platform
Hybrid III-V/Si DFB laser integration on a 200 mm fully CMOS-compatible silicon photonics platform B. Szelag 1, K. Hassan 1, L. Adelmini 1, E. Ghegin 1,2, Ph. Rodriguez 1, S. Bensalem 1, F. Nemouchi 1,
More informationPROJECT PERIODIC REPORT
PROJECT PERIODIC REPORT Grant Agreement number: 619456 Project acronym: SITOGA Project title: Silicon CMOS compatible transition metal oxide technology for boosting highly integrated photonic devices with
More informationFIBRE-COUPLED HIGH-INDEX PECVD SILICON- OXYNITRIDE WAVEGUIDES ON SILICON
FIBRE-COUPLED HIGH-INDEX PECVD SILICON- OXYNITRIDE WAVEGUIDES ON SILICON Maxim Fadel and Edgar Voges University of Dortmund, High Frequency Institute, Friedrich-Woehler Weg 4, 44227 Dortmund, Germany ABSTRACT
More informationCompact hybrid plasmonic-si waveguide structures utilizing Albanova E-beam lithography system
Compact hybrid plasmonic-si waveguide structures utilizing Albanova E-beam lithography system Introduction Xu Sun Laboratory of Photonics and Microwave Engineering, Royal Institute of Technology (KTH),
More informationChapter 3 Silicon Device Fabrication Technology
Chapter 3 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world) are manufactured every year. VLSI (Very Large Scale Integration) ULSI (Ultra Large Scale
More informationLow Temperature Dielectric Deposition for Via-Reveal Passivation.
EMPC 2013, September 9-12, Grenoble; France Low Temperature Dielectric Deposition for Via-Reveal Passivation. Kath Crook, Mark Carruthers, Daniel Archard, Steve Burgess, Keith Buchanan SPTS Technologies,
More informationProgress in Monolithic III-V/Si and towards processing III-V Devices in Silicon Manufacturing. E.A. (Gene) Fitzgerald
Progress in Monolithic III-V/Si and towards processing III-V Devices in Silicon Manufacturing E.A. (Gene) Fitzgerald M.J. Mori, C.L.Dohrman, K. Chilukuri MIT Cambridge, MA USA Funding: MARCO IFC and Army
More informationLow-cost, deterministic quasi-periodic photonic structures for light trapping in thin film silicon solar cells
Low-cost, deterministic quasi-periodic photonic structures for light trapping in thin film silicon solar cells The MIT Faculty has made this article openly available. Please share how this access benefits
More informationOptimization of optical performances in submicron silicon-on-insulator rib and strip waveguides by H 2 thermal annealing
I N S T I T U T D E R E C H E R C H E T E C H N O L O G I Q U E Optimization of optical performances in submicron silicon-on-insulator rib and strip waveguides by H thermal annealing Erwine Pargon 1, Cyril
More information200mm Next Generation MEMS Technology update. Florent Ducrot
200mm Next Generation MEMS Technology update Florent Ducrot The Most Exciting Industries on Earth Semiconductor Display Solar 20,000,000x reduction in COST PER TRANSISTOR in 30 years 1 20x reduction in
More informationNear- and mid- infrared group IV photonics
Near- and mid- infrared group IV photonics C. G. Littlejohns 1,2, M. Saïd Rouifed 1, H. Qiu 1, T. Guo Xin 1, T. Hu 1, T. Dominguez Bucio 2, M. Nedeljkovic 2, G. Z. Mashanovich 2, G. T. Reed 2, F. Y. Gardes
More informationA Nano-thick SOI Fabrication Method
A Nano-thick SOI Fabrication Method C.-H. Huang 1, J.T. Cheng 1, Y.-K. Hsu 1, C.-L. Chang 1, H.-W. Wang 1, S.-L. Lee 1,2, and T.-H. Lee 1,2 1 Dept. of Mechanical Engineering National Central University,
More informationMicroelectronics. Integrated circuits. Introduction to the IC technology M.Rencz 11 September, Expected decrease in line width
Microelectronics Introduction to the IC technology M.Rencz 11 September, 2002 9/16/02 1/37 Integrated circuits Development is controlled by the roadmaps. Self-fulfilling predictions for the tendencies
More informationMicro-Electro-Mechanical Systems (MEMS) Fabrication. Special Process Modules for MEMS. Principle of Sensing and Actuation
Micro-Electro-Mechanical Systems (MEMS) Fabrication Fabrication Considerations Stress-Strain, Thin-film Stress, Stiction Special Process Modules for MEMS Bonding, Cavity Sealing, Deep RIE, Spatial forming
More informationSilicon nitride deposited by ECR CVD at room temperature for LOCOS isolation technology
Applied Surface Science 212 213 (2003) 388 392 Silicon nitride deposited by ECR CVD at room temperature for LOCOS isolation technology Marcus A. Pereira, José A. Diniz, Ioshiaki Doi *, Jacobus W. Swart
More informationAmorphous silicon waveguides for microphotonics
4 Amorphous silicon waveguides for microphotonics Amorphous silicon a-si was made by ion irradiation of crystalline silicon with 1 10 15 Xe ions cm 2 at 77 K in the 1 4 MeV energy range. Thermal relaxation
More informationMicrostructures using RF sputtered PSG film as a sacrificial layer in surface micromachining
Sādhanā Vol. 34, Part 4, August 2009, pp. 557 562. Printed in India Microstructures using RF sputtered PSG film as a sacrificial layer in surface micromachining VIVEKANAND BHATT 1,, SUDHIR CHANDRA 1 and
More informationChip and system-level integration technologies for silicon photonics
Chip and system-level integration technologies for silicon photonics Bert Jan Offrein 5th International Symposium for Optical Interconnect in Data Centres Outline The need for integration at component
More informationMicro-Electro-Mechanical Systems (MEMS) Fabrication. Special Process Modules for MEMS. Principle of Sensing and Actuation
Micro-Electro-Mechanical Systems (MEMS) Fabrication Fabrication Considerations Stress-Strain, Thin-film Stress, Stiction Special Process Modules for MEMS Bonding, Cavity Sealing, Deep RIE, Spatial forming
More informationSurface Micromachining
Surface Micromachining Micro Actuators, Sensors, Systems Group University of Illinois at Urbana-Champaign Outline Definition of surface micromachining Most common surface micromachining materials - polysilicon
More informationLect. 2: Basics of Si Technology
Unit processes Thin Film Deposition Etching Ion Implantation Photolithography Chemical Mechanical Polishing 1. Thin Film Deposition Layer of materials ranging from fractions of nanometer to several micro-meters
More informationAmorphous and Polycrystalline Thin-Film Transistors
Part I Amorphous and Polycrystalline Thin-Film Transistors HYBRID AMORPHOUS AND POLYCRYSTALLINE SILICON DEVICES FOR LARGE-AREA ELECTRONICS P. Mei, J. B. Boyce, D. K. Fork, G. Anderson, J. Ho, J. Lu, Xerox
More informationSilver Diffusion Bonding and Layer Transfer of Lithium Niobate to Silicon
Chapter 5 Silver Diffusion Bonding and Layer Transfer of Lithium Niobate to Silicon 5.1 Introduction In this chapter, we discuss a method of metallic bonding between two deposited silver layers. A diffusion
More informationUV15: For Fabrication of Polymer Optical Waveguides
CASE STUDY UV15: For Fabrication of Polymer Optical Waveguides Master Bond Inc. 154 Hobart Street, Hackensack, NJ 07601 USA Phone +1.201.343.8983 Fax +1.201.343.2132 main@masterbond.com CASE STUDY UV15:
More informationChapter 2 Manufacturing Process
Digital Integrated Circuits A Design Perspective Chapter 2 Manufacturing Process 1 CMOS Process 2 CMOS Process (n-well) Both NMOS and PMOS must be built in the same silicon material. PMOS in n-well NMOS
More informationRed luminescence from Si quantum dots embedded in SiO x films grown with controlled stoichiometry
Red luminescence from Si quantum dots embedded in films grown with controlled stoichiometry Zhitao Kang, Brannon Arnold, Christopher Summers, Brent Wagner Georgia Institute of Technology, Atlanta, GA 30332
More informationMicro-Electro-Mechanical Systems (MEMS) Fabrication. Special Process Modules for MEMS. Principle of Sensing and Actuation
Micro-Electro-Mechanical Systems (MEMS) Fabrication Fabrication Considerations Stress-Strain, Thin-film Stress, Stiction Special Process Modules for MEMS Bonding, Cavity Sealing, Deep RIE, Spatial forming
More informationMethod to obtain TEOS PECVD Silicon Oxide Thick Layers for Optoelectronics devices Application
Method to obtain TEOS PECVD Silicon Oxide Thick Layers for Optoelectronics devices Application ABSTRACT D. A. P. Bulla and N. I. Morimoto Laboratório de Sistemas Integráveis da EPUSP São Paulo - S.P. -
More informationFRAUNHOFER INSTITUTE FOR PHOTONIC MICROSYSTEMS IPMS SMART MATERIALS
FRAUNHOFER INSTITUTE FOR PHOTONIC MICROSYSTEMS IPMS SMART MATERIALS 1 ELECTRO-ACTIVE ORGANIC MATERIALS At Fraunhofer IPMS electro-active organic materials are implemented in the design of new and smarter
More informationMaterials Characterization
Materials Characterization C. R. Abernathy, B. Gila, K. Jones Cathodoluminescence (CL) system FEI Nova NanoSEM (FEG source) with: EDAX Apollo silicon drift detector (TE cooled) Gatan MonoCL3+ FEI SEM arrived
More informationPoly-SiGe MEMS actuators for adaptive optics
Poly-SiGe MEMS actuators for adaptive optics Blake C.-Y. Lin a,b, Tsu-Jae King a, and Richard S. Muller a,b a Department of Electrical Engineering and Computer Sciences, b Berkeley Sensor and Actuator
More informationSurface Micromachining of Uncooled Infrared Imaging Array Using Anisotropic Conductive Film
Surface Micromachining of Uncooled Infrared Imaging Array Using Anisotropic Conductive Film Weiguo Liu, Lingling Sun, Weiguang Zhu, Ooi Kiang Tan Microelectronics Center, School of Electrical and Electronic
More informationLecture 5. SOI Micromachining. SOI MUMPs. SOI Micromachining. Silicon-on-Insulator Microstructures. Agenda:
EEL6935 Advanced MEMS (Spring 2005) Instructor: Dr. Huikai Xie SOI Micromachining Agenda: SOI Micromachining SOI MUMPs Multi-level structures Lecture 5 Silicon-on-Insulator Microstructures Single-crystal
More informationMonolithic Microphotonic Optical Isolator
Monolithic Microphotonic Optical Isolator Lei Bi, Juejun Hu, Dong Hun Kim, Peng Jiang, Gerald F Dionne, Caroline A Ross, L.C. Kimerling Dept. of Materials Science and Engineering Massachusetts Institute
More informationSTUDY OF INFLUENCE OF IN SITU CLEANING PROCESS ON THE QUALITY OF PECVD SiO 2 / LPCVD POLYSILICON INTERFACE
STUDY OF INFLUENCE OF IN SITU CLEANING PROCESS ON THE QUALITY OF PECVD SiO 2 / LPCVD POLYSILICON INTERFACE Abstract ANA NEILDE R. DA SILVA, NILTON MORIMOTO, OLIVIER BONNAUD* neilde@lsi.usp.br - morimoto@lsi.usp.br
More informationHigh Performance Optical Waveguides based on Boron and Phosphorous doped Silicon Oxynitride
High Performance Optical Waveguides based on Boron and Phosphorous doped Silicon Oxynitride Fei Sun*, Alfred Driessen, Kerstin Wörhoff Integrated Optical Micro Systems group, MESA+ Research Institute for
More informationCharacterisation of Fe-Ni amorphous thin films for possible magnetostrictive sensor applications
Characterisation of Fe-Ni amorphous thin films for possible magnetostrictive sensor applications Contents 9.1 Introduction 9.2 Experiment 9.3 Results and Discussions 9.4 Conclusion 9.1 Introduction Magnetostrictive
More informationChemical Mechanical Planarization STACK TRECK. SPCC 2017 Viorel Balan
Chemical Mechanical Planarization STACK TRECK Viorel.balan@cea.fr > Red 50 is years The of New Moore s Blue Law Stacking Is The New Scaling 2 Lithography Enables Scaling / CMP Enables Stacking Building
More information5.8 Diaphragm Uniaxial Optical Accelerometer
5.8 Diaphragm Uniaxial Optical Accelerometer Optical accelerometers are based on the BESOI (Bond and Etch back Silicon On Insulator) wafers, supplied by Shin-Etsu with (100) orientation, 4 diameter and
More informationSUPPLEMENTARY INFORMATION
SUPPLEMENTARY INFORMATION doi:.38/nphoton..7 Supplementary Information On-chip optical isolation in monolithically integrated nonreciprocal optical resonators Lei Bi *, Juejun Hu, Peng Jiang, Dong Hun
More information5. Packaging Technologies Trends
5. Packaging Technologies Trends Electronic products and microsystems continue to find new applications in personal, healthcare, home, automotive, environmental and security systems. Advancements in packaging
More informationEE 330 Lecture 8. IC Fabrication Technology Part II. - Oxidation - Epitaxy - Polysilicon - Interconnects
EE 330 Lecture 8 IC Fabrication Technology Part II - Oxidation - Epitaxy - Polysilicon - Interconnects Review from Last Time MOS Transistor Bulk Source Gate Drain p-channel MOSFET Lightly-doped n-type
More information3.46 OPTICAL AND OPTOELECTRONIC MATERIALS
Badgap Engineering: Precise Control of Emission Wavelength Wavelength Division Multiplexing Fiber Transmission Window Optical Amplification Spectrum Design and Fabrication of emitters and detectors Composition
More informationLecture 22: Integrated circuit fabrication
Lecture 22: Integrated circuit fabrication Contents 1 Introduction 1 2 Layering 4 3 Patterning 7 4 Doping 8 4.1 Thermal diffusion......................... 10 4.2 Ion implantation.........................
More informationMirror Coatings for Next Generation Detector
Mirror Coatings for Next Generation Detector Prof. Shiuh Chao (Member of LSC) Institute of Photonics Technologies (IPT) National Tsing Hua University (NTHU) Hsinchu, Taiwan, R.O.C. The 3rd KAGRA International
More informationSilicon-on-insulator (SOI) was developed in the
66 Silicon-on-insulator substrates for compound semiconductor applications Mike Cooke reports on research developments reaching towards high-power electronics and infrared optical communications. Silicon-on-insulator
More informationPreface Preface to First Edition
Contents Foreword Preface Preface to First Edition xiii xv xix CHAPTER 1 MEMS: A Technology from Lilliput 1 The Promise of Technology 1 What Are MEMS or MST? 2 What Is Micromachining? 3 Applications and
More informationMicro/nanophotonics at VTT
Micro/nanophotonics at VTT Timo Aalto (timo.aalto@vtt.fi) VTT Technical Research Centre of Finland Micro and nanotechnology seminar, St Petersburg, 16 th Nov 2010 2 Outline Overview of micro and nanophotonics
More informationSilicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant
Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant substrate Creates latch up protection for CMOS Buried Epi
More information1. Photonic crystal band-edge lasers
TIGP Nanoscience A Part 1: Photonic Crystals 1. Photonic crystal band-edge lasers 2. Photonic crystal defect lasers 3. Electrically-pumped photonic crystal lasers 1. Photonic crystal band-edge lasers Min-Hsiung
More informationChapter 4 Fabrication Process of Silicon Carrier and. Gold-Gold Thermocompression Bonding
Chapter 4 Fabrication Process of Silicon Carrier and Gold-Gold Thermocompression Bonding 4.1 Introduction As mentioned in chapter 2, the MEMs carrier is designed to integrate the micro-machined inductor
More informationCMOS Technology. Flow varies with process types & company. Start with substrate selection. N-Well CMOS Twin-Well CMOS STI
CMOS Technology Flow varies with process types & company N-Well CMOS Twin-Well CMOS STI Start with substrate selection Type: n or p Doping level, resistivity Orientation, 100, or 101, etc Other parameters
More informationActivities in Plasma Process Technology at SENTECH Instruments GmbH, Berlin. Dr. Frank Schmidt
Activities in Plasma Process Technology at SENTECH Instruments GmbH, Berlin Dr. Frank Schmidt The Company Company Private company, founded 1990 80 employees ISO 9001 Location Science & Technology Park,
More informationSimple UV-based Soft-lithography Process for. Fabrication of Low-Loss Polymer PSQ-L-based. Waveguides
Simple UV-based Soft-lithography Process for Fabrication of Low-Loss Polymer PSQ-L-based Waveguides Jie Teng 1, 2, 4, Stijn Scheerlinck 4, Geert Morthier 4, Roel Baets 4, Hongbo Zhang 2,3, Xigao Jian 2,3,
More informationIndium Phosphide Planar Integrated Optics Comes of Age. For planar integrated optics, the future has finally arrived
Indium Phosphide Planar Integrated Optics Comes of Age Jens Noeckel Tom Pierson Jane Zucker Nanovation Technologies For planar integrated optics, the future has finally arrived Integrated optics had its
More informationDesign and fabrication of ultrathin silicon-nitride membranes for use in UV-visible airgap-based MEMS optical filters
Journal of Physics: Conference Series PAPER OPEN ACCESS Design and fabrication of ultrathin silicon-nitride membranes for use in UV-visible airgap-based MEMS optical filters To cite this article: Mohammadamir
More informationReview of CMOS Processing Technology
- Scaling and Integration Moore s Law Unit processes Thin Film Deposition Etching Ion Implantation Photolithography Chemical Mechanical Polishing 1. Thin Film Deposition Layer of materials ranging from
More informationFormation of and Light Emission from Si nanocrystals Embedded in Amorphous Silicon Oxides
10.1149/1.2392914, copyright The Electrochemical Society Formation of and Light Emission from Si nanocrystals Embedded in Amorphous Silicon Oxides D. Comedi a, O. H. Y. Zalloum b, D. E. Blakie b, J. Wojcik
More informationTEPZZ 5 Z 6A_T EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (43) Date of publication: Bulletin 2012/46
(19) (12) EUROPEAN PATENT APPLICATION TEPZZ 5 Z 6A_T (11) EP 2 523 026 A1 (43) Date of publication: 14.11.2012 Bulletin 2012/46 (21) Application number: 12167332.1 (51) Int Cl.: G02B 6/12 (2006.01) G02B
More informationSemiconductor Device Fabrication
5 May 2003 Review Homework 6 Semiconductor Device Fabrication William Shockley, 1945 The network before the internet Bell Labs established a group to develop a semiconductor replacement for the vacuum
More informationSET Technical Bulletin
SET Technical Bulletin DIE BONDING APPLICATIONS An Innovative Die to Wafer 3D Integration Scheme: Die to Wafer Oxide or Copper Direct Bonding with Planarised Oxide Inter-Die Filling RF MEMS and Flip-Chip
More informationPassivation of SiO 2 /Si Interfaces Using High-Pressure-H 2 O-Vapor Heating
Jpn. J. Appl. Phys. Vol. 39 (2000) pp. 2492 2496 Part, No. 5A, May 2000 c 2000 The Japan Society of Applied Physics Passivation of O 2 / Interfaces Using High-Pressure-H 2 O-Vapor Heating Keiji SAKAMOTO
More informationTackling the optical interconnection challenge for the Integrated Photonics Revolution
Tackling the optical interconnection challenge for the Integrated Photonics Revolution Dr. Ir. TU Delft, Precision and Microsystems Engineering m.tichem@tudelft.nl Microfabrication and MEMS Si microfabrication
More informationOptically thin palladium films on silicon-based substrates and nanostructure formation: effects of hydrogen
Ž. Applied Surface Science 161 2000 54 60 www.elsevier.nlrlocaterapsusc Optically thin palladium films on silicon-based substrates and nanostructure formation: effects of hydrogen Andreas Othonos a,),
More informationis kept at a minimum with low power densities of less than 50 mw/cm 2.
Production Performance Success with a High Throughput PECVD System David Lishan 1, Ken Mackenzie 1, Mike Fresina 2, Doug Wend 2, John Erickson 2, and Dave Johnson 1 1 Unaxis Wafer Processing, St. Petersburg,
More informationPEAK EFFICIENCIES WITH FALLING MANUFACTURING COSTS
PEAK EFFICIENCIES WITH FALLING MANUFACTURING COSTS Simple and cost-effective introduction of PERC technology into the mass production of solar cells Kerstin Strauch, Florian Schwarz, Sebastian Gatz 1 Introduction
More informationEE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects
EE 330 Lecture 9 IC Fabrication Technology Part II -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects Review from Last Time Etching Dry etch (anisotropic) SiO
More informationSupporting Information
Supporting Information Fast-Response, Sensitivitive and Low-Powered Chemosensors by Fusing Nanostructured Porous Thin Film and IDEs-Microheater Chip Zhengfei Dai,, Lei Xu,#,, Guotao Duan *,, Tie Li *,,
More informationSilicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant
Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant substrate Creates latch up protection for CMOS Buried Epi
More informationPROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS
Contents: VI Sem ECE 06EC63: Analog and Mixed Mode VLSI Design PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS 1. Introduction 2. CMOS Fabrication 3. Simplified View of Fabrication Process 3.1 Alternative
More informationExtending Etch and Deposition Capabilities for Implementation of 3D Packaging of MEMS in Volume Production
Extending Etch and Deposition Capabilities for Implementation of 3D Packaging of MEMS in Volume Production David Butler, VP Product Management & Marketing SPTS Technologies Contents Industry Trends TSV
More informationOxidized Silicon-On-Insulator (OxSOI) from bulk silicon: a new photonic platform
Oxidized Silicon-On-Insulator (OxSOI) from bulk silicon: a new photonic platform Nicolás Sherwood-Droz*, Alexander Gondarenko and Michal Lipson School of Electrical and Computer Engineering, Cornell University,
More informationIn-Situ Characterization During MOVPE Growth of III-Nitrides using Reflectrometry
18 Annual Report 1999, Dept. of Optoelectronics, University of Ulm In-Situ Characterization During MOVPE Growth of III-Nitrides using Reflectrometry Christoph Kirchner and Matthias Seyboth The suitability
More informationPublished in: Proceedings of the 19th Annual Symposium of the IEEE Photonics Benelux Chapter, 3-4 November 2014, Enschede, The Netherlands
Characterization of Ge/Ag ohmic contacts for InP based nanophotonic devices Shen, L.; Wullems, C.W.H.A.; Veldhoven, van, P.J.; Dolores Calzadilla, V.M.; Heiss, D.; van der Tol, J.J.G.M.; Smit, M.K.; Ambrosius,
More informationRadiation Tolerant Isolation Technology
Radiation Tolerant Isolation Technology Background The following contains a brief description of isolation technologies used for radiation hardened integrated circuits. The technologies mentioned are junction
More informationEFFECT OF CRYSTALORIENTATIONIN OXIDATION PROCESS OF VLSI FABRICATION
International Journal of Research in Engineering, Technology and Science, Volume VII, Special Issue, Feb 2017 www.ijrets.com, editor@ijrets.com, ISSN 2454-1915 EFFECT OF CRYSTALORIENTATIONIN OXIDATION
More informationApplication of infrared thermography to the characterization of multicristalline silicon solar cells
Application of infrared thermography to the characterization of multicristalline silicon solar cells A. Kaminski, O. Nichiporuk*, J. Jouglar, P.L. Vuillermoz, A. Laugier Laboratoire de Physique de la Matière
More informationEngineered Substrates
Engineered Substrates Engineered Substrates Using the NanoCleave TM Process Francois J. Henley President and CEO Silicon Genesis Corporation San Jose, California SiGen Presentation Outline Engineered Substrates
More informationPHYS 534 (Fall 2008) Process Integration OUTLINE. Examples of PROCESS FLOW SEQUENCES. >Surface-Micromachined Beam
PHYS 534 (Fall 2008) Process Integration Srikar Vengallatore, McGill University 1 OUTLINE Examples of PROCESS FLOW SEQUENCES >Semiconductor diode >Surface-Micromachined Beam Critical Issues in Process
More informationHigh Pressure Chemical Vapor Deposition to make Multimaterial Optical Fibers
High Pressure Chemical Vapor Deposition to make Multimaterial Optical Fibers Subhasis Chaudhuri *1 1, 2, 3, John V. Badding 1 Department of Chemistry, Pennsylvania State University, University Park, PA
More informationSPP waveguides. Introduction Size Mismatch between Scaled CMOS Electronics and Planar Photonics. dielectric waveguide ~ 10.
SPP waveguides Introduction Size Mismatch between Scaled CMOS Electronics and Planar Photonics CMOS transistor: Medium-sized molecule dielectric waveguide ~ 10 Silicon Photonics? Could such an Architecture
More informationState of the art quality of a GeOx interfacial passivation layer formed on Ge(001)
APPLICATION NOTE State of the art quality of a Ox interfacial passivation layer formed on (001) Summary A number of research efforts have been made to realize Metal-Oxide-Semiconductor Field Effect Transistors
More informationElectrical and Fluidic Microbumps and Interconnects for 3D-IC and Silicon Interposer
Electrical and Fluidic Microbumps and Interconnects for 3D-IC and Silicon Interposer Li Zheng, Student Member, IEEE, and Muhannad S. Bakir, Senior Member, IEEE Georgia Institute of Technology Atlanta,
More informationRare Earth Doping of Silicon-Rich Silicon Oxide for Silicon-Based Optoelectronic Applications
Journal of the Korean Physical Society, Vol. 39, December 2001, pp. S78 S82 Rare Earth Doping of Silicon-Rich Silicon Oxide for Silicon-Based Optoelectronic Applications Se-Young Seo, Hak-Seung Han and
More informationMolding materials performances experimental study for the 3D interposer scheme
Minapad 2014, May 21 22th, Grenoble; France Molding materials performances experimental study for the 3D interposer scheme Y. Sinquin, A. Garnier, M. Argoud, A. Jouve, L. Baud, J. Dechamp, N. Allouti,
More informationResearch Article Thermal Characteristics of InGaN/GaN Flip-Chip Light Emitting Diodes with Diamond-Like Carbon Heat-Spreading Layers
International Photoenergy, Article ID 829284, 5 pages http://dx.doi.org/1.1155/214/829284 Research Article Thermal Characteristics of InGaN/GaN Flip-Chip Light Emitting Diodes with Diamond-Like Carbon
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 9/13/2007 Fabrication Technology Lecture 1 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world)
More informationMetallizing High Aspect Ratio TSVs For MEMS Challenges and Capabilities. Vincent Mevellec, PhD
Metallizing High Aspect Ratio TSVs For MEMS Challenges and Capabilities Vincent Mevellec, PhD Agenda Introduction MEMS and sensors market TSV integration schemes Process flows for TSV Metallization aveni
More informationInfluence of Underlayer on Crystallography and Roughness of Aluminum Nitride Thin Film Reactively Sputtered by Ion-Beam Kaufman Source
Influence of Underlayer on Crystallography and Roughness of Aluminum Nitride Thin Film Reactively Sputtered by Ion-Beam Kaufman Source GABLECH Imrich 1,*, SVATOŠ Vojtěch 1,, PRÁŠEK Jan 1,, HUBÁLEK Jaromír
More informationSemiconductor Technology
Semiconductor Technology from A to Z Oxidation www.halbleiter.org Contents Contents List of Figures List of Tables II III 1 Oxidation 1 1.1 Overview..................................... 1 1.1.1 Application...............................
More informationIsolation Technology. Dr. Lynn Fuller
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Isolation Technology Dr. Lynn Fuller Motorola Professor 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Fax (585) 475-5041
More information9 rue Alfred Kastler - BP Nantes Cedex 3 - France Phone : +33 (0) website :
9 rue Alfred Kastler - BP 10748-44307 Nantes Cedex 3 - France Phone : +33 (0) 240 180 916 - email : info@systemplus.fr - website : www.systemplus.fr November 2010 - Version 2 Written by: Sylvain HALLEREAU
More informationGrowth and Doping of SiC-Thin Films on Low-Stress, Amorphous Si 3 N 4 /Si Substrates for Robust Microelectromechanical Systems Applications
Journal of ELECTRONIC MATERIALS, Vol. 31, No. 5, 2002 Special Issue Paper Growth and Doping of SiC-Thin Films on Low-Stress, Amorphous Si 3 N 4 /Si Substrates for Robust Microelectromechanical Systems
More informationHigh Mobility Flexible Amorphous IGZO Thin-Film Transistors with a Low Thermal Budget Ultra-Violet Pulsed Light Process.
High Mobility Flexible Amorphous IGZO Thin-Film Transistors with a Low Thermal Budget Ultra-Violet Pulsed Light Process. M. Benwadih 1*, R. Coppard 1, K. Bonrad 2, A. Klyszcz 2, D. Vuillaume 3 1 : Univ.
More informationFiber Bragg grating sensor based on external cavity laser
Dolores Calzadilla, V.M.; Pustakhod, D.; Leijtens, X.J.M.; Smit, M.K. Published in: Proceedings of the 20th Annual Symposium of the IEEE Photonics Benelux Chapter, 26-27 November 2015, Brussels, Belgium
More informationVisualization and Control of Particulate Contamination Phenomena in a Plasma Enhanced CVD Reactor
Visualization and Control of Particulate Contamination Phenomena in a Plasma Enhanced CVD Reactor Manabu Shimada, 1 Kikuo Okuyama, 1 Yutaka Hayashi, 1 Heru Setyawan, 2 and Nobuki Kashihara 2 1 Department
More informationProcese de depunere in sistemul Plasma Enhanced Chemical Vapor Deposition (PECVD)
Procese de depunere in sistemul Plasma Enhanced Chemical Vapor Deposition (PECVD) Ciprian Iliescu Conţinutul acestui material nu reprezintă in mod obligatoriu poziţia oficială a Uniunii Europene sau a
More informationMerle D. Yoder, Jr. 5th Year Microelectronic Engineering Student Rochester Institute of Technology ABSTRACT
LOW TEMPERATURE DEPOSITION OF FILMS BY ECR INT~0DUCTION Merle D. Yoder, Jr. 5th Year Microelectronic Engineering Student Rochester Institute of Technology ABSTRACT SiO films of high quality have been depositeä
More informationEE 330 Lecture 9. IC Fabrication Technology Part 2
EE 330 Lecture 9 IC Fabrication Technology Part 2 Quiz 8 A 2m silicon crystal is cut into wafers using a wire saw. If the wire diameter is 220um and the wafer thickness is 350um, how many wafers will this
More informationEE 330 Lecture 8. IC Fabrication Technology Part II. - Masking - Photolithography - Deposition - Etching - Diffusion
EE 330 Lecture 8 IC Fabrication Technology Part II?? - Masking - Photolithography - Deposition - Etching - Diffusion Review from Last Time Technology Files Provide Information About Process Process Flow
More information