Development of an Low Cost Wafer Level Flip Chip Assembly Process for High Brightness LEDs Using the AuSn Metallurgy

Transcription

1 Development of an Low Cost Wafer Level Flip Chip Assembly Process for High Brightness LEDs Using the AuSn Metallurgy Gordon Elger, Rafael Jordan, Maria v. Suchodoletz and Hermann Oppermann Fraunhofer Institute for Reliability and Microintegration Berlin, Germany Abstract A low cost wafer level packaging process for bumped flip-chip LEDs (light emitting diodes) is demonstrated. The GaAlAs-LEDs are picked from blue tape and placed on the silicon 4"-substrate wafer containing more than 2000 single substrates. After reflow soldering in an infrared oven under active atmosphere, the wafer is diced and the components are individualized. The pick and place process, the tacking of the LEDs on the wafer and the reflow soldering process are investigated to obtain a high process yield. Due to the flip chip design all electrical contacts are formed in one assembly step and wire bonding isn't necessary. Another advantage is the good heat transfer to the substrate due to the p-side down connection that allows high current and therefore high brightness of the LED. Au80Sn20 solder is used for the electrical and mechanical interconnection. The AuSn solder is applied in different ways: Sn is either electroplated on the Au-contacts of the LEDs or as a pad on the Au metallization of the substrates. The metallurgy of the solder process and the reliability of the LEDs are investigated. The amount of Au and Sn was adjusted, i.e. the thickness of the electroplated Au and Sn layers, to achieve interconnections formed by the intermetallic phases AuSn and ζ of the Au80Sn20 eutectic solder. Due to the good mechanical properties, the good thermal conductivity and the low growth of intermetallic phases the reliability of the contacts is very high. It is demonstrated that the performance of the LED is excellent and the degradation is very small. Due to the high melting point of Au80Sn20 solder (278 C) the component can be used in SMD processes without remelting of the LED contacts. Introduction Since LEDs were developed in the 1960 th the market has grown rapidly. Constantly, the efficiency and the brightness of the LEDs have been increased by the employment of new technologies. Flip-Chip LEDs (FC-LEDs) have the n- and p- contact on one side. All electric contacts can be joined to the substrate in one assembly step. The assembly process, investigated in this paper, was developed for a high brightness FC-LED, which has one p- and two n-contact (see Fig. 1), manufactured by the company EPIGAP. The p- and the n-contact are in the same plane. This is achieved by an etching technique for GaAs (see Fig. 2). The flip-chip is used to realize high power LEDs on a small area without any wire bond. The chip is soldered with the contacts on a SMD-type carrier. The light is emitted to the rear side of the chip intensified by the reflector. No bonding wire disturbs the light output. Because the p-n-junction is near to the area of the electrical contact, which itself can be soldered directly on a heat sink, the heat transfer is excellent. High current and, therefore, high radiant output power can be achieved. Without wire bonds the reliability is improved compared to standard devices and lens n p silicon substrate Fig. 1 Flip-Chip LED on substrate solder joint handling is easier. Also arrays of flip-chip-leds can be realized with very narrow distances between the single devices due to the low thermal resistance of the assembly. To increase the reliability of the component the metallurgy of the solder joints were modified. Instead of tin-rich solder joints Au-rich solder joints (Au80Sn20) were established. The substrate metallization was redesigned in a way that the project partner EPIGAP is still able to perform the plating in his own facilities. Au80Sn20 (gold 80wt% and tin 20wt%) is a reliable solder applied for flip-chip assemblies. A detailed description of the technical application is given in [1,2]. An advantage for optoelectronic n GaAlAs-Chip -red/infrared emission -one sided contacted

2 Assembly Fig. 2 Flip-Chip design components is that the Au80Sn20 solder can be used in a flux-free process. The melting point of Au80Sn20 is 278 C and, therefore, higher than the temperature of SMD reflow processes. The mounted LEDs can be used as SMDs when soldered with Au80Sn20. Reliability investigations were performed to demonstrate the superiority of the achieved Au-rich interconnection compared to the earlier Sn-rich interconnection [3]. Usually, the AuSn solder is used in its eutectic composition as solder preforms, AuSn-bumps or metallization layers on the substrate. Typically, 1.5 µm Au-layer per 1µm Sn-layer is necessary to achieve the Au/Sn ratio of the Au80Sn20 solder. In this paper, the solderability is investigated when the solder compounds, gold and tin, are electroplated separated on different sides. The LED contacts and the substrate pads were Au-plated. Tin was either electroplated on the Au metallized substrate pads or on the Au contacts of the LEDs. The solderability of both layouts were investigated. When the tin is plated on the LED wafer the situation is similar to AuSn chip-wafer bumping described in [4,5,6]. However, usually after electroplating a separated reflow step is performed for forming the eutectic AuSn solder caps of the bump. Fig. 3 BSE picture of a cross section of a LED assembly after reflow (C, 290 C) Fig. 4 Assembled LEDs on a silicon substrate For the assembly two different strategies were investigated. On the one hand single chip thermode bonding on the other hand reflow bonding on wafer level. For the thermode bonding a flip-chip bonder from Karl-Suss with an accuracy of ± 1µm was used. The chip is picked by a vacuum tool (arm) from a waffle pack. The substrate is fixed on the bonding table (chuck) also by vacuum. The chip is aligned on the substrate using a simultaneous up and down looking microscope. After the alignment the chip is placed on the substrate and hold in this position for the whole bonding process with a given small force. Because arm and chuck can be heated separately, the heating profile for soldering can be adjusted taking into account the different thermal mass of chip and substrate. Additionally the manner of melting can be influenced. Maximum heating rates are about 40K/s and a bonding cycle is about 75s. The advantage of thermode bonding is the high accuracy. But heating the tool and changing the substrate for each die increases the bond cycle compared to a simple pick and place process. Using the reflow-process the whole substrate wafer is populated with a maximum rate of 3s/die. The wafer (4") with about 2250 LEDs will than soldered in one step, so the longer soldering cycle of 3-5min is negligible. The common solution for the packaging of the LEDs is the following process: The LEDs are offered face up on blue tape; the LEDs are flipped by a flip-unit during the picking process of the machine. The dies were detached from the blue tape using a die eject system with a small needle. After flipping, the LEDs are placed on the substrate wafer. Important for the process yield is the tacking of the LEDs because the populating of the wafer takes more than one hour. After reflowing the

3 whole wafer (Fig. 4), the components are individualized by dicing the wafer. For automatic assembly an apm2200 from DATACON with an maximum accuracy of ± 10µm was used. Running the common way of placing the LEDs have shown, that the vacuum tool can not grip the die on the bump side as reliable as on the flat surface. Additionally flipping the die needs more time. Therefore the LEDs are now placed face down on the blue tape to avoid the flipping step. Picking the LEDs with the bond arm is less difficult because it can be synchronized with the needle system. This prevent from damaging the sensitive LEDs. To increase the gripping force of the pick and place arm a special rectangle tool with the exact size of the LED was build. Under this conditions a reliable pick and place process can be run (Fig. 5). Fig. 5 Part of a soldered wafer To increase the picking time from the blue tape it is still under investigation to use a green tape. The green tape looses his adhesion by heating to about 90 C. AuSn metallurgy The metallurgy of the AuSn system has been discussed earlier [1,4-6]. The phase diagram is shown in Fig. 6 [7]. The first Sn-rich eutectic Au10Sn90 forms at 217 C. The Sn-rich eutectic consists of Sn and AuSn 4. The Au10Sn90 eutectic is known to be brittle. With increasing Au content the Au-richer intermetallic phases AuSn 2 and AuSn can be observed. The melting point of the Au-rich eutectic Au80Sn20 is 278 C. It is formed by the solid phases AuSn and ζ (Au 5 Sn). Increasing the temperature more Au can be dissolved in the liquid phase. If excess Au is available at a given Fig. 6 AuSn-phase diagramm [7] temperature formation of ζ-phase is observed. The growth of the ζ-phase is diffusion controlled and, therefore, depends on the thickness of the ζ-phase layer. Although the growth rate is quite small, a four micron thick ζ-phase layer forms at 290 C in 25s. The ζ-phase is stable up to 519 C; it has good mechanical properties, i.e. a lower Vickers microhardeness than eutectic Au80Sn20, an increased thermal conductivity and an excellent reliability [5,8]. Therefore, it is suited also for high power applications [9]. Contacts formed by the ζ- phase don t remelt at the Au80Sn20 reflow temperature any more and show a better performance [6]. Working with the ζ-phase offers the possibility to use the fluxfree AuSn metallurgy on different assembly hierarchies of optoelectronic modules without remelting the interconnections soldered at previous assembly steps. Metallization chip pad substrate A B C D 6 m µ Au m µ Sn 10 m µ Au 4 m µ Sn tin on substrate 10 m µ Au 7 m µ Au 5 m µ Au Sn Au 3-5 m µ Au bumped LED Fig. 7 Metallization scheme. GaAlAs Chip: Au electroplated on an AuGe contact, silicon substrate: Sn electroplated on 3 µm Cu/0.5 µm Ti. For the assembly C, the Sn is patterned (undersize pad) and an Au layer is introduced between Cu-layer and Sn-pad. For metallization type D the LED wafer was bumped by plating 5µm tin on 7µm Au contacts. For the previous tin-rich solder contacts the silicon substrate was metallized as follows: 10 µm Sn-

4 layer over 3 µm Cu and 0.5 µm Ti. The chip was electroplated with 3-6 µm Au over an AuGe contact (metallization type A, Fig. 7). The thickness of the metallization was changed to form interconnections with the Au-rich Au80Sn20 solder. In Fig. 7 the different metallization types are shown schematically. The thickness of the Sn-layer could not be reduced to less than 4 µm due to the electroplating process of EPIGAP. Therefore, the Au-layer on the contacts of the chip was increased to 10 µm and the Sn-layer was decreased to 4 µm (metallization type B, Fig. 7). In a second step, a gold layer was introduced on the Si substrate over the Cu-layer. This Au-layer has two functions: One is to increase the amount of Au, the other is that an Au-layer on Cu can separate the AuSn solder from the Cu which effects long time reliability [10 Zakel (1994)]. The Sn was patterned on the Au-layer (metallization type C, Fig. 7). The pad size is crucial for the assembly. As the pad formed by the tin was larger than the gold pad on the LED (case A and B, Fig. 7), the excessive tin flew into the joining area. By using undersized pads the amount of tin was reduced without having to reduce the thickness. Because of the excellent wetting properties of AuSn solder, the interconnection area is not decreased by using undersized pads (see Fig. 10). Finally, the LED wafer was bumped by plating 5µm tin on 7µm Au contacts (metallization type D). The substrates used for soldering this bumped LEDs had 3-5µm Au on a Ti adhesion layer. Reflow soldering of LEDs The metallurgic phases of the solder joints were investigated with a scanning electron microscope using the BSE modus (back scattered electron). Using metallization type A at a reflow temperature of 280 C the Sn-rich eutectic (see Fig. 8, top) was observed. Often cracks appear directly after cooling down to room temperature (see Fig. 8, top). With increased Au content (metallization type B) at a higher reflow temperature at 240 C the Au-richer intermetallic phases AuSn 2 and AuSn were observed. In Fig. 9 a cross section of a flip-chip LED after reflow at 240 C is shown. Using metallization type C at a reflow temperature of 290 C a typical Au80Sn20 interface was obtained (see Fig. 10). Because the Au was offered from chip and substrate side the eutectic Au80Sn20 is observed between ζ phase layers growing on chip and substrate interface (see Fig. 11). Reliable ζ- phase interconnection where achieved in a wide parameter range ( C) with the bumped LED (metallization type D). Fig. 8 BSE picture of a LED after reflow (A, 280 C) The bright domains are AuSn 4 and the dark domains pure Sn. Notable is the crack (top). Large cracks were often found in the Au10Sn90 eutectic (AuSn 4 /Sn domains). With excess of Sn, the typical structure of the eutectic Au10Sn90 is found (bottom). Because the Sn-layer was larger than the Au-pad of the chip, large amounts of solder flew into the joint area. Au AuSn AuSn2 η Fig. 9 BSE picture of the solder interconnection of a LED (B,240 C). The phase η contains 50% Sn, 25% Au and 25%Cu (at%).

5 The yield of the solder process is better than 98% using solder temperatures between 325 C and 350 C. Over 50 LEDs were aged for 120h or 240h at 200 C or cycled between -40 C and +150 C for 500 times. Neither the voltage drop increased nor the luminance decreased for any LED and the shear values were within the normal range. Due to the formation of Kirkendall voids it was observed earlier that the tin caps of AuSn electroplated bumps fall off if no reflow is performed. For the FC-LED we could show that the reflow step can be omitted and LED wafer were used that were plated more than three month before assembly without a decrease of yield and shear values. Fig. 10 BSE picture of a solder joint of the LED. (C,290 C). The connection is formed by the eutectic Au80Sn20. ζ phase layers (bright phase) grow at the chip and at the substrate side. Fig. 11 BSE picture of an interconnection of a LED (D, 350 C) formed by the ζ phase. Reliability The reliability of the solder joint formed by tin-rich and gold-rich eutectic AuSn solder was compared earlier [3]. Here we focus on the comparison between gold-rich interfaces of the metallization type C and D. The shear values of the bumped LEDs (metallization type D) are significant higher than the shear values of metallization type C. For the layout C different shear modes were observed (chip breaking, partly solder joint, pad lift on substrate side). Sometimes not all three Au contacts of the LED were wetted by the tin. Because the tin pads were undersized a competition between wetting of the full Au substrate pad and wetting of the LED Au contact proceed. In contrast, for the layout D solely chip breaking was observed and the values are between 400cN and 900cN. This is due to the improved wetting situation of the layout C. f Conclusions and Outlook A low cost FC-process was developed for soldering the electric contacts of LEDs with Au80Sn20 suited to the plating process of EPIGAP. The automatic pick and place process was investigated. On a apm2200 from Datacon a throughput of 3 s/units could be achieved. It was shown that reliable Au80Sn20 solder joints can be achieved with ζ-phase layers formed on the substrate and on chip side. Pure ζ-phase interconnections are formed in case of sufficient Au-excess. For bumped LEDs a very reliable solder process was established with a high yield (better than 98%) and a wide process window. The next step will be the transfer of the wafer level process from silicon wafers to ceramic wafers. Bumped FC-LEDs were soldered on single ceramic carriers which can be individualized just by breaking. The ceramic LED carrier will have the advantage of through connection and the components will function as real SMD devices (see Fig. 12). Fig. 12 LED on a ceramic carrier

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