Semiconductor Manufacturing Technology. IC Fabrication Process Overview
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1 Semiconductor Manufacturing Technology Michael Quirk & Julian Serda October 00 by Prentice Hall Chapter 9 IC Fabrication Process Overview /4
2 Objectives After studying the material in this chapter, you will be able to:. Draw a diagram showing how a typical wafer flows in a sub-micron CMOS IC fab.. Give an overview of the six major process areas and the sort/test area in the wafer fab. 3. For each of the 4 CMOS manufacturing steps, describe its primary purpose. 4. Discuss the key process and equipment used in each CMOS manufacturing step. /4
3 Major Fabrication Steps in MOS Process Flow UV light oxygen Silicon dioxide photoresist Mask exposed photoresist oxide Silicon substrate Oxidation (Field oxide) Photoresist Coating Mask-Wafer Alignment and Exposure Exposed Photoresist Photoresist Develop RF Power RF Power RF Power RF Power Ionized CF 4 gas photoresist oxide Ionized oxygen gas oxide oxygen gate oxide Dopant gas Silane gas polysilicon Ionized CCl 4 gas oxide poly gate Oxide Photoresist Strip Oxidation (Gate oxide) Polysilicon Deposition Polysilicon Mask and Scanning ion beam silicon nitride Contact holes Metal contacts ox S Ion Implantation resist resist G D S G D Active Regions S top nitride G Used with permission from Advanced Micro Devices D Nitride Deposition Figure 9. S G D Contact drain G S D Metal Deposition and 3/4
4 CMOS Process Flow Overview of Areas in a Wafer Fab Diffusion Photolithography Ion Implant Thin Films Polish CMOS Manufacturing Steps Parametric Testing 6~8 weeks involve 350-step 4/4
5 Model of Typical Wafer Flow in a Sub-Micron CMOS IC Fab Wafer Fabrication (front-end) Wafer Start Unpatterned Wafer Thin Films Polish Completed Wafer Diffusion Photo Test/Sort Implant 6 major production areas Figure 9. 5/4
6 Diffusion: Simplified Schematic of High- Temperature Furnace Temperature controller Thermocouple measurements Gas flow controller Process gas Quartz tube Temperaturesetting voltages Heater Heater Heater 3 Three-zone Heating Elements Can do : oxidation, diffusion, deposition, anneals, and alloy Pressure controller Exhaust Figure 9.3 6/4
7 Photolithography Bay in a Sub-micron Wafer Fab Yellow fluorescent: do not affect photoresist Photo 9. 7/4
8 Simplified Schematic of a Photolithography Processing Module Load Station Vapor Prime Resist Coat Develop- Rinse Edge-Bead Removal Transfer Station Wafer Stepper (Alignment/Exposure System) Wafer Cassettes Wafer Transfer System Soft Bake Cool Plate Cool Plate Hard Bake Note: wafers flow from photolithography into only two other areas: etch and ion implant Figure 9.4 8/4
9 Simplified Schematic of Dry Plasma er Gas distribution baffle ant gas entering gas inlet High-frequency energy Anode electrode RF coax cable Electromagnetic field Free electron e - e - λ Photon Glow discharge (plasma) Ion sheath e - Vacuum gauge Wafer Chamber wall Positive ion + R Radical chemical Vacuum line Cathode electrode Flow of byproducts and process gases Exhaust to vacuum pump Figure 9.5 9/4
10 Simplified Schematic of Ion Implanter Gas cabinet Ion source Filament Plasma Extraction assembly Analyzing magnet Ion beam Lighter ions Mass resolving slit Acceleration column Beamline tube Process chamber Heavy ions Graphite Scanning disk Figure 9.6 0/4
11 Thin Film Metallization Bay Photo courtesy of Advanced Micro Devices Photo 9. /4
12 Simplified Schematics of CVD Processing System Gas inlet Process chamber Capacitivecoupled RF input Chemical vapor deposition Wafer Susceptor Exhaust Heat lamps CVD cluster tool Figure 9.7 /4
13 Polish Bay in a Sub-micron Wafer Fab Photo courtesy of Advanced Micro Devices Photo 9.3 3/4
14 . Twin-well Implants. Shallow Trench Isolation 3. Gate Structure 4. Lightly Doped Drain Implants 5. Sidewall Spacer 6. Source/Drain Implants 7. Contact Formation 8. Local Interconnect 9. Interlayer Dielectric to Via- 0. First Metal Layer. Second ILD to Via-. Second Metal Layer to Via-3 3. Metal-3 to Pad 4. Parametric Testing CMOS Manufacturing Steps 8 LI metal n + 7 Via M-4 M-3 9 Passivation layer M- M- Poly gate 3 LI oxide p + p + STI n + n n-well ILD ILD-5 ILD-4 ILD-3 ILD- ILD- p - Epitaxial layer p + Silicon substrate 6 p-well 4 Bonding pad metal p + 4/4
15 n-well Formation Epitaxial layer : improved quality and fewer defect In step, initial oxide: () protects epi layer from contamination, () prevents excessive damage to ion/implantation, (3) control the depth of the dopant during implantation In step 5, anneal: () drive-in, () repair damage, (3) activation Phosphorus implant Thin Films Polish 3 Photoresist Diffusion Photo Implant Oxide 5 4 n-well p- Epitaxial layer ~5 um p+ Silicon substrate (Dia = 00 mm, ~ mm thick) Figure 9.8 5/4
16 p-well Formation Boron implant Thin Films Polish Photoresist Diffusion 3 Photo Implant Oxide n-well p-well p- Epitaxial layer 3 p+ Silicon substrate Figure 9.9 6/4
17 STI Trench STI: shallow trench isolation. Barrier oxide: a new oxide. Nitride: () protect active region, () stop layer during CMP 3. 3 rd mask 4. STI etching Selective etching opens isolation regions in the epi layer. Thin Films Polish Photoresist Nitride +Ions 4 Diffusion Photo Oxide n-well p-well Implant STI trench p- Epitaxial layer p+ Silicon substrate Figure 9.0 7/4
18 STI Oxide Fill. Liner oxide to improve the interface between the silicon and trench CVD oxide. CVD oxide deposition Trench fill by chemical vapor deposition Oxide Thin Films Polish Trench CVD oxide Nitride Diffusion Photo Implant Liner oxide n-well p- Epitaxial layer p-well p+ Silicon substrate Figure 9. 8/4
19 STI Formation. Trench oxide polish (CMP): nitride as the CMP stop layer since nitride is harder than oxide. Nitride strip: hot phosphoric acid Thin Films Polish Planarization by chemical-mechanical polishing STI oxide after polish Nitride strip Diffusion Photo n-well p-well Liner oxide Implant p- Epitaxial layer p+ Silicon substrate Figure 9. 9/4
20 Poly Gate Structure Process. Oxide thickness.5 ~ 5.0 nm is thermal grown. Poly-Si ~ 300 nm is doped and deposited in LPCVD using SiH4 3. Need Antireflective coating (ARC), very critical 4. The most critical etching step in dry etching Thin Films Polish 3 4 Polysilicon deposition Gate oxide 3 Photoresist ARC 4 Poly gate etch Diffusion Photo n-well p-well Implant p- Epitaxial layer p+ Silicon substrate Figure 9.3 0/4
21 n LDD Implant. LDD: lightly doped drain to reduce S/D leakage. Large mass implant (BF, instead of B, As instead of P) and amorphous surface helps maintain a shallow junction 3. 5 th mask Arsenic n- LDD implant Thin Films Polish Photoresist mask Diffusion Photo n- n-well n- p-well n- Implant p- Epitaxial layer p+ Silicon substrate Figure 9.4 /4
22 p LDD Implant. 6th mask. In modern device, high doped drain is used to reduce series resistance. It called S/D extension BF p- LDD implant Thin Films Polish Photoresist Mask Photoresist mask Diffusion Photo n- p- n-well p- n- p-well n- p- Implant p- Epitaxial layer p+ Silicon substrate Figure 9.5 /4
23 Side Wall Spacer Formation Spacer is used to prevent higher S/D implant from penetrating too close to the channel Spacer etchback by anisotropic plasma etcher Thin Films Polish +Ions Spacer oxide Side wall spacer Diffusion Photo n- p- p- n- n- n-well p-well p- Implant p- Epitaxial layer p+ Silicon substrate Figure 9.6 3/4
24 n + Source/Drain Implant. Energy is high than LDD I/I, the junction is deep. 7 th mask Arsenic n+ S/D implant Thin Films Polish Photoresist mask Diffusion Photo n+ n-well n+ n+ p-well Implant p- Epitaxial layer p+ Silicon substrate Figure 9.7 4/4
25 p + Source/Drain Implant. 8th mask. Using rapid thermal anneal (RTA) to prevent dopant spreading and to control diffusion of dopant Boron p+ S/D implant Thin Films Polish Photoresist Mask Photoresist mask Diffusion 3 Photo n+ p+ n-well p+ n+ p-well n+ p+ Implant p- Epitaxial layer p+ Silicon substrate Figure 9.8 5/4
26 Contact Formation. Titanium (Ti) is a good choice for metal contact due to low resistivity and good adhesion. No mask needed, called self-align 3. Using Ar to sputtering metal 4. Anneal to form TiSi, tisilicide 5. Chemical etching to remove unreact Ti, leaving TiSi, called selective etching Titanium depostion 3 Thin Polish Tisilicide contact formation (anneal) Films Titanium etch 3 Diffusion Photo n+ p+ n-well p+ n+ p-well n+ p+ Implant p- Epitaxial layer p+ Silicon substrate Figure 9.9 6/4
27 LI Oxide as a Dielectric for Inlaid LI Metal (Damascene) Damascene: a name doped of year ago from a practice that began thousands ago by artist in Damascus, Syria LI metal LI oxide LI: local interconnection Figure 9.0 7/4
28 LI Oxide Dielectric Formation. Nitride: protect active region. Doped oxide 3. Oxide polish 4. 9 th mask Doped oxide CVD Thin Films 3 Polish Nitride CVD 3 Oxide polish LI oxide 4 LI oxide etch 4 Diffusion Photo p-well p-well Implant p- Epitaxial layer p+ Silicon substrate Figure 9. 8/4
29 LI Metal Formation Ti/TiN is used: Ti for adhesion and TiN for diffusion barrier Tungsten (W) is preferred over Aluminum (Al) for LI metal due to its ability to fill holes without leaving voids 3 4 Thin Films Polish Ti/TiN deposition 3 Tungsten deposition LI oxide 4 LI tungsten polish Diffusion Photo Implant n-well p-well Ti deposition p- Epitaxial layer p+ Silicon substrate Figure 9. 9/4
30 Via- Formation. Interlayer dielectric (ILD): insulator between metal. Via: electrical pathway from one metal layer to adjacent metal layer 3. 0 th mask ILD- oxide deposition Oxide polish 3 ILD- oxide etch (Via- formation) Thin Films Polish ILD- LI oxide Diffusion Photo 3 n-well p-well Implant p- Epitaxial layer p+ Silicon substrate Figure /4
31 Plug- Formation. Ti layer as a glue layer to hold W. TiN layer as the diffusion barrier 3. Tungsten (W) as the via 4. CMP W-polish Ti/TiN deposition 3 Tungsten deposition 4 Tungsten polish (Plug-) 3 4 Thin Films Polish Ti dep. ILD- LI oxide Diffusion Photo n-well p-well Implant p- Epitaxial layer p+ Silicon substrate Figure 9.4 3/4
32 SEM Micrographs of Polysilicon, Tungsten LI and Tungsten Plugs Tungsten LI Polysilicon Tungsten plug Mag. 7,000 X Micrograph courtesy of Integrated Circuit Engineering Photo 9.4 3/4
33 Metal- Interconnect Formation. Metal stack: Ti/Al (or Cu)/TiN is used. Al(99%) + Cu (%) is used to improve reliability 3. th mask Ti Deposition Al + Cu (%) deposition TiN 3 4 deposition Metal- etch 3 Thin Films Polish ILD- LI oxide Diffusion Photo 4 n-well p-well Implant p- Epitaxial layer p+ Silicon substrate Figure /4
34 SEM Micrographs of First Metal Layer over First Set of Tungsten Vias TiN metal cap Metal, Al Tungsten plug Mag. 7,000 X Micrograph courtesy of Integrated Circuit Engineering Photo /4
35 Via- Formation. Gap fill: fill the gap between metal. Oxide deposition 3. Oxide polish 4. th mask ILD- oxide deposition 3 Oxide polish 4 ILD- oxide etch (Via- formation) ILD- gap fill Thin Films 3 Polish ILD- LI oxide 4 Diffusion Photo n-well p-well Implant p- Epitaxial layer p+ Silicon substrate Figure /4
36 Plug- Formation. Ti/TiN/W. CMP W polish Ti/TiN deposition 4 Tungsten polish Tungsten deposition (Plug-) 3 Ti deposition ILD- 3 4 Thin Films Polish ILD- LI oxide Diffusion Photo n-well p-well Implant p- Epitaxial layer p+ Silicon substrate Figure /4
37 Metal- Interconnect Formation. Metal : Ti/Al/TiN. ILD-3 gap filling 3. ILD-3 4. ILD-polish 5. Via-3 etch and via deposition, Ti/TiN/W Metal- deposition to etch ILD-3 oxide 3 4 Via-3/Plug-3 formation polish Gap fill ILD-3 ILD- ILD- LI oxide n-well p-well p- Epitaxial layer p+ Silicon substrate Figure /4
38 Full 0.8 µm CMOS Cross Section Passivation layer ILD-6 Bonding pad metal. Passivation layer of nitride is used to protect from moisture, scratched, and contamination. ILD-6 : oxide M-4 M-3 M- ILD-5 ILD-4 ILD-3 ILD- M- Via ILD- LI metal Poly gate LI oxide n + p + p + STI n + n + p + n-well p-well p - Epitaxial layer Figure 9.9 p + Silicon substrate 38/4
39 SEM Micrograph of Cross-section of AMD Microprocessor Mag. 8,50 X Micrograph courtesy of Integrated Circuit Engineering Photo /4
40 Wafer Electrical Test using a Micromanipulator Prober (Parametric Testing). After metal- etch, wafer is tested, and after passivation test again. Automatically test on wafer, sort good die (X- Y position, previous marked with an red ink) 3. Before package, wafer is backgrind to a thinner thickness for easier slice and heat dissipation Photo courtesy of Advanced Micro Devices Photo /4
41 Chapter 9 Review Summary Key Terms 3 Review Questions 3 SMT Web Site References 4 4/4
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