Microelectronics Reliability

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1 Microelectronics Reliability 5 (21) Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: Design and optimization of thermo-mechanical reliability in wafer level packaging X.J. Fan a,b, *, B. Varia a, Q. Han b a Department of Mechanical Engineering, Lamar University, P.O. Box 128, Beaumont, TX 7771, USA b College of Civil Engineering and Transportation, South China University of Technology, Guangzhou, PR China article info abstract Article history: Received 4 July 29 Received in revised form 16 November 29 Available online 29 January 21 In this paper, a variety of wafer level packaging (WLP) structures, including both fan-in and fan-out WLPs, are investigated for solder joint thermo-mechanical reliability performance, from a structural design point of view. The effects of redistribution layer (RDL), bump structural design/material selection, polymer-cored ball application, and PCB design/material selection are studied. The investigation focuses on four different WLP technologies: standard WLP (ball on I/O WLP), ball on polymer WLP without under bump metallurgy (UBM) layer, ball on polymer WLP with UBM layer, and encapsulated copper post WLP. Ball on I/O WLP, in which solder balls are directly attached to the metal pads on silicon wafer, is used as a benchmark for the analysis. 3-D finite element modeling is performed to investigate the effects of WLP structures, UBM layer, polymer film material properties (in ball on polymer WLP), and encapsulated epoxy material properties (in copper post WLP). Both ball on polymer and copper post WLPs have shown great reliability improvement in thermal cycling. For ball on polymer WLP structures, polymer film between silicon and solder balls creates a cushion effect to reduce the stresses in solder joints. Such cushion effect can be achieved either by an extremely compliant film or a hard film with a large coefficient of thermal expansion. Encapsulated copper post WLP shows the best thermo-mechanical performance among the four WLP structures. Furthermore, for a fan-out WLP, it has been found that the critical solder balls are the outermost solder balls under die-area, where the maximum thermal mismatch takes place. In a fan-out WLP package, chip size, other than package size, determines the limit of solder joint reliability. This paper also discusses the polymer-cored solder ball applications to enhance thermo-mechanical reliability of solder joints. Finally, both experimental and finite element analysis have demonstrated that making corner balls non-electrically connected can greatly improve the WLP thermomechanical reliability. Ó 29 Elsevier Ltd. All rights reserved. 1. Introduction * Corresponding author. Address: Department of Mechanical Engineering, Lamar University, P.O. Box 128, Beaumont, TX 7771, USA. Tel.: ; fax: address: xuejun.fan@lamar.edu (X.J. Fan). Wafer level packaging (WLP) is one of the fast growing segments in semiconductor packaging industry due to the rapid advances in integrated circuit (IC) fabrication and the demands of a growing market for faster, lighter, smaller, yet less expensive electronic products with high performance and low-cost packaging [1 3]. WLPs are mainly used for low pin-count and small die-size applications, such as analog devices, power management devices, image sensors, integrated passives, and memory devices. More WLPs appear in handheld devices such as cellular phones. WLP is an advanced packaging technology, in which the dies or packages are fabricated and tested at the wafer level before singulation. By performing batch wafer level testing and packaging, the processing costs can be brought down significantly. Many IC makers are incorporating WLP into their designs, and migrating from traditional wirebond interconnection to WLP solutions. As such, a paradigm shift to wafer level packaging is apparent. It is well understood that solder joint thermo-mechanical reliability performance become a critical concern of WLPs with larger die packages [3,4]. The ability of solder joint to survive the required thermal cycle testing has limited the WLPs to the products having relatively small die-sizes and a small number of I/O. The intrinsic difference in the coefficient of thermal expansion (CTE) between silicon (2.6 ppm/ C) and PCB (16 ppm/ C) determines that the solder ball thermal cycling fatigue performance is limited by diesize. However, there has been a demand for WLP development with larger die, finer pitch and higher functionality applications. Consequently, there is an urgent need to develop new WLP technologies to address this concern of meeting reliability requirement for large array WLPs. A variety of WLP technologies have been developed in recent years to improve the thermo-mechanical reliability performance for large array WLPs. Standard WLP, which is similar to a typical flip chip technology, has evolved with the incorporation /$ - see front matter Ó 29 Elsevier Ltd. All rights reserved. doi:1.116/j.microrel

2 X.J. Fan et al. / Microelectronics Reliability 5 (21) of redistribution layer (RDL) process [4 7], copper post process [8], and compliant layer process [9]. These WLP structures have demonstrated the significant enhancement and improvement on solder joint reliability [4 9]. In general, there are two categories of WLP technologies: fanin WLP, and fan-out WLP. In fan-in WLP packages, chip area is equal to the package area, as shown in Fig. 1. The number of I/O is limited by die-size. In order to develop ultra large array WLPs, fan-out wafer level packaging technologies have emerged recently, such as embedded wafer-level ball grid array (ewlb) technology, and redistributed chip packaging (RCP) technology [1,11]. In a fan-out WLP process, wafer reconfiguration and wafer molding technology are needed. Fan-out WLP technologies have extended WLPs to the next stage with a great extension of pin-count. Fig. 1 is a schematic for the comparison between a fan-in WLP and a fan-out WLP. There are many factors that affect the thermo-mechanical reliability of solder joints in WLP packages. Polymer film layer, in which redistribution traces are embedded, serve as a stress buffer layer to reduce the stress level in solder joints. It is generally conceived that the high compliance of polymer film (e.g., low Young s modulus) results in solder joint stress reduction [12]. Ball shape, geometry, standoff height, and material also play an important role in thermo-mechanical performance of WLPs [13 2]. Previous works have demonstrated that a greater standoff height with a slim ball-shape offer improved reliability performance. In addition, PCB design and material selection also contribute significantly to WLP s reliability. In this paper, a variety of WLP structures, which include both fan-in and fan-out WLPs, are studied for solder joint reliability performance, from a structural design point of view. Standard WLP structure, i.e., ball on I/O, is used as a benchmark to compare with other WLP configurations, such as ball on polymer WLP without UBM layer, ball on polymer WLP with UBM layer, and encapsulated copper post WLP. Finite element models for various WLP structures are developed and analyzed. The effects of WLP structures, UBM process, polymer film material properties (in ball on polymer), and encapsulated epoxy material properties (in copper post WLP), are investigated in detail. The solder joint reliability for a fan-out WLP is analyzed to compare with fan-in WLPs. In addition, the effect of polymer-cored solder ball connection is discussed. Other considerations to improve solder joint reliability, such as the use of dummy balls at corner locations, the effect of PCB design, and PCB core material selection, are also discussed in this paper. Fig. 2. WLP Structure A: (a) Ball on I/O; and (b) ball on Nitride with RDL. from the die peripheral I/O to the new desired bump locations, as shown in Fig. 2b. Although these two structures shown in Fig. 2 are different, the added redistribution layer and the passivation layer in Fig. 2b do not provide additional benefit to solder joint reliability performance. The solder balls in these two structures are both directly connected to silicon base. It has been well reported that WLP Structure A is limited to 6 6 array size (or less) at.5 mm pitch to meet the thermal cycling reliability requirement [3 6] WLP Structure B ball on polymer without under bump metallurgy (UBM) layer Fig. 3 is a schematic of ball on polymer WLP structure without UBM layer. In this structure the solder ball is placed over RDL pad on a stack of polymer dielectric materials. Two layers of dielectric materials (usually polyimide) are processed, named polymer 1 and polymer 2, respectively, to serve as passivation and redistribution layers. Redistribution traces and pads are processed with electroplating using copper, which makes it possible to attach solder balls directly on RDL pads without UBM layer. This WLP structure is different from WLP Structure A in Fig. 2b, although in both cases the redistributions are used. In Fig. 3, a 2. Fan-in WLPs 2.1. WLP Structure A ball on I/O structure Ball on I/O WLP is a standard wafer level packaging technology and the process is very similar to a typical flip chip technology. As shown in Fig. 2a, the ball is attached to the aluminum pad directly through under bump metallurgy (UBM) structure. The redistribution layer (RDL) process can be added to re-route the signal path Fig. 3. WLP Structure B: ball on polymer without UBM layer. Fig. 1. Fan-in and fan-out WLP packages.

3 538 X.J. Fan et al. / Microelectronics Reliability 5 (21) polymer dielectric film layer is placed between solder ball and silicon base. Such a layer will act as stress buffer when thermal mechanical stress is subjected due to thermal mismatch between PCB and silicon during temperature change. Consequently, the stresses applied to solder balls will be reduced. Detailed finite element analysis will be performed in the subsequent analysis. It has been demonstrated experimentally [7] that with WLP Structure B, the array size can be extended to with.5 mm pitch while meeting reliability requirement WLP Structure C ball on polymer with UBM layer Fig. 4 is a schematic of WLP Structure C for ball on polymer WLP with UBM layer. Since UBM process is added, manufacturing cost might be higher. Similar to WLP Structure B, solder balls in WLP Structure C sit on a dielectric polymer film layer to avoid a direct connection with silicon base. The effect of UBM structure will be investigated in the subsequent analysis. Fig. 6. Copper post formation before encapsulation on wafer [8] WLP Structure D encapsulated copper post WLP Fig. 5 is a schematic of a copper post WLP structure. Thick copper pillars (7 lm) are electroplated, followed by an epoxy encapsulation. Fig. 6 is a picture of copper post formation on wafer before molding process [8]. The difference between WLP Structure B (ball on polymer) and copper post WLP is that a thick copper/ epoxy layer is placed on the top of polymer film before the ball attachment. Such a structure has demonstrated superior thermomechanical reliability performance. 3. Fan-out WLPs In fan-in WLP packages, chip area is equal to the package area, thus the number of I/O is limited. In addition, fan-in WLPs are subject to front-end yield, therefore, both front-end good dies and front-end bad dies are packaged. Fan-in WLP is bare die package, which is fragile and difficult in handling during test, assembly and surface mount. Fan-out WLP eliminates those restrictions. Fig. 7 is a cross-section schematic view of fan-out WLP. Mold compound is used to carry fan-out array and protect the chip back side. Fig. 7. Schematic view of a cross-section of a fan-out WLP. From a structural point of view, fan-out WLP is very similar to a typical ball grid array (BGA) package, in which a substrate or interposer is used. However, fan-out WLPs are substrate-less wafer level packages, which are fabricated and tested at wafer level. Fig. 8 depicts a general flow of fan-out WLP process. Wafer reconfiguration is needed with a wafer molding process. Since a fan-out WLP is structurally similar to a BGA package, solder joint thermo-mechanical behaviors in a fan-out WLP is similar to a BGA package. The critical solder balls in a fan-out WLP are located beneath silicon chip area, where the maximum CTE mismatch occurs between silicon and PCB [21]. 4. Finite element modeling 4.1. Structural model Fig. 4. WLP Structure C: ball on polymer with UBM layer. Four fan-in WLP Structures A D are considered first. The detailed geometry information of the four WLP structures is shown in Fig. 9. In the present study, the ball pitch for all structures is.5 mm, and the solder ball opening diameter on silicon side is fixed as.25 mm. The PCB side is assumed to be non-solder mask defined (NSMD). Other important geometrical dimensions of the four structures are shown in Table 1. Copper post Epoxy RDL / Passivation Silicon Fig. 5. WLP Structure D: encapsulated copper post WLP.

4 X.J. Fan et al. / Microelectronics Reliability 5 (21) Fig. 8. General process of fan-out WLP [1]. a Silicon Metal pad RDL / passivation b Silicon Passivation Pl Polymer 1 Polymide UBM Solder ball PCB pad Polymer 2 RDL pad Solder ball PCB pad Pi Printed tdcircuit it board Printed circuit board c Silicon Passivation i Polymer 1 Polymer 2 RDL pad UBM Sld Solder bll ball PCB pad d Silicon Passivation / Redistribution Epoxy Copper post Solder ball PCB pad Printed circuit board Pi Printed tdcircuit it board Fig. 9. Schematics of WLP structural models (not scale): (a) WLP Structure A; (b) WLP Structure B; (c) WLP Structure C; and (d) WLP Structure D. Table 1 Geometrical dimensions of the four WLP structures. Dimensions (lm) WLP structure A B C D Silicon thickness Solder ball diameter Solder ball standoff height Solder ball opening diameter PCB pad diameter PCB thickness Wafer Passivation thickness UBM combined thickness Epoxy/copper post thickness 7 Polymer film 1 thickness 5 5 Polymer film 2 thickness Finite element model 3-D finite element models are developed for the four WLP packages. In the present study, we consider only the equal array size of WLP packages in both directions. Thus, the one-eighth model is used, as shown in Fig. 1, according to the symmetry conditions. It is known that the outermost solder balls along the diagonal directions are the most critical ones with the largest thermomechanical stresses. To reduce the possible edge effect of PCB board on the outermost solder ball stresses, the PCB size in the model is extended at least 2.5 times of the package size. ANSYS 11. is used for finite element analysis. The SOLID45 linear element is used for meshing all the materials except solder balls. The VIS- CO17 linear element (8-node element), which describes the viscoplastic material behavior, is used to mesh solder balls. Detailed

5 54 X.J. Fan et al. / Microelectronics Reliability 5 (21) Table 2 Material property details. Fig. 1. One-eighth finite element model for a WLP package on board. finite element mesh patterns at solder ball regions for the four WLP structures are shown in Fig. 11. Based on the experimental observations of the failure mode in solder joints under thermal cycling conditions [3], fatigue cracks occur in solder bulks at package side near the interface of solder bulk/copper or UBM layer. In order to extract the meaningful damage parameters, a fixed thickness layer of 1 lm is created in each finite element model for each WLP structure, as shown in Fig Material model The WLP packages are made up of different materials. A summary of the materials used in the present study is shown in Tables 2 and 3, respectively. All materials except solder alloy are modeled as linear elastic. The temperature dependency can be taken into consideration whenever the glass transition temperature T g is within the thermal cycling range of 4 C to 125 C. The PCB is fiber reinforced epoxies which makes the properties differ in out of Materials Young s modulus (GPa) Coefficient of thermal expansion (ppm/ C) Poisson s ratio Silicon Passivation UBM Aluminum pad RDL pad Epoxy Polyimide Polymer film 1 Polymer film 2 Cu post Solder ball PCB pad PCB Table 3 Anand s model constants for the SAC solder [23]. Constant Value s, MPa 1.3 Q/R, K 9 A, s 1 5 n 7.1 m.3 h, MPa 59 s^, MPa 39.4 n.3 a 1.5 Fig. 11. Finite element models of various WLP structures: (a) WLP Structure A; (b) WLP Structure B; (c) WLP Structure C; and (d) WLP Structure D.

6 X.J. Fan et al. / Microelectronics Reliability 5 (21) per emp Te K) e (K ure ratu First Cycle Second Cycle Third Cycle Fourth Cycle Time (Seconds) Fig. 12. Temperature cycling condition. plane direction. However, the isotropic properties are used here for the PCB since this study is not intended to develop a precise predictive fatigue model. The solder alloy, i.e. SAC35 alloy, is modeled as rate-dependant viscoplastic material using ANAND model [22]. Reinikainen et al. [23] has fitted constants for SAC35 alloy, and the nine constants are shown in Table Loading condition Before subjecting the package to thermal cycling condition, stress-free temperature should be determined. There are three commonly-used initial stress-free temperature conditions. One is the solidus temperature of solder material (e.g., for SAC35, this temperature is 217 C). This condition considers that the solder joints start to provide mechanical support as soon as the solder material is solidified during the reflow process. The second option for stress-free condition is the room temperature as initial stressfree (e.g. 25 C). This assumes that the shipping and storage time is sufficiently long to relax all the residual stresses in solder joints from the assembly process. The last option for stress-free condition uses the high-dwell temperature of thermal cycle or operating conditions (denoted as T max, e.g. = 125 C for thermal cycling from 45 C to 125 C). This assumes that after several thermal cycles, the package reaches a stabilized cyclic pattern where the lowest stresses are seen at the end of the high temperature dwell period. Previous studies have found that, for viscous materials such as solder, regardless of initial stress-free conditions, the structure will readjust the stress state during thermal cycling and will reach a near-stress-free at high-dwell temperature after a few cycles. The studies also showed that the stabilized values of strain or strain energy density per cycle are independent of the initial stress-free setting [24]. Since only per-cycle stabilized values are used in fatigue analysis, it was recommended to use T max as initial stress-free condition to achieve the stabilized solutions quickly. In the present study, 125 C is used as stress-free temperature for thermal cycling loading from 4 C to 125 C. Results showed that the stabilization is even achieved within the first cycle. The packages are simulated with a loading profile shown in Fig. 12. The cycle time each cycle is 6 min, with 15 min during ramp up and down, and 15 min of dwell at 4 C and 125 C, respectively. Since the initial stress-free is selected as 125 C, the stabilization is achieved within the first cycle. The data reported in the subsequent analysis are based on the per-cycle data in the second cycle Per-cycle inelastic strain energy density Usually, the per-cycle inelastic strain (or creep strain) or inelastic strain energy density is used as damage metrics to evaluate solder joint reliability. To prevent any mesh dependency and stress singularity effect at geometry edge, Darveaux [25] and Syed [26] have used a solid thin layer of elements near package/solder interface for volume averaging. As described previously, a 1 lm thickness layer is created for each model with two layers of elements near the interface of solder bulk/ubm layer or copper pad. The volume averaged inelastic energy density over the thin disk (Fig. 13) is defined as follows: P DWi V i DW ave ¼ P ð1þ V 1 where DW ave is the average inelastic strain energy density accumulated per cycle for fixed thickness layer elements, DW i the strain energy density accumulated per cycle for each element i and V i the volume of each element i. It is noted that the accumulated inelastic strain density each cycle comes from the four time-periods during each cycle, i.e., ramp up and down, dwell at high temperature and low temperature respectively [27 31]. 5. Modeling results 5.1. Effect of WLP structures Fig. 13. Volume averaging on a fixed thickness layer. Fig. 14 plots the per-cycle inelastic strain energy densities for the four WLP Structures A D, respectively, for a array packages with.5 mm pitch. Compared to the Structure A, all other

7 542 X.J. Fan et al. / Microelectronics Reliability 5 (21) sity rgy De ens En ner Pa ) tra ain (MP c St stic Ine elas I A B C D WLP Structuret sity De ens nerg gy ) En Pa) in E MP trai (M St tic las nel I Coefficient of Thermal Expansion (ppm/ C) (E=1.2GPa) Fig. 14. Comparison of the thermo-mechanical performance of four WLP structures. Fig. 15. Effect of CTE of polymer film 1 with Young s modulus of 1.2 GPa (WLP Structure B). three Structures B D show more than 3% reduction in the accumulated inelastic strain energy density per cycle. This means that, with the incorporation of a dielectric polymer film between solder balls and silicon, and/or an encapsulated copper post layer, the stresses in solder joints can be reduced significantly compared to a rigid connection in WLP Structure A. WLP Structure D, i.e., the encapsulated copper post WLP, shows the best performance. Experimental data have shown that Structure A WLPs can survive only up to 6 6 array size, while all other three structures can pass thermal cycling reliability requirement up to array size [1,5]. The finite element modeling results are consistent with the experimental observations Effect of UBM layer ity ensi De gy D Energ Pa) rai in E (M MP Str tic last nel In W with compliant film of 1.2GPa Coefficient of fthermal Expansion (ppm/ C) Both Structures B and C are ball on polymer WLP configurations. The difference between these two structures is that Structure B does not have UBM layer. It can be seen from Fig. 14 that the UBM layer has slightly beneficial effect on thermo-mechanical performance of solder joint reliability. Both Structures B and C show superior fatigue resistance due to the introduction of dielectric film layer between solder ball and silicon Effect of polymer film material properties Polyimide film is usually used for polymers 1 and 2 in WLP Structures B and C. From Table 2, it can be seen that polyimide is very compliant with a Young s modulus of 1.2 GPa, and a coefficient of thermal expansion of / C respectively. The extreme compliance of polyimide film is often attributed to be the reason for thermal mechanical performance improvement in solder joints. A parametric matrix study is performed to understand the effects of the Young s modulus and the CTE of the film, as shown in Figs. 15 and 16, respectively. When the modulus is 1.2 GPa, which means that film is extremely compliant, the CTE of the film has negligible effect on solder joint behavior. However, when the film modulus is 1 GPa, the solder joint stress decreases significantly with the increase of the film CTE. When the CTE is above / C, solder joint stress is even lower than that the case with the film Young s modulus of 1.2 GPa. Such results indicate that the stress buffer effect can be realized either with an extreme compliant material or a hard material with a relatively large CTE. For a very soft film, solder joint stresses are relieved due to the large deformation of the film. For a hard film with a larger CTE, the overall CTE of the combined silicon/film structure increases, therefore, the thermal mismatch between the silicon/film stack and the PCB is reduced, and solder joint stresses are reduced Fig. 16. Effect of CTE of polymer film 1 with Young s modulus of 1 GPa (WLP Structure B). as well. The encapsulated copper post WLP structure is similar to the case of a hard film described above. A relatively high CTE of both copper and epoxy in a copper post WLP releases thermal stresses in solder joints Effect of encapsulated copper post structure The CTEs of the encapsulated epoxy and copper post in WLP Structure D are / C and / C, respectively, which are much greater than silicon s CTE. Therefore, the effective CTE of the encapsulated silicon increases effectively. As a result, solder joint stresses are reduced. To understand the effect of material properties of epoxy, a parametric study is performed, as shown in Figs. 17 and 18, respectively. When the CTE of the epoxy is kept at / C, the modulus of epoxy has a nonlinear relationship with DW. It seems an optimal value is around 7 GPa for the lowest solder joint stress. On the other hands, in Fig. 18, it can be seen that further increasing epoxy CTE from / Cto4 1 6 / C will reduce stresses in solder joint, but stress will not go down further from / C to6 1 6 / C. These results show that there might be an optimal point for both CTE and modulus of the epoxy to achieve the maximum benefit of solder joint reliability improvement. By optimizing epoxy material properties, copper post WLP reliability can be further enhanced. Furthermore, it has been found that in a copper post WLP structure, the effect of the copper post/epoxy layer is more prominent than the redistribution layer on solder joint stress reduction. Without the presence of the redistribution layer in a copper post WLP structure, the per-cycle inelastic strain energy density has a slightly increase, as shown in Table 4.

8 X.J. Fan et al. / Microelectronics Reliability 5 (21) ity erg gy Den nsi Ene Pa) n E MP rai (M Str tic In nela ast ty ner rgy yd Den nsit a) ain E (M MPa c Stra Ine ela asti Effect of fan-out WLP structure Modulus of Epoxy (GPa) Fig. 17. Effect of epoxy modulus in WLP Structure D (CTE = 2 ppm/ C) Coefficient i of Thermal Expansion (ppm/ C) Fig. 18. Effect of epoxy CTE in WLP Structure D (E = 14 GPa). Table 4 Effect of RDL layer in a copper post WLP package. Copper post WLP configuration Copper post WLP without RDL 1. Copper post WLP with RDL.96 DW DW In Fig. 19, the per-cycle inelastic energy density is plotted against the location of solder balls in a diagonal direction for a array fan-out WLP package, in which 6 6 array solder balls are under die-area. Fig. 19 shows that outermost ball right beneath silicon die has the maximum inelastic energy density among all balls. This is because the maximum local CTE mismatch is between silicon chip and the PCB. Thus the thermal stresses of solder balls beneath the chip are expected to be higher than the stresses on the outermost solder balls. The results show that fan-out WLP packages can extend the array size greatly while meeting thermo-mechanical reliability requirement. 6. Reliability enhancement by ball geometry and material optimization Thermo-mechanical reliability of solder joints in WLP packages can also be improved by optimizing ball geometry and selecting appropriate material properties. Previous works have demonstrated that hourglass-shape solder joint has the best reliability performance during thermal cycling compared to column, barrel, and spherical-shaped joints. Another factor is the standoff height of the solder joint [18,19]. Solder joints with greater standoff height offer better reliability performance. In the following the effects of solder joint opening diameter, solder ball diameter (volume), and polymer-cored ball implementation are discussed Effect of solder ball opening diameter When solder balls become the weakest link during thermal cycling, failures often take place at solder bulk near solder ball/package interface. It becomes obvious that increasing the contact area, the solder ball opening diameter, is the most direct way to improve the solder joint reliability. In Table 5, the per-cycle inelastic strain energy density is shown for various solder ball opening diameters. A larger diameter increases the total contact/interface area, and therefore it takes a longer time for solder ball crack propagations throughout contact interface. It is noted that such a conclusion is reached with a fixed ball diameter assumption. It will be shown next that increasing solder ball diameter will reduce the thermomechanical reliability Effect of solder ball volume (solder ball diameter) When the solder ball opening size is fixed, the optimization of solder ball shape and volume has a great impact on solder joint reliability. Fig. 2 shows three scenarios of solder ball shapes. The larger solder ball diameter means more solder volume, which intuitively may provide stronger support for solder ball against fatigue failures. Finite element analysis has been performed on those three scenarios and the results of per-cycle inelastic strain energy density are tabulated in Table 6. It shows that the convex shape solder ball (more solder volume with a larger diameter) will result in the worst solder joint reliability performance. It seems that contradicting results are obtained for solder ball opening diameter versus solder ball volume (solder ball diameter). These two results reveal the fundamental failure mechanism for solder ball fatigue failures. When solder volume is reduced, WLP structures become more flexible to move during thermal cycling. This will results less stresses developed at the neck area (package/silicon interface). Although less solder volume induces a greater stress in the middle portion of solder balls, the stress level at Table 5 Effect of solder ball opening diameter. Solder ball opening diameter (lm) DW/DW Fig. 19. Normalized inelastic strain energy density for a fan-out WLP package (die-size 3 3 mm with.5 mm pitch)

9 544 X.J. Fan et al. / Microelectronics Reliability 5 (21) Effect of plastic cored solder balls Fig. 2. Three scenarios of solder ball shapes with the fixed solder ball opening size and ball height. Table 6 Effect of solder ball volume (diameter). Legs Solder ball diameter (lm) DW/DW Leg Leg Leg A plastic core solder ball consists of a large polymer core coated by a copper layer and covered with eutectic and/or lead-free solder. The main advantages of such a system are higher reliability due to the relaxing of stress by the polymer core and a defined ball height after reflow [13 15]. These balls could improve the solder ball reliability significantly due to the compliant feature of balls. Fig. 21 is a schematic of horizontal view of polymer core ball. Fig. 22 shows the photos of the plastic core solder balls. Table 7 shows the comparison of Young s modulus of polymer core material and SnPb. It can be seen that polymer core material has only 1/ 1th of the modulus of SnPb, which will make the structure more flexible when subjected to temperature cycling. Fig. 23 is the Weibull plot of temperature cycling results for the comparison of polymer-cored ball and conventional solder balls [14]. It clearly indicates that the plastic core solder ball structures improve the fatigue life significantly. The Young s modulus of plastic core is much smaller than that of metal, so it is superior in relaxing the thermal stress and enables much greater resistance to micro-cracks in the solder layer than that of conventional solder balls. 7. Other considerations for solder ball reliability enhancement in WLPs 7.1. Implementation of dummy solder balls Fig. 21. Cross-section structure of polymer core ball. neck area is reduced. Therefore, hourglass-shape solder joint shows the best reliability performance. On the other hands, When solder volume is fixed, local enhancement at the neck area can improve reliability performance greatly, such as the increase of solder ball opening diameter. It has been well understood that the outermost corner solder balls in diagonal directions are subjected to the maximum inelastic deformation during thermal cycling, and therefore, fail first. For large array WLP packages, making corner balls non-electrically connected can improve package thermo-mechanical reliability. Two daisy chain loops were designed, as shown in Fig. 24 [3]. Corner daisy chain loops include only eight corner balls, while center daisy chain loop connects all other balls. A comparison of failure data under thermal cycling for corner and non-corner balls are shown in Table 8 [3]. It is observed that the non-corner balls have 4% longer fatigue life than corner daisy chain loop. In other words, making the corner balls non-electrically connected will improve the fatigue life dramatically by 4%. Fig. 25 plots the per-cycle normalized inelastic strain energy density map for all solder balls in a array WLP package. The inelastic strain energy density Fig. 22. Real images of plastic core solder balls on WLP [14].

10 X.J. Fan et al. / Microelectronics Reliability 5 (21) Table 7 Material properties for polymer core material and SnPb solder. Young s modulus (GPa) Poisson s ratio CTE (ppm/ C) 2 C 15 C 2 C 15 C Plastic core material Solder (Sn/Pb) Substrate Board %] res [% lur Fail Sn37Pb Sn Ag Sn-3.5Ag-.7Cu Polymer w/ SnPb Fatigue Life [cycles] Fig. 23. Weibull plot of the performance of polymer core balls compared to the conventional solder balls [14]. Fig. 25. Normalized inelastic strain energy density per cycle for a one eighth part of a array WLP package. sity ens rgy D ner a) En Pa tra ain (M elas stic St Ine I Coefficient of Thermal Expansion (ppm/ C) Fig. 26. Effect of PCB CTE on solder joint reliability. Fig. 24. Two daisy chain loops design. Table 8 Normalized characteristic fatigue life for failures of corner and non-corner balls [3]. Solder ball groups Corner group Non-corner group Normalized characteristic life PCB CTEs. When low CTE PCB core material is used, the fatigue life can be increased greatly. It has been demonstrated that a polymer film layer between solder balls and silicon with a larger CTE can increase the overall effective CTE of silicon assembly, and thus reduce the thermal stresses in solder joints. Similar concept can be developed at PCB side to include a layer of material between PCB and solder balls. The detailed studies will be reported separately. decays rapidly both along die edge and diagonal direction towards package center. This agrees very well with the test results Effect of PCB Thermal mechanical stresses developed in solder joints are induced by the thermal mismatch between PCB and silicon. Lowering the CTE of PCB can also reduce the stresses in solder joints. Fig. 26 shows the results of inelastic strain energy density for three sets of 8. Concluding remarks Four types of fan-in WLP structures are studied first to investigate the effect of WLP structures on solder joint reliability. These four WLP structures are: standard WLP (bump on I/O), bump on polymer WLP without UBM layer, bump on polymer WLP with UBM layer, and encapsulated copper post WLP. Finite element modeling results for these WLP structures show that ball on polymer WLP, and copper post WLP have a greater improvement

11 546 X.J. Fan et al. / Microelectronics Reliability 5 (21) in thermo-mechanical reliability performance over the bump on I/ O WLPs. In a ball on polymer WLP structure, polymer film between silicon and solder balls creates a cushion effect to reduce the stresses in solder joints. Such cushion effect can be achieved either by an extremely compliant film or a hard film with large coefficient of thermal expansion. In the later case, the reduction of solder joint stresses is due to the overall increase of the combined film/ wafer effective CTE. It has been found that a hard layer with a large CTE can reduce solder joint stress beyond a compliant film. This has been validated by an encapsulated copper post WLP structure, which shows the best performance on all four structures in terms of solder joint reliability, experimentally and numerically. Fan-out WLPs are structurally similar to BGA packages. Therefore, the critical solder balls are not on the outermost corners along package diagonal directions. The outermost solder balls under diearea are most critical since the maximum thermal mismatch takes place at die-shadow location. For fan-out WLP packages, chip size, other than package size, determines the limit of solder joint reliability. Ball geometry and materials play important roles in enhancing solder joint reliability. The more compliant solder ball is, the greater thermo-mechanical reliability is achieved. Therefore, reducing individual solder ball volume or using more compliant materials such as polymer-cored solder balls will improve reliability performance. On the other hands, since failures are often at solder bulk near package/solder interface region, local enhancement methods, such as the increase of solder ball opening diameter, will be beneficial in reliability performance. Solder balls often start to crack at the corner locations along package diagonal directions. Both experimental and finite element analysis have demonstrated that making corner balls non-electrically connected can improve the WLP thermo-mechanical reliability significantly. References [1] Fan XJ, Liu Y. Design, reliability and electromigration in chip scale wafer level packaging. ECTC professional development short course notes; 29. [2] Fan XJ, Han Q. Design and reliability in wafer level packaging. In: Proc of IEEE 1th electronics packaging technology conference (EPTC); 28. p [3] Rahim MSK, Zhou T, Fan XJ, Rupp G. Board level temperature cycling study of large array wafer level packages. In: Proc of electronic components and technology conference (59th ECTC); 29. p [4] Reche JHJ, Kim DH. Wafer level packaging having bump-on-polymer structure. Microelectron Reliab 23;43: [5] Varia B, Fan XJ, Han Q. Effects of design, structure and material on thermal mechanical reliability of large array wafer level packages. Beijing: ICEPT-HDP; 29. [6] Kim D-H, Elenius P, Johnson M, Barrett S. Solder joint reliability of a polymer reinforced wafer level package. Microelectron Reliab 22;42:1837. [7] Bumping design guide. < [8] Kawahara T. SuperCSPs. IEEE Trans Adv Packag 22;23(2):22. [9] Gao G, Haba B, Organesian V, Honer H, Ovrutsky D, Rosenstein C, et al. Compliant WLP for enhanced reliability. In: International wafer level package conference, San Jose (CA); September [1] Meyer-Berg G. Wafer-level ball grid array packaging technology trends. In: 9th IEEE international conference on thermal and mechanical simulation and experiments in microelectronics and microsystems (EuroSimE); April [11] Keser B, Amrine C, Duong T, Hayes S, Leal G, Lytle M, et al. Advanced packaging: the redistributed chip package. IEEE Trans Adv Packag 28;31(1). [12] Lee CC, Liu HC, Chiang KN. 3-D structure design and reliability analysis of wafer level package with stress buffer mechanism. IEEE Trans Compon Packag Technol 27;3(1):11 8. [13] Wang YP, Hung LY. High drop performance interconnection: polymer cored solder ball. ECTC 28. [14] Eagelmaier W. Achieving solder joint reliability in a lead-free world part 2. Global SMT & packaging, vol. 7; 27. p < documents/columns-engelmaier/7.7_engelmaier.pdf>. [15] Okinaga N, Kuroda H, Nagai Y. Excellent reliability of solder ball made of a compliant plasticcore. Electron Compon Technol Conf 21: [16] Keser B, Yeung B, White J, Fang T. Encapsulated double-bump WL-CSP: design and reliability. ECTC 21:35 9. [17] Mitsuka K, Kurata H, Jun Furukawa, Takahashi M. Wafer process chip scale package consisting of double-bump structure for small-pin-count packages. ECTC 25: [18] Liu X, Lu GQ. Effects of solder joint shape and height on thermal fatigue lifetime. IEEE Trans Compon Packag Technol 23;26(2): [19] Lim SS, Rajoo R, Wong EH. Reliability performance of stretch solder interconnections. In: Proc IEMT; 26. [2] Tee TY, Tan LB, Anderson R, Ng HS, Low JH, Khoo CP, et al. Advanced analysis of WLCSP copper interconnect reliability under board level drop test. In: 1th EPTC conference proc.; 28. p [21] Fan XJ, Zhou J, Zhang GQ. Multi-physics modeling in virtual prototyping of electronic packages combined thermal, thermo-mechanical and vapor pressure modeling. J Microelectron Reliab 24;44: [22] Anand L. Constitutive equations for hot working of metals. J Plast 1985;1: [23] Reinikainen TO, Marjamäki P, Kivilahti JK. Deformation characteristics and microstructural evolution of SnAgCu solder joints. EuroSimE; 25. [24] Fan XJ, Pei M, Bhatti PK. Effect of finite element modeling techniques on solder joint fatigue life prediction of flip-chip BGA packages. In: Proc of IEEE electronic components and technology conference (ECTC), San Diego (CA); May 3 June [25] Darveaux R. Solder joint fatigue life model. In: Proceedings of the TMS annual meeting; p [26] Syed A. Predicting solder joint reliability for thermal, power, & bend cycle within 25% accuracy. In: 51st ECTC; 21. p [27] Pei M, Fan XJ, Bhatti PK. Field condition reliability assessment for SnPb and SnAgCu solder joints in power cycling including mini cycles. In: Proc of electronic components and technology conference (ECTC); 26. p [28] Bhatti PK, Pei M, Fan XJ. Reliability analysis of SnPb and SnAgCu solder joints in FC-BGA packages with thermal enabling preload. In: Proc of electronic components and technology conference (ECTC); 26. p [29] Fan XJ, Rasier G, Vasudevan VS. Effects of dwell time and ramp rate on leadfree solder joints in FCBGA packages. In: Proc of electronic components and technology conference (ECTC); 25. p [3] Vasudevan V, Fan X, Liu T, Young D. Slow cycle fatigue creep performance of Pb-Free (LF) solders. In: Proc of electronic components and technology conference (ECTC); 27. p [31] Fan XJ, Wang HB, Lim TB. Investigation of the underfill delamination and cracking for flip chip module during thermal cyclic loading. IEEE Trans Compon Manufact Packag Technol 21;24(1):84 91.

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