Lecture 5. SOI Micromachining. SOI MUMPs. SOI Micromachining. Silicon-on-Insulator Microstructures. Agenda:
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1 EEL6935 Advanced MEMS (Spring 2005) Instructor: Dr. Huikai Xie SOI Micromachining Agenda: SOI Micromachining SOI MUMPs Multi-level structures Lecture 5 Silicon-on-Insulator Microstructures Single-crystal silicon Flatness (optical MEMS) Robustness High-Q High-power capacity Good temperature stability High resolution, low noise (Inertial sensors) Thickness control SOI CMOS compatibility A big trend for optical MEMS and inertial sensors EEL6935 Advanced MEMS 2005 H. Xie 1/19/ EEL6935 Advanced MEMS 2005 H. Xie 2 SOI MUMPs process Silicon as structural layer Silicon as structural and sacrificial material Two-level beam structures Multilevel beam structures Buckled beam structures Many others SOI Micromachining SOI MUMPs Features: Silicon-on-insulator (SOI) wafer as the starting substrate: Silicon thickness: 10 ± 1 µm or 25 ± 1 µm Oxide thickness: 1 ± 0.05 µm Handle wafer (Substrate) thickness: 400 ± 5 µm Silicon layer is doped and can be used for mechanical structures, resistor structures, and/or electrical routing. Backside Substrate etch allows for through-hole structures. Shadow-masked metal process for coarse Metal features such as bond pads, electrical routing, and optical mirror surfaces. A second pad-metal feature that allows finer metal features and precision alignment but limited to areas not etched in the silicon device layer. EEL6935 Advanced MEMS 2005 H. Xie 1/12/ EEL6935 Advanced MEMS 2005 H. Xie 4
2 SOI MUMPs Process Flow (1) SOI MUMPs Process Flow (2) Silicon layer: 10um Oxide layer: 1um Substrate: 400um Bottom oxide present Starting Substrate SOI Wafer First mask (PAD METAL) 20nm Cr/500nm gold (E-beam evaporation) Metal Liftoff PSG deposition Annealing: 1050 C, 1 hour Remove PSG Silicon Doping Photoresist as mask DRIE Silicon Patterning EEL6935 Advanced MEMS 2005 H. Xie 5 EEL6935 Advanced MEMS 2005 H. Xie 6 SOI MUMPs Process Flow (3) SOI MUMPs Process Flow (4) Protection material applied to front side Pattern backside oxide DRIE silicon from back side, stopping on the middle oxide Remove photoresist Wet etch oxide (both middle layer and backside layer) Substrate Patterning Release Separate silicon wafer DRIE silicon Shadow Mask Shadow Mask Bonding and Metal Deposition Dry etch protection material Vapor HF etch oxide Expose silicon layer and substrate for electrical contacts Temporarily bond the shadow mask Metal deposition: 50nm Cr /600nm Au EEL6935 Advanced MEMS 2005 H. Xie 7 EEL6935 Advanced MEMS 2005 H. Xie 8
3 SOI MUMPs Process Flow (5) SOI MUMPs Example Remove the shadow mask Shadow Mask Removal In-Plane Vibrating Diffraction Grating Scanning an optical angle of 15.9 at a resonant frequency of 8.34 khz for a 635-nm wavelength incident laser beam, electrostatically driven by 15-V dc bias and 15-Vac voltages EEL6935 Advanced MEMS 2005 H. Xie 9 G. Zhou et al, IEEE Photonics Technology Letters, Vol.16, no. 10, (2004) EEL6935 Advanced MEMS 2005 H. Xie 10 SOI MEMS Processes -2 SOI MEMS Processes -3 Backside Etch Angular Comb Drive Actuator Frontside HF Release SOI wafer DRIE Si etch LPCVD Si3N4 Light-weight SOI MEMS Mirror LPCVD poly-si Oxidize poly-si CMP LPCVD poly-si Si DRIE RTA 750~900 C to form tensile stress HF release Supercritical drying Patterson et al, OFC 2002 EEL6935 Advanced MEMS 2005 H. Xie 11 J.T. Nee et al, MEMS 2000 EEL6935 Advanced MEMS 2005 H. Xie 12
4 Multilevel Beam Microstructures Multilevel Beam Fabrication Process (1) Torsional Mirror Concept SOI wafer DRIE Si etch LPCVD Si3N4 Vertical Comb- Drive Mirror V. Milanovic, JMEMS, vol.13 (2004) EEL6935 Advanced MEMS 2005 H. Xie 13 EEL6935 Advanced MEMS 2005 H. Xie 14 (e) (f) (g) Multilevel Beam Fabrication Process (2) SOI wafer DRIE Si etch LPCVD Si3N4 SOI substrate Two-side alignment DRIE silicon on both sides Timed DRIE Si Thickness variations of Upper beams and Lower beams EEL6935 Advanced MEMS 2005 H. Xie 15 Torsional Micromirrors Multilevel Beam Fabrication Process (3) Flat Lightweight High speed Low power Electrostatic actuation V. Milanovic, JMEMS, vol.13 (2004) EEL6935 Advanced MEMS 2005 H. Xie 16
5 SOI MEMS Processes -5 SOI MEMS Processes -6 Vertical Comb Drive SOI Epitaxial MEMS Micromirror Vertically buckled bridge Wet etch SiO2 Poly-Si as HF etching mask Sasaki et al, JMEMS, vol.13 (2004) EEL6935 Advanced MEMS 2005 H. Xie 17 Epitaxial Si/SiGe/Si multilayer structures Vertical symmetry for flat surface Vertical asymmetry for bending Size: 0.1mm by 0.27mm Maximum rotation (static): 10 Tokuda et al, Electronics Letters, vol.40 (2004), no.21 EEL6935 Advanced MEMS 2005 H. Xie 18
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