EE 247B/ME 218: Introduction to MEMS Design Lecture 25m2: Sensing Circuit Non-Idealities & Integration CTN 4/21/16

Transcription

1 EE 247B/ME 218: Introduction to MEM esign Actual Op Amps Are Not Ideal Actual op amps, of course, are not ideal; rather, they enerate noise Have finite gain, A o Have finite bandwidth, b Have finite input resistance, R i Have finite input capacitance, C i Have finite output resistance, R o Have an offset voltage V O between their (+) and (-) terminals Have input bias currents Have an offset I O between the bias currents into the (+) and (-) terminals Have finite slew rate Have finite output swing (governed by the supply voltage used, -L to +L) And what s worse: All of the above can be temperature (or otherwise environmentally) dependent! 10 Finite Op Amp ain and Bandwidth For an ideal op amp: A In reality, the gain is given by: A For >> b : A0 A0 b T A( s) s b s s A j log 20 A 0 b s A0 s 1 This pole actually designed in for some op amps. 3 db frequency Open-loop response of the amplifier. 11 T b Integrator w/ time const. 1/ T 20dB/dec Unity gain frequency: Finite ain Finite Bandwidth T A0 b Effect of Finite Op Amp ain +V P Total AXL-50 ense C ~ 100fF C p C gd + - Unity ain Buffer v 0 Integration of MEM and Transistors -V P

2 EE 247B/ME 218: Introduction to MEM esign Integrate or Not? 250 nm CMO Cross-ection Benefits: Lower parasitic capacitance and resistance improved sensitivity and resolution, higher operation frequency Better reliability Reduced size lower cost? Reduced packaging complexity integration is a form of packaging lower cost? Higher integration density supports greater functionality Challenges: Temperature ceilings imposed by the transistors or MEM Protecting one process from the other urface topography of MEM Material incompatibilities Multiplication of yield losses (versus non-integrated) Acceptance by transistor foundries ub 2nd Level Metal Interconnect (e.g., Cu) 14 Merged MEM/Transistor Technologies (Process Philosophy) 1st Level Metal Interconnect (e.g., Al) LPCV io2 Polysilicon ate CV Tungsten P+ LOCO Oxidation N N+ P+ N Well - PMO ubstrate N+ P P Well - NMO ubstrate Tii2 Contact Barrier ilicon ubstrate ub P TiN Local Interconnect Lightly oped rain (L) masks masks and and aa lot lot more more complicated complicated than than MEM! MEM! 15 Analog evices BiMEM Process Interleaved MEM and 4 m BiMO processes (28 masks) iffused n+ runners used to interconnect MEM & CMO Relatively deep junctions allow for MEM poly stress anneal Used to manufacture the AXL-50 accelerometer and MEM-Last: Analog evices family of accelerometers MEM-First: Mixed: problem: multiple passivation/protection steps large number of masks required problem: custom process for each product MEM-first or MEM-last: adv.: modularity flexibility less development time adv.: low pass./protection complexity fewer masks

3 EE 247B/ME 218: Introduction to MEM esign Merged MEM/Transistor Technologies (Process Philosophy) Analog evices BiMEM Process (cont) Examples: Old New Mixed: problem: multiple passivation/protection steps large number of masks required problem: custom process for each product Analog evices AXL-202 Multi-Axis Accelerometer Analog evices AXL 78 MEM-first or MEM-last: adv.: modularity flexibility less development time adv.: low pass./protection complexity fewer masks Can you list the advances in the process from old to new? 18 MEM-First Integration 19 Problem: structural topography interferes with lithography Module 1: micromachining process (planar technology) Module 2: transistor process (planar IC technology) Adv.: (ideally) no changes needed to the transistor process Adv.: high temperature ceiling for some MEM materials Challenges: Reducing topography after MEM processing so transistors can be processed Maximizing the set of permissible MEM materials; the materials must be able to withstand transistor processing temperatures etting transistor foundries to accept pre-processed wafers MEM-First Integration Modular technology minimizes product updating effort difficult to apply photoresist for submicron circuits oln.: build mechanics in a trench, then planarize before circuit processing [mith et al, IEM 95]

4 EE 247B/ME 218: Introduction to MEM esign MEM-First Ex: andia s imem Used to demonstrate functional fully integrated oscillators Issues: lithography and etching may be difficult in trench may limit dimensions (not good for RF MEM) mechanical material must stand up to IC temperatures (>1000 o C) problem for some metal materials might be contamination issues for foundry IC s [mith et al, IEM 95] Bosch/tanford MEM-First Process ingle-crystal silicon microstructures sealed under epi-poly encapsulation covers Many masking steps needed, but very stable structures Epi-Poly eal Resonator Epi-Poly Cap ubstrate Contact Epi-silicon for CMO Transistor Circuits Vacuum Chamber [Kim, Kenny Trans 05] Mechanical evice Problems With MEM-First Many masking steps needed, plus CMP required cost can grow if you re not careful Processes using trenches sacrifice lithographic resolution in microstructures MEM must withstand transistor processing temperatures Precludes the use of structural materials with low temperature req mts: metals, polymers, etc. Exotic MEM (e.g., ZnO) that can contaminate transistors during their processing are not permissible thus, not truly modular Foundry acceptance not guaranteed and might be rare Foundry Acceptance of MEM-First? Is a CMP ed silicon surface sufficiently pure for fabrication of aggressively scaled transistors? How about if an oxide is grown over the CMP ed surface and removed via a wet etch to yield a pristine surface? Is epi silicon grown as part of a sealing process sufficiently pure for fabrication of aggressively scaled transistors? CMO is many times more difficult to run than MEM Feature sizes on the nm scale for billions of devices Contamination a big issue: many foundries may not accept pre-processed wafers for contamination reasons Many foundries will not accept any pre-processed wafers, MEM or not just can t guarantee working transistor circuits with unknowns in starting silicon

5 EE 247B/ME 218: Introduction to MEM esign Merged MEM/Transistor Technologies (Process Philosophy) Mixed: problem: multiple passivation/protection steps large number of masks required problem: custom process for each product MEM-first or MEM-last: adv.: modularity flexibility less development time adv.: low pass./protection complexity fewer masks 26 MEM-Last Integration Modular technology minimizes product updating effort Module 1: transistor process (planar IC technology) Module 2: micromachining process (planar technology) Adv.: foundry friendly Virtually any foundry can be used can use the lowest cost transistor circuits (big advantage) Adv.: topography after circuit fabrication is quite small, especially given the use of CMP to planarize the metallization layers Issue: limited thermal budget limits the set of usable structural materials Metallization goes bad if temperature gets too high Aluminum grows hillocks and spikes junctions if T>500 o C Copper diffusion can be an issue at high temperature Low-k dielectrics used around metals may soon lower the temperature ceiling to only 320 o C 27 Berkeley Polysilicon MIC Process urface Micromachining Uses surface-micromachinedpolysilicon microstructures with silicon nitride layer between transistors & MEM Polysilicon dep. T~600 o C; nitride dep. T~835 o C 1100 o C RTA stress anneal for 1 min. metal and junctions must withstand temperatures ~835 o C tungsten metallization used with Tii 2 contact barriers in situ doped structural polyi; rapid thermal annealing 28 Fabrication steps compatible with planar IC processing 29 5

6 EE 247B/ME 218: Introduction to MEM esign ingle-chip Ckt/MEM Integration Usable MEM-Last Integration Completely monolithic, low phase noise, high-q oscillator Problem: tungsten is not an accepted primary interconnect (effectively, an integrated crystal oscillator) metal Challenge: retain conventional metallization minimize post-cmo processing temperatures explore alternative structural materials (e.g., plated nickel, ie [Franke, Howe et al, MEM 99]) Limited set of usable structural materials not the best situation, but workable Oscilloscope Output Waveform [Nguyen, Howe [Nguyen, Howe1993] 1993] To allow the use of >600oC processing temperatures, tungsten (instead of aluminum) is used for metallization 30 Poly-ie MIC Process Poly-ie MEM hielded vertical signal path to gate of input transistor [Franke, Howe 2001] eposition processed directly above conventional foundry circuits enabled by lower deposition temperature of ie ~450oC Adv.: alleviates contamination issues of pre-circuit processes, allowing a wider choice of IC technologies 5-Level Metal Foundry CMO Polysilicon ermanium MIC = Modular Integration of Circuits and tructures MEM-last process, where ie micromechanics are planar hielded Interconnect to drive electrode 32 LPCV thermal decomposition of eh4 and ih4 or i2h6 Rate >50 Å/min, T < 475 C, P = mt At higher [e]: rate, T In-situ doping, ion implantation ry Etching imilar to poly-i, use F, Cl, and Br- containing plasmas Rate ~0.4 m/min Wet Etching o 90 C: can get 4 orders of magnitude selectivity between >80% and <60% e content ood release etchant 6

7 EE 247B/ME 218: Introduction to MEM esign Poly-ie Mechanical Properties UCB Poly-ie MIC Process Conformal deposition Low as-deposited stress (when 2 m standard CMO process w/ Al metallization P-type poly-i0.35e0.65 structural material; poly-e Young s modulus ~ 146 Pa (for Process: its done right) sacrificial material Passivate CMO w/ 400oC Open vias to interconnect runners eposit & pattern ground plane RTA anneal to lower resistivity (550oC, 30s) poly-i0.35e0.65) ensity ~4280 kg/m3 Acoustic velocity ~5840 m/s (25% lower than polysilicon) Harder to achieve high frequency devices Fracture strain 1.7% (compared to 1.5% for MUMP polyi) Q=30,000 for n-type poly-e in vacuum 34 AIMP Ckt/MEM Integration Process MEM constructed from metal/insulator laminates of foundry CMO Top metal layer used as etch mask for CHF3/O2 oxide etch tructures released via a final F6 isotropic dry etch Independent electrostatic actuation possible due to multiple insulated metal layers tress issues can be tricky Must design defensively against warping 35 AIMP Ckt/MEM Integration Process irect integration of Al/oxide MEM structure with silicon CMO or ie BiCMO circuits Multiple electrodes within structures erivatives for bulk silicon structures Composite Beam Etched Pit yro Resonator CMO Transistor Metal/insulator stack ilicon ubstrate [. Fedder, CMU] Transistor Circuits tator Electrodes [. Fedder, CMU] 36 Uncooled IR etector Element 37 7