Microelectronics Reliability

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Microelectronics Reliability 52 (2012) 2215 2219 Contents lists available at SciVerse ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.

Electronic Engineering, Yonsei University, Seoul 120-749, Republic of Korea article info abstract Article history: Received 29 May 2012 Received in revised form 27 June 2012 Accepted 3 July 2012

1 Microelectronics Reliability 52 (2012) Contents lists available at SciVerse ScienceDirect Microelectronics Reliability journal homepage: Threshold voltage shift prediction for gate bias stress on amorphous InGaZnO thin film transistors Suehye Park 1, Edward Namkyu Cho 1, Ilgu Yun Department of Electrical and Electronic Engineering, Yonsei University, Seoul , Republic of Korea article info abstract Article history: Received 29 May 2012 Received in revised form 27 June 2012 Accepted 3 July 2012 Available online 31 July 2012 The demand for amorphous InGaZnO (a-igzo) thin film transistors (TFTs) has increased due to the high mobility and suitability for low temperature fabrication. A prediction of the threshold voltage shift (DV th ) under bias stress is required for the commercial use of a-igzo TFTs. We have investigated effects of the channel length and alternating pulse bias (positive and negative gate bias stress in sequence) with different positive gate bias values (V GS+ )ondv th. We found that DV th increases as the channel length decreases or V GS+ increases, due to the increase in the charge trapping rate. Finally, the degradation behaviors of a-igzo TFTs are predicted. Ó 2012 Elsevier Ltd. All rights reserved. 1. Introduction Amorphous InGaZnO (a-igzo) thin film transistors (TFTs) are very attractive and have been developed to meet a large market demand due to the suitability of low temperature fabrication and usage in transparent electronic applications [1,2]. Moreover, a- IGZO TFTs have good electrical performance including high mobility (>10 cm 2 /V) and a large drain current on off ratio (>10 7 ) [1,2]. However, like other TFTs, the characteristic variations of a-igzo TFTs, such as the threshold voltage (V th ) variation, occur due to bias stress. The variations of the electrical characteristics limit the application of a-igzo TFTs in display applications such as active matrix organic light emitting diodes (AMOLEDs), resulting in non-uniform pixel brightness [3]. Several papers have reported on the electrical instability of a-igzo TFTs, but they focused on gate bias stress (V GS ) instability without varying the channel dimension [3 5]. An investigation of the channel length (L) effect on the bias stress instability of a-igzo TFTs has not yet been performed. Secondly, to understand the role of the TFT as a switch, an investigation on the effects of both positive gate bias (V GS+ ) and negative gate bias (V GS ) is required. Previous studies have focused on how the V GS+ and V GS stresses can independently induce the degradation of TFTs [6,7]. The impact of the AC V GS on instability has already been studied [8,9], whereas the DC alternating pulse gate stress has hardly been investigated. Furthermore, the issue of the variation of V GS+ not using the AC bias has not yet been analyzed. In this paper, we performed two types of bias stress tests to investigate the variations of the threshold voltage (DV th ): (1) Influence of the channel length (L) on the electrical instability of Corresponding author. Tel.: ; fax: address: iyun@yonsei.ac.kr (I. Yun). 1 These authors contributed equally to this work. a-igzo TFTs and (2) Influence of V GS+ in alternating pulse biases for the same total stress time (T stress ). The transfer characteristics (I DS V GS ) are measured to investigate the electrical stability including the DV th and subthreshold swing (S SUB ). 2. Test structure description a-igzo TFTs were fabricated as a conventional staggered bottom gate structure, as shown in Fig. 1 [10,11]. The tested TFT structures were fabricated on a glass substrate with a 250-nm thick Mo gate deposited by sputtering. The 200-nm thick SiN X gate insulator was deposited on the Mo gate by plasma enhanced chemical vapor deposition (PECVD). The 40-nm thick a-igzo channel was deposited by sputtering using a polycrystalline In 2 Ga 2 ZnO 7 target. The source and drain electrodes were then deposited via sputtering with a Mo target. The tested structures were passivated by a SiO X layer. The TFTs showed no degradation even though they were exposed to air. For that reason, we did not consider that any trapping states or contaminants existed in the environment atmosphere during device manufacturing. 3. Stress test conditions and experiments Two types of bias stress tests were performed with two samples: (1) V GS+ stress with various values of L and (2) alternating pulse bias stress. A detailed description of the each stress test is shown below: (1) The TFTs with the same channel width (W) of 200 lm but different L values of 100, 50, 15, and 10 lm were used to verify the effects of L on the electrical bias stress instability. The V GS+ was stressed at 20 V for 60 min with grounded drain and source electrodes. (2) The TFTs with W =50lm and L =50lm were used to analyze the effect of alternating pulse bias stress /$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved.

2216 S. Park et al. / Microelectronics Reliability 52 (2012) 2215 2219 DV th ¼ V th;time V th;initial ð1þ where V th, time is the V th value at the measured time and V th, initial is the initial V th.

2 2216 S. Park et al. / Microelectronics Reliability 52 (2012) DV th ¼ V th;time V th;initial ð1þ where V th, time is the V th value at the measured time and V th, initial is the initial V th. One of the electrical characteristics, S SUB, was also determined by: dv GS S SUB ¼ dðlog I DS Þ ð2þ 4. Results and discussions 4.1. V GS+ stress at various channel lengths Fig. 1. Schematic of the tested a-igzo TFT structure. The total T stress was 80 min, where the positive and negative T stress were 40 min each; and these times were the same for all four stress conditions shown in Fig. 6. Both V GS+ and V GS stresses were applied to the TFTs alternately with a 10 min-interval stress time [12]. Four levels of V GS+ bias were tested: 20, 15, 10, and 5 V. The transfer characteristics were measured during the stress tests using a Keithley 236 source measure unit (SMU) at room temperature. The elapsed time between the former measurement and the latter was about 3 s. As a pre-screening, we measured the transfer characteristics for nine times in sequence without stressing the devices and found that measurement data were identical. Therefore, the V GS sweep from 10 V to 20 V did not show any degradation. V th was calculated by adjusting V GS when I DS of L/ W 10 na. DV th was defined as: The V GS+ stress instability is analyzed with L variation. Fig. 2a d shows the transfer characteristics before and after the V GS+ stresses when the L values are 100, 50, 15, and 10 lm, respectively. The transfer characteristic for each L is shifted in the positive direction as the gate bias stress time increases with no apparent change in S SUB indicating carrier trapping in the channel/gate dielectric interface and/or channel with no creation of additional defect states [13,14]. Interestingly, as shown in Fig. 2, DV th shows an incremental tendency as L decreases. For example, the DV th values at 3600 s are 1.68, 1.76, 2.31, and 2.86 V when the L values are 100, 50, 15, and 10 lm, respectively. We think that this tendency originates from the different initial characteristics of the tested TFTs. From the initial transfer characteristics, S SUB degrades as the channel length decreases which is consistent with previously reported researches [15,16]. To investigate how the TFTs suffer from V GS+ stress as L varies, we performed a 2-D ATLAS device simulation produced by Silvaco, Inc. [17]. In our previous research, we reported the subgap density of states (DOS) modeling of a-igzo TFTs Fig. 2. Transfer characteristics for V GS+ (=20 V) when L are (a) 100, (b) 50, (c) 15, and (d) 10 lm, respectively.

S. Park et al. / Microelectronics Reliability 52 (2012) 2215 2219 2217 Fig. 3.

3 S. Park et al. / Microelectronics Reliability 52 (2012) Fig. 3. (a) Optimized subgap DOS, (b) channel electric field, schematic figure of electric field simulation for L of, (c) 10 and (d) 100 lm. Table 1 Parameter values for stretched-exponential function. L (lm) DV th0 (V) s (s) b Table 2 Parameter values for fitting exponential function. 600 s 1200 s 1800 s 2400 s 3000 s 3600 s DV th A L B Fig. 4. The DV th versus T stress with different L: measured (scatters) and stretchedexponential fitting (lines) with fixed b. [5,18]. The initial transfer characteristics for L of 100 and 10 lm are modeled with subgap DOS parameters, representatively. Fig. 3a shows the optimized subgap DOS for L values of 100 and 10 lm. It is shown that as subgap DOS increases, S SUB degrades. From the optimized model, we applied V GS+ of 20 V in the simulation. Fig. 3b shows the transversal electric field extracted from the middle of the channel for L of 10 and 100 lm while Fig. 3c and d show the schematic figures of the electric field simulation. It is clear from the figures that the channel for 10 lm exhibits a higher electric field than the channel for 100 lm, even when the same V GS+ (20 V) is applied to the devices. This result can explain why DV th increases as L decreases, even though the same V GS+ is applied. As the electric field increases, more charges are accumulated, resulting in more charges being trapped due to the increase of the charge trapping rate [3,4].

4 2218 S. Park et al. / Microelectronics Reliability 52 (2012) Table 3 Parameter values for stretched-exponential function. V GS+ (Set) DV th0 (V) s (s) b 20 V for 80 min V (Set a) V (Set b) V (Set c) V (Set d) , and the data of L =50lm is used to verify the model. Table 2 summarizes the fitting parameter values to support Eq. (4). All of the parameter values are quite similar, although T stress varies. Fig. 5 shows DV th with respect to L with measured (scatters) and fitting (lines) data using the parameters listed in Table Alternating pulse bias stress with various V GS+ Fig. 5. Comparison of DV th with respect to L: measured (scatters) and fitting (lines) data. Fig. 6. Alternating DC bias stress conditions. The increase of the charge trapping rate as L decreases can also be verified from a stretched-exponential function model of DV th. The stretched-exponential function is determined as a function of T stress by [13,14]: DV th ¼ DV th0 ½1 expf ðt stress =sg b Š where DV th0 is DV th at infinite time, s is the characteristics trapping time of carriers, and b is the stretched-exponential exponent. Fig. 4 shows the comparison of DV th with respect to L. The scattered points represent the measured DV th, while the straight lines represent the stretched-exponential model for DV th with fixed b (=0.55). It is shown that the stretched-exponential model fits well to the measured DV th, which means that charge trapping occurs in the channel/dielectric interface and/or channel [13,14]. The extracted parameter values, DV th0 and s, are summarized in Table 1. DV th0 increases from 3.64 V to 4.9 V as the channel length decreases. The s value decreases from 9043 s to 4760 s as channel length decreases which is consistent with an increase of the charge trapping rate, because the smaller s causes the faster charge trapping time [19]. As the experimental data is well described by the stretchedexponential function [13,14], we propose a model to predict DV th as a function of L. The proposed empirical model for DV th is determined by: DV th ¼ DV th1 þ A exp L L 0 ð4þ B where DV th1,a,l 0, and B are the fitting parameters to support Eq. (4). To ensure the reliability and reproducibility of Eq. (4), the measured data of L = 100, 15, and 10 lm are used to build the equation ð3þ According to Suresh et al., it is obvious that V GS+ has a larger effect than V GS because the transfer curves shift in the positive direction even though T stress is the same [4]. Therefore, the impact of four-type-v GS+ will be compared. Fig. 6 shows the four sets of stress conditions with V GS+ as 20 (Set a), 15 (Set b), 10 (Set c), and 5 (Set d) V with fixed V GS of 20 V. Although V GS is also applied to the TFTs for a total of 40 min, it is predicted that a higher V GS+ induces a larger DV th based on other studies [4,5]. As the applied V GS+ decreases from 20 V to 5 V, DV th decreases from 1.34 V to 0.3 V. The bias-dependent tendency on DV th can be verified by the carrier trapping parameters extracted from the stretchedexponential function with DV th0, s, and b [13,14]. Unlike the stretched-exponential function used in Section 4.1, V GS+ and V GS are alternately applied to the TFTs. Under V GS+, the carrier trapping time is obtained from Eq. (3). For that reason, cases in which T stress equals 10, 30, 50, and 70 min are considered in order to extract the carrier trapping time. Two parameters, DV th0 and s, are extracted, and their parameter values are summarized in Table 3. To observe the effect of adding V GS bias stress, we compared the DV th0 and s values for +20 V V GS stress (80 min) to Set a. The charges are trapped under V GS+ stress while they are detrapped under V GS stress. DV th values for Set a are smaller than those for +20 V V GS stress (80 min), due to the charge detrapping induced by V GS stress. DV th0 decreases from 2.38 V to 0.58 V as V GS+ decreases. s increases from 3368 s to s as V GS+ decreases from 20 V to 5 V. A smaller s causes a faster charge trapping time; therefore, a large V GS+ induces more charge trapping than a small V GS+, and also induces a larger DV th than the small V GS+ case [20]. Fig. 7 shows the Fig. 7. The DV th versus T stress with different V GS+ when V DS = 2.1 V: measured (scatters) and stretched-exponential fitting (lines) with fixed b (=0.45) data.

5 S. Park et al. / Microelectronics Reliability 52 (2012) shown that DV th increased as the channel length decreased due to the increase of the electric field in the channel layer. For the case of alternating pulse bias stress, DV th increased as V GS+ increased from 5 V to 20 V due to the decrease in the charge trapping time. The degradation behaviors of a-igzo TFTs for the channel length and the alternating pulse bias are verified by the stretched-exponential function and predicted by the empirically proposed model. It was shown that the proposed empirical model was in good agreement with the measured DV th data. Acknowledgement This work was supported by Yonsei University, Institute of TMS Information Technology, a Brain Korea 21 program, Korea. References Fig. 8. Comparison of DV th with respect to V GS+: measured (scatters) and fitting (lines) data. Table 4 Parameter values for fitting exponential function. comparison of DV th with respect to T stress when V DS = 2.1 V, and the inset shows the final DV th (T stress = 80 min) with respect to V GS+ when V DS = 2.1 V. The scattered points represent the measured DV th, while the straight lines represent the stretched-exponential model for DV th with fixed b (=0.45) [21]. According to the previous research [4], it is evident that the higher V GS+ causes V th to shift more in the positive direction but it is also evident that DV th is not a linear function of V GS+. As the degradation behavior of TFTs is well explained by the stretchedexponential function, we propose a model for the amount of DV th as an exponential function of V GS+. The proposed empirical model for DV th is determined by: DV th ¼ DV th2 þ C exp V GSþ V GS0 D where DV th2,c,v GS0, and D are the fitting parameters to support Eq. (5). To ensure the reliability and reproducibility of Eq. (5), the measured data of Set a, b, and d are used to build the equation and we use data Set c to verify the model. Table 4 summarizes the fitting parameter values to support Eq. (5). By using Eq. (5) with the fitting parameters listed in Table 4, the predicted DV th value for Set c when V DS = 2.1 V is predicted to be V, which is very similar to the measured value of 0.32 V. Likewise, the predicted DV th for Set c when V DS = 10.1 V is V, which is almost identical to the measured value of 0.28 V. Fig. 8 shows the comparison of DV th with respect to V GS+ with measured (scatters) and fitting (lines) data using the parameters listed in Table 4. Both curves appear to reproduce the V th shift very well. 5. Conclusion V DS = 2.1 V We investigated the effects of the channel length variation and alternating pulse bias on the instability of a-igzo TFTs. It was V DS = 10.1 V DV th C V GS D ð5þ [1] Nomura K, Ohta H, Takagi A, Kamiya T, Hirano M, Hosono H. Roomtemperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors. Nature 2004;432: [2] Yabuta H, Sano M, Abe K, Aiba T, Den T, Kumomi H, et al. High-mobility thinfilm transistor with amorphous InGaZnO 4 channel fabricated by room temperature rf-magnetron sputtering. Appl Phys Lett 2006;89: [3] Lopes ME, Gomes HL, Medeiros MCR, Barquinha P, Pereira L, Fortunato E. Gatebias stress in amorphous oxide semiconductors thin-film transistors. Appl Phys Lett 2009;95: [4] Suresh A, Muth JF. Bias stress stability of indium gallium zinc oxide channel based transparent thin film transistors. Appl Phys Lett 2008;92: [5] Cho EN, Kang JH, Kim CE, Moon P, Yun I. Analysis of bias stress instability in amorphous InGaZnO thin-film transistors. IEEE Trans Dev Mater Reliab 2011;11: [6] Lee S, Park S, Kim S, Jeon Y, Jeon K, Park J-H, et al. Extraction of subgap density of states in amorphous InGaZnO thin-film transistors by using multifrequency capacitance-voltage characteristics. IEEE Electron Dev Lett 2010;31: [7] Kimura M, Nakanishi T, Nomura K, Kamiya T, Hosono H. Trap densities in amorphous-ingazno 4 thin-film transistors. Appl Phys Lett 2008;92: [8] Lee S, Jeon K, Park J-H, Kim S, Kong D, Kim DM, et al. Electrical stress-induced instability of amorphous indium gallium zinc oxide thin-film transistors under bipolar ac stress. Appl Phys Lett 2009;95: [9] Son K-S, Kim H-S, Maeng W-J, Jung J-S, Lee K-H, Kim T-S, et al. The effect of dynamic bias stress on the photon-enhanced threshold voltage instability of amorphous HfInZnO thin-film transistors. IEEE Electron Dev Lett 2011;32: [10] Kim SI, Park J-S, Kim CJ, Park JC, Song I, Park YS. High reliable and manufacturable gallium indium zinc oxide thin-film transistors using the double layers as an active layer. J Electrochem Soc 2009;156:H [11] Park J-S, Kim T-W, Stryakhilev D, Lee J-S, An S-G, Pyo Y-S, et al. Flexible full color organic light-emitting diode display on polyimide plastic substrate driven by amorphous indium gallium zinc oxide thin-film transistors. Appl Phys Lett 2009;95: [12] Park S, Cho EN, Yun I. Effects of alternating pulse bias stress on amorphous InGaZnO thin-film transistors. ECS Trans 2012;45: [13] Libsch FR, Kanicki J. Bias-stress-induced stretched-exponential time dependence of charge injection and trapping in amorphous thin-film transistors. Appl Phys Lett 1993;62: [14] Powell MJ. Charge trapping instabilities in amorphous silicon-silicon nitride thin-film transistors. Appl Phys Lett 1983;43: [15] Hsieh H-H, Wu C-C. Scaling behavior of ZnO transparent thin-film transistors. Appl Phys Lett 2006;89: [16] Brotherton SD, Glasse C, Glaister C, Green P, Rohlfing F, Ayres JR. High-speed, short-channel polycrystalline silicon thin-film transistors. Appl Phys Lett 2004;84: [17] ATLAS user s manual. Santa Clara, CA: Silvaco International; [18] Park S, Cho EN, Yun I. Investigation on the relationship between channel resistance and subgap density of states of amorphous InGaZnO thin film transistors. Solid-State Electron 2012;75:93 6. [19] Cho EN, Kang JH, Yun I. Effects of channel thickness variation on bias stress instability of InGaZnO thin-film transistors. Microelectron Reliab 2011;51: [20] Chen Y-C, Chang T-C, Li H-W, Chen S-C, Lu J, Chung W-F, et al. Bias-induced oxygen adsorption in zinc tin oxide thin film transistors under dynamic stress. Appl Phys Lett 2010;96: [21] T.-C. Fung, K. Abe, H. Kumomi, J. Kanicki, P-11: DC/AC Electrical Instability of R.F. Sputter Amorphous In-Ga-Zn-O TFTs. In: SID Tech Dig. vol. 40; p

THERE is considerable interest in adapting amorphous

THERE is considerable interest in adapting amorphous IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 4, APRIL 2014 1109 Electrical Instability of Double-Gate a-igzo TFTs With Metal Source/Drain Recessed Electrodes Gwanghyeon Baek, Linsen Bie, Katsumi