High Performance High-K + Metal Gate Strain Enhanced Transistors on (110) Silicon
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1 High Performance High-K + Metal Gate Strain Enhanced Transistors on (110) Silicon Paul Packan, S. Cea*, H. Deshpande, T. Ghani, M. Giles*, O. Golonzka, M. Hattendorf, R. Kotlyar*, K. Kuhn, A. Murthy, P. Ranade, L. Shifren*, C. Weber* and K. Zawadzki Logic Technology Development, *Process Technology Modeling Intel Corporation IEDM 2008
2 Outline Transistor Scaling Stress Effects on Mobility Comparison of (100) and (110) Silicon Substrates Device Performance Summary IEDM
3 Key Messages Record PMOS drive current of 1.2mA/um is presented for devices on (110) silicon substrates For short gate lengths, NMOS drive currents on (110) substrates are not degraded as much as believed by many in literature The fundamental physics behind these behaviors is understood IEDM
4 Outline Transistor Scaling Stress Effects on Mobility Comparison of (100) and (110) Silicon Substrates Device Performance Summary IEDM
5 Traditional Scaling Id= Cox/Le(Vg-Vt) Source Source Gate Gate Drain Drain 1 na/um Ioff Gate Length REXT Voltage Potential Contours 0.0 R EXT Junction Depth (nm) Traditional device scaling requires all dimensions to scale to maintain performance and leakage Scaling junction depths and S/D areas is causing Rext increase IEDM
6 Constant Leakage Scaling Id= Cox/Le(Vg-Vt) Doping Concentration 2.5E E E E E E+00 Solid Solubility Depth Doping Year Junction Depth Normalized Value VT IDLIN Gate Length IDSAT Junction scaling is slowing due to unacceptable resistance increases Scaling gate lengths at constant leakage requires increasing Vt which results in drive current reduction Traditional device scaling is losing steam IEDM
7 Mobility Scaling Id= Cox/Le(Vg-Vt) Increasing mobility increases device performance without increasing leakage Reducing scattering mechanisms, applying stress and surface orientation all affect mobility Ge Conc. (%) nm 65nm 45nm Technology node Gate-to-SiGe S/D (nm) 65 nm 45 nm IEDM
8 Outline Transistor Scaling Stress Effects on Mobility Comparison of (100) and (110) Silicon Substrates Device Performance Summary IEDM
9 Silicon Band Structure gap conduction band for electrons valence band for holes Electron hh Hole IEDM
10 Stress and Band Structure k y (2 /a) D B Unstressed k x (2 /a) A C 0.2 k y (2 /a) D B M.Giles, AVS 2006 Stressed A C k x (2 /a) (001) surface 1GPa uniaxial stress [110] 1 MV/cm vertical field 30meV energy contours Compression lowers the energy of (C,D) Holes redistribute from (A,B) to (C,D) The effective mass is reduced IEDM
11 Conduction Band Stress Response z Repopulation y y Scattering x [110] x Energy No stress XY Plane [110] uniaxial tensile [001] uniaxial compressive E Mobility gain comes from valley repopulation, valley warping, and scattering suppression M.Giles, AVS 2006 IEDM
12 Stress Effects on Mobility longitudinal stress transverse stress vertical stress longitudinal stress transverse stress vertical stress Mobility Ratio MV/cm MV/cm Electrons Stress MPa Holes Stress MPa Longitudinal tension and vertical compression increases electron mobility Longitudinal compression and vertical tension increases hole mobility Transverse tension increases both electron and hole mobility Hole mobility shows a greater sensitivity to stress for (100) IEDM
13 Stress Methods Capping Layers Gate Induced Epitaxial Layers Contacts C. Auth, VLSI 2008 IEDM
14 1000 VDD = 1.0V NMOS Stress Contact Stress Ioff(nA/ m) % 10 Tensile Fill Control Idsat(mA/ m) 1000 VDD = 1.0V Gate Stress Ioff (na/ m) % Compressive Gate Control Idsat (ma/ m) C. Auth, VLSI 2008 IEDM
15 PMOS Stress SiGe Stress K.Mistry, 2004 VLSI IEDM
16 Outline Transistor Scaling Stress Effects on Mobility Comparison of (100) and (110) Silicon Substrates Device Performance Summary IEDM
17 Substrate Orientation (100) (110) [010] [001] [100] [100] [010] [001] calculated using MASTAR ( IEDM
18 PMOS Hole Occupation and Band Structure (100) (110) stressed unstressed ky <-110> ky <001> constant energy contours kx <110> kx <110> More dense contour lines show lower effective mass for (110) PMOS hole occupation of band structure shows a larger difference between unstressed and stressed devices for (100) IEDM
19 Stress Response of Electron Mobility Mobility Ratio longitudinal stress stress transverse stress transverse stress vertical stress vertical stress (100) Electrons Stress MPa longitudinal stress transverse longitudinal stress stress vertical transverse stress stress vertical stress (100) (110) Electrons Holes Mobility Ratio Stress MPa Stress MPa Stress MPa Longitudinal tension improves (100) and (110) mobility Vertical and transverse stress show opposite dependencies Stress sensitivity is larger for (110) substrate orientation IEDM
20 Stress Response of Hole Mobility Mobility Ratio longitudinal stress longitudinal stress transverse stress vertical transverse stress stress vertical stress vertical stress Mobility Ratio longitudinal stress transverse stress vertical stress (100) (110) Electrons Holes Holes Stress MPa Stress MPa Stress MPa MPa Longitudinal compression improves (100) and (110) mobility Vertical and transverse tension improves (100) and (110) mobility Stress sensitivity is larger for (100) substrate orientation IEDM
21 Simulated Hole and Electron Mobility Hole Mobility (cm 2 /Vs) (100) Mobility (110) Mobility 1.6x Hole 3.5x <110> Stress (MPa) x (100) Mobility (110) Mobility 2000 Electron 1000 <110> Stress (MPa) 2.5x Electron Mobility (cm 2 /Vs) Hole mobility increases and electron mobility decreases for (110) substrates The difference in mobility depends on device stress IEDM
22 Outline Transistor Scaling Stress Effects on Mobility Comparison of (100) and (110) Silicon Substrates Device Performance Summary IEDM
23 45 nm Hi-K+Metal Gate Technology Based on Intel s 45 nm process technology High-k first, metal gate last process architecture 35nm gate length 160 nm contacted gate pitch 1.0 nm EOT High-k Dual workfunction metal gate electrodes 3 RD generation strained silicon K.Mistry IEDM 2007 IEDM
24 (110) and (100) PMOS Idsat Ioff IOFF (A/um) (A/um) 1E-5 1E-6 1E-7 1E-8 1E Idsat (ma/um) IDSAT (ma/um) % (110) (100) Record PMOS drive currents of 1.2 ma/um at 1.0V and 100nA/um Ioff are reported for (110) substrates The performance improvement is 15% for (110) substrates compared to (100) substrates IEDM
25 PMOS (110)/(100) Idsat Improvement versus Stress PMOS % IDSAT improvement 50% experimental (110)/(100) data 40% (110)/(100) 30% 20% 10% 0% 0% 10% 20% 30% 40% Ge Fraction Under stress, the relative hole mobility between (110) and (100) substrates decreases due to the larger stress sensitivity of mobility on the (100) substrate Even under high stress, substantial performance improvement is seen IEDM
26 (110) and (100) NMOS Idsat 1E-7 160nm Lgate 1E-5 35nm Lgate Ioff (A/um) 1E-8 1E-9 1E-10 40% 1E Idsat IDSAT (ma/um) (110) (100) Ioff IOFF (A/um) 1E-6 1E-7 1E-8 1E-9 13% (110) (100) Idsat IDSAT (ma/um) As channel lengths are decreased, NMOS performance loss on (110) substrates is reduced Why is the degradation reduced? IEDM
27 Surface Confinement Effect [110] Bulk conduction m [110] =0.43m e (100) surface confinement (110) surface confinement Ground state [110] m [110] =0.19m e [110] m [110] =0.55m e Surface confinement changes ground state transport mass Separation depends on confinement field IEDM
28 Local Electron Mobility Electron Density (/cm 3 ) 1e20 1e18 1e16 1e14 1e12 (100) inversion layer at center of channel Device Length 30nm 60nm 0.03 um 0.06 um 1e Distance from Surface (A) (110)/(100) mobility ratio (a) source mid- Source Channel drain Drain tip/channel channel tip/channel Lgate nm nm nm nm LC LC Slice Location Location along along Device the Lgate k. p calculations for an unstressed device show the maximum degradation occurs near the middle of the channel As the channel lengths is decreases, the carrier confinement is reduced due to 2D short channel effects IEDM
29 2D Effects on Valley Splitting Valley Splitting splitting due to Confinement Field field for Long in Long Channel Device Valley Splitting splitting Reduction reduced in due Short to 2D SCE for Short Channel Channel Device E o E 1 E 1 -E 2 =large E o E 1 E 1 -E 2 =reduced due E 2 to 2D short-channel effects E 2 Reduced carrier confinement in short channel devices due to 2D effects reduce the valley splitting This reduction results in reduced NMOS performance loss for (110) substrates IEDM
30 Simulated 2D Effects Simulated NMOS and PMOS performance both with and without 2D effects The NMOS devices shows a large reduction in short channel degradation when 2D effects are included Due to high stress effects in the PMOS device, little change is seen by including the 2D effects. IEDM
31 Narrow Width Stress Effects STI Expand Compress Gate Channel % IDSAT Loss 0% -2% -4% -6% -8% -10% NMOS (110)/(100) -12% -14% Device Width (um) STI causes compressive transverse stress in the channel which increases at narrower device widths Transverse compression improves (110) and degrades (100) electron mobility NMOS performance for typical devices is only degraded by 5-8% IEDM
32 Reliability Data Relative BTI (100) (110) (100) (110) NMOS PMOS BTI reliability data for 45nm high-k+metal gate devices show no intrinsic difference between (100) and (110) substrate orientations IEDM
33 Outline Transistor Scaling Stress Effects on Mobility Comparison of (100) and (110) Silicon Substrates Device Performance Summary IEDM
34 Summary Record PMOS drive current of 1.2mA/um are shown PMOS drive currents on (110) substrates show a 15% performance improvement NMOS drive currents on (110) substrates for typical device widths are only degraded 5-8% The fundamental physical reason behind these behaviors is understood The use of (110) silicon substrates is a promising technology option IEDM
35 For further information on Intel's silicon technology, please visit our Technology & Research page at IEDM
Portland Technology Development, * CR, # QRE, % PTM Intel Corporation
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