Strain for CMOS performance Improvement

Transcription

1 IBM Corporation Strain for CMOS performance Improvement +Victor Chan, +Ken Rim, #Meikei Ieong, +Sam Yang, +Rajeev Malik, Young Way Teh, #Min Yang, #Qiqing (Christine) Ouyang +IBM Systems & Technology Group, #IBM Research Division, T. J. Watson Research Center and Chartered Semiconductor Mfg. Ltd IBM Semiconductor Research and Development Center (SRDC) Hopewell Junction, NY 12533

2 Outline * Introduction: Strain helps carriers to travel faster * Substrate-induced strain * Process-induced strain - Contact etch-stop nitride liner (DSL) - Stress Memorization Technique (SMT) - Embedded SiGe in S/D (e-sige) * Stress and Device / Circuit Implication * Mobility Improvement beyond Stress Engineering - Channel Orientation - Substrate Orientation (eg. HOT, DSB) * Summary Fort Collins, Jan 27 Page 2

3 Outline * Introduction: Strain helps carriers to travel faster * Substrate-induced strain * Process-induced strain - Contact etch-stop nitride liner (DSL) - Stress Memorization Technique (SMT) - Embedded SiGe in S/D (e-sige) * Stress and Device / Circuit Implication * Mobility Improvement beyond Stress Engineering - Channel Orientation - Substrate Orientation (eg. HOT) * Summary Fort Collins, Jan 27 Page 3

4 Mechanical Stress: basic A Material A (tens/comp) (eg. Nitride) Material B (eg. Si) Due to material mismatch of A & B from material composition, element size / volume and thermal expansion rate, A will introduce mechanical stress to B. Strained Si Stress transfer Carrier B A Relax Si 1-x Stress transfer Carrier B Fort Collins, Jan 27 Page 4

5 Mechanical Stress : many ways A A Stress transfer Carrier B Stress transfer B Carrier A B Carrier Many different ways Stress transfer dependent on material A deposition / growth condition (eg. process temp, material) subsequent steps (eg. annealing, implantation) gate gate Carrier Carrier source drain source drain Uniaxial stress: 1-direction biaxial stress: 2-directions Fort Collins, Jan 27 Page 5

6 Electrons have higher mobility in Strained (biaxial tensile) Si Ec Ev Eg Conduction Band Unstrained Si <100> <001> Ec fold degenerate conduction valleys <010> fold valleys Biaxial tensile Si in 100 and 010 direction <001> 2 fold valley (lowest E) <100> In Strained Si, i) m* (effective mass) is smaller higher mobility ii) split energy band less inter-valley scattering higher mobility m l m t <010> Larger curvature smaller m* µ = qτ * m K. Rim, VLSI Sym 2002 Fort Collins, Jan 27 Page 6

7 Holes have higher mobility in Strained (biaxial tensile) Si Ec Eg HH HH = heavy holes LH = light holes Valence Band Unstrained Si Ev LH E Spin-orbit m* is rated average of m*(hh) and m*(lh) k 2 fold degenerate valence band (Lower E) Spin-orbit strained Si In Strained Si, i) m* (effective mass) is smaller higher mobility ii) split energy band less carrier scattering higher mobility LH HH in-plane (x,y) E k Out-of-plane (z) K. Rim, VLSI Sym 2002 Fort Collins, Jan 27 Page 7

8 Desired uni-axial stress on CMOS performance gate gate Source Drain Transverse Source Z Drain Longitudinal NMOS PMOS Longitudinal X Tensile Compressive Transverse Y Tensile Tensile Si Depth Z Compressive Tensile Fort Collins, Jan 27 Page 8

9 Longitudinal stress provides different drive current n(100) n(110) nfetion Ioff=100nA/um Ion 100nA/um A B C D E F p(110) p(100) pfet Ion (ua/um) Ion Ioff=100nA/um A B C D E F Compressive Neutral Tensile Fort Collins, Jan 27 Page 9

10 Technology in this presentation IBM 90 / 65nm CMOS technology VCC (V) Lpoly (nm) Tox (nm) Fort Collins, Jan 27 Page 10

11 Outline * Introduction: Strain helps carriers to travel faster * Substrate-induced strain * Process-induced strain - Contact etch-stop nitride liner (DSL) - Stress Memorization Technique (SMT) - Embedded SiGe in S/D (e-sige) * Stress and Device / Circuit Implication * Mobility Improvement beyond Stress Engineering - Channel Orientation - Substrate Orientation (eg. HOT) * Summary Fort Collins, Jan 27 Page 11

12 Strain in Si-based Heterostructures Cubic Lattice at Equilibrium Ge Si 1-x Ge x Si β-sic a a / a x Si Si = x Pseudomorphically Grown Epitaxial Layers Pseudomorphically Grown Epitaxial Layers Strained Strained Si Si 1-x Ge x Relaxed Si Si 1-x Ge x Unstrained Si Tensile-Strained Si on Si 1-x Ge x Compressively Compressive-Strained Si Si 1-x Ge x on Si Fort Collins, Jan 27 Page 12

13 Schematic diagram to show three ways of formation of strained Si MOS devices a) Strained Si/SiGe on bulk wafer b) SiGe-on-Insulator (SGOI) c) Strained-Si Directly On Insulator (SSDOI) MOSFET Strained Si SiGe Si substrate Strained Si SiGe Buried oxide Si substrate Strained Si Buried oxide Si substrate K. Rim, VLSI 2002, B. H. Lee IEDM 2002, K. Rim IEDM 2003 Fort Collins, Jan 27 Page 13

14 Ioff I (A/µm) (na/um) NMOS shows benefits with biaxial tensile strained Si with 13% & 28% Ge Higher NMOS Ion improvement with higher % Ge E E-7 1E E E E-11 Strain Str. Si/SiGe / SiGe (13% (13% [Ge]) Ge) Control nfet NMOS 400.0µ 600.0µ 800.0µ I on (A/µm) Ion (ua/um) 1000 Effective e- Mobility (cm/v-sec) Effective Electron Mobility (cm/v*sec) Str. Si / Relax SiGe 28% Str. Si / Relx. SiGe 28% Str. Si Si / Relx. / Relax SiGe SiGe 13% 13% Str. Si Si / Str. / Str SiGe SiGe 30% 30% / Relx. / Relax SiGe 13% SiGe 13% 110% 200 Control control Mobility Universal Mobility k 1.0M 1.5M % Effective Effective Field, (E E eff (V/cm) eff (MV/um)) K. Rim, VLSI Sym, 2002 Fort Collins, Jan 27 Page 14

15 PMOS shows benefits with Biaxial Tensile Strained Si with 28% Ge pmos Ion only improved with high % Ge in SiGe, eg. > 20%. Ioff (na/um) I (A/µm) off E E E-8 1 1E E-10 pfet PMOS Strain Si / SiGe (28% Ge) Control Strain Str. Si/SiGe / SiGe (28% Ge) [Ge]) Control 200 I (A/µm) Ion (ua/um) 200.0µ 400.0µ K. Rim, VLSI Sym, 2002 Fort Collins, Jan 27 Page 15

16 % Ge vs mobility Mobility Enhancement Factor Strain = (a Str.Si -a Si )/a Si (%) N inv = 1e13 cm -2 Chan.Dop.= 2e17 cm good bad Equivalent [Ge] in Fully Relaxed SiGe (%) nmos (e - ) pmos (h + ) Uniaxial longitudinal tensile stress Biaxial tensile stress Good Good Bad Dependent on %Ge K. Rim, VLSI Sym, 2002 Fort Collins, Jan 27 Page 16

17 Outline * Introduction: Strain helps carriers to travel faster * Substrate-induced strain * Process-induced strain - Contact etch-stop nitride liner (DSL) - Stress Memorization Technique (SMT) - Embedded SiGe in S/D (e-sige) * Stress and Device / Circuit Implication * Mobility Improvement beyond Stress Engineering - Channel Orientation - Substrate Orientation (eg. HOT) * Summary Fort Collins, Jan 27 Page 17

18 Ion enhancement using stress liner compared to neutral liner (non-stressed process) for nmos nmos Ion improves with higher Tensile nitride liner 10-4 a) NMOS Tensile Nit N Ioff (A/µm) Un-stress tensile Ion (µa/µm) H. S. Yang, IEDM 2004 Fort Collins, Jan 27 Page 18

19 Ion enhancement using stress liner compared to neutral liner (non-stressed process) for pmos pmos Ion improves with higher Compressive nitride liner 10-5 b) PMOS Comp Nit P Ioff (A/µm) Un-stress Compressive Ion (µa/µm) H. S. Yang, IEDM 2004 Fort Collins, Jan 27 Page 19

20 SEM cross-section of an SRAM cell features tensile and compressive liner in NMOS and PMOS respectively IBM powerpc TM micro-processor Fmax vs power improves 7 % with DSL due to higher current. Tensile nit Contact Compr nit N P ST oxide Buried tensile Compr N P Fort Collins, Jan 27 H. S. Yang, IEDM 2004 Page 20

21 Nitride film stress changes after annealing Nit film stress tends to be tensile after annealing Annealing temperature will affect hot-carrier reliability nit stress vs anneal temp Tensile annealing Tensile liner A Neutral Performance Reliability Compressive Compressive liner B After nitride Liner deposition After C temperature annealing K. Lim, EESDERC, 2005 Fort Collins, Jan 27 Page 21

22 Nitride film stress will be relaxed after Ge implant Tensile nit Contact Tensile Nit + Ge Compr nit Ge implantation destroys and relaxes nit film N Buried ST oxide P Nit film stress tends to be tensile after annealing Tensile Tensile liner A Neutral Compressive After nitride Liner deposition After Ge implantation Compressive liner B After C annealing H. S. Yang, IEDM 2004 Fort Collins, Jan 27 Page 22

23 Outline * Introduction: Strain helps carriers to travel faster * Substrate-induced strain * Process-induced strain - Contact etch-stop nitride liner (DSL) - Stress Memorization Technique (SMT) - Embedded SiGe in S/D (e-sige) * Stress and Device / Circuit Implication * Mobility Improvement beyond Stress Engineering - Channel Orientation - Substrate Orientation (eg. HOT) * Summary Fort Collins, Jan 27 Page 23

24 Integration process of SMT Amorphous layer by implant After anneal & Nit Removal Stress will be transferred from the nitride film to the channel during annealing. Si is crystallized and stress is memorized Fort Collins, Jan 27 Page 24

25 SMT vs DSL SMT contact end-stop liner Sensitive to Nitride material yes yes (stress, thickness) Require Annealing yes No (dependent on annealing temperature and ramp rate) Sensitive to a-si layer yes some (from extension & S/D implant, dependent on implant species, dose, energy) Sensitive to transistor profile yes yes (eg. gate height, spacer shape and material) Fort Collins, Jan 27 Page 25

26 SMT annealing Purpose of annealing: i) Tensile transfer from nitride to Si channel through amorphorization layer in S/D, extension and poly gate. ii) a-si crystallization STI from a-si to c-si layer after anneal STI Fort Collins, Jan 27 Page 26

27 NMOS: 15% current improvement with Disposable Tensile Stressor nfet Ioff (na/um) e e e -0 7 Control Tensile Nit stressor 1 1 e -0 8 Tensile contact etch-stop liner is used a b s ( M 1 FN1 0 x p 1 0,0.0 8, M 1 Io n ) nfet Ion (ua/um) Fort Collins, Jan 27 Page 27

28 SMT benefit with different types of Nitiride stressor Stress properties of nitride material is changed after annealing % nmos Ion at target Ioff 115% 110% 105% 100% POR OP_Comp Compr nit No SMT AMAT ~ OP_Nutural Neutral nit BTBAS Nov Tens nit Relative OP Nitride stress liner stress Fort Collins, Jan 27 Page 28

29 Outline * Introduction: Strain helps carriers to travel faster * Substrate-induced strain * Process-induced strain - Contact etch-stop nitride liner (DSL) - Stress Memorization Technique (SMT) - Embedded SiGe in S/D (e-sige) * Stress and Device / Circuit Implication * Mobility Improvement beyond Stress Engineering - Channel Orientation - Substrate Orientation (eg. HOT) * Summary Fort Collins, Jan 27 Page 29

30 PMOS with e-sige structure in S/D Uniaxial stress in Si channel induced by SiGe S/D higher hole mobility to enhance drive current nit Nit liner SiGe SiGe PMOS SiGe SiGe Uniaxial compressive strain Si Substrate C. Ouyang,VLSI Sym, 2005 Fort Collins, Jan 27 Page 30

31 SEM photo and SiGe grow rate SiGe epi growth rate in S/D is dependent on pattern density Base on (100) wfr and 15% Ge pmos Strained Si SiGe pmos Strained Si Growth Rate (Angstrom/sec) blanket patterned C. Ouyang,VLSI Sym, 2005 Fort Collins, Jan 27 Page 31

32 PMOS Ion-Ioff for e-sige esige No-eSiGe esige+ Compr nit liner From iedm 05, ibm, Luo Fort Collins, Jan 27 Page 32

33 Outline * Introduction: Strain helps carriers to travel faster * Substrate-induced strain * Process-induced strain - Contact etch-stop nitride liner (DSL) - Stress Memorization Technique (SMT) - Embedded SiGe in S/D (e-sige) * Stress and Device / Circuit Implication * Mobility Improvement beyond Stress Engineering - Channel Orientation - Substrate Orientation (eg. HOT) * Summary Fort Collins, Jan 27 Page 33

34 Ion_N / Ion_P ratio in the Recent Technology Nodes Stress engineering Ion changes Ion_N / Ion_P (beta) ratio may change 2.6 IonN / IonP ratio Tens N, Neut P Tens N, Compr P Neut N, Compr P Neutral N, Neutral P technology node (nm) Fort Collins, Jan 27 Page 34

35 Vt shift due to longitudinal tensile stress Channel Stress can change the energy band gap of Si channel Vtlin (V) Vtlin(V) Vtlin (V) Un-stress control Disposable Stressor Tensile Un-stress control Tensile n POR n OP p POR p OP Disposable Stressor process Without pmos selective RIE Lpoly 0.1 (um) Lgate (um) Lpoly (um) Fort Collins, Jan 27 Page 35

36 Different Active Sizes (along channel) STI provides longitudinal stress and affect N/P Ion. X-direction: more compressive IonN decreases, IonP increases X nmos Ion pmos Ion active size active size Ion changes % Ion change from large from Rx=1.2 to small to 0.24um active size 0 % %Ion All all W=10um Ion changes % Io n from ch an glarge e fro m to R x=1.2 small to 0.24u active m size 25 % %Ion Ion nmos L (um) L_Design (µm) pmos All all W=10umW L (u m ) 1 10 L_Design (µm) V. Chan, IEDM 2003 Fort Collins, Jan 27 Page 36

37 STI Stress Proximity Effect (Different Device Lengths) drive Drive current current change (%) Lgate (µm) active size size PFET pmos NFET nmos n-10x0.045 n-10x0.24 n-10x10 p-10x0.045 p-10x0.24 p-10x active size (symmetric) (um) active size (symmetric) (µm) V. Chan, IEDM 2003 Fort Collins, Jan 27 Page 37

38 Different Active Sizes with different widths (bi-axial effect) STI provides both longitudinal and lateral stress and affect N/P Ion. X Z Z-direction: more compressive IonN decreases, IonP decreases Ion changes from large to small active size % Ion %Ion % Ion %Ion % Ion change from Rx=1.2 to 0.24um nmos All all L=0.08um L=45nm W (um) width (µm) % Ion change from Rx=1.2 to 0.24um Ion changes from large to small active size pmos all All L=0.08um L=45nm Z W (um) Width (µm) V. Chan, IEDM, 2003 Fort Collins, Jan 27 Page 38

39 STI Stress Proximity Effect (Different Device Widths) drive current change (%) Drive current (%) W(µm) , NFET active size active size pmos PFET nmos n-10x0.045 n-0.24x0.045 n-0.12x0.045 p-10x0.045 p-0.24x0.045 p-0.12x active size (symmetric) (um) active size (symmetric) (µm) V. Chan, IEDM, 2003 Fort Collins, Jan 27 Page 39

40 Technology development & Stress Engineering (1) [Stress engineering is developed early] Base Line Development Pre-manufacturing Develop Strained Si Fabrication Process Modify Device model after mobility enhancement; include STI stress proximity model Mask tape-out (additional mask may be required) Stress Engineering Discovery Circuit Design Circuit adjustment Time Fort Collins, Jan 27 Page 40

41 Technology development & Stress Engineering (2) [Stress engineering is developed a little bit late] Base Line Development Pre-manufacturing Develop Strained Si Fabrication Process (late development) Stress Engineering Discovery Not Modify Device model after mobility enough enhancement; include Time STI stress proximity model Circuit Design Mask tape-out (additional mask may be Required. logic vs array) Not Enough Time Circuit adjustment Time Fort Collins, Jan 27 Page 41

42 Technology development & Stress Engineering (3) [Device adjustment] Stress engineering will change the devices: 1) Ion 2) Vt and Ioff The change will be also dependent on i) Active area dimension (longitudinal and lateral) ii) Device length and width Pre-manufacturing a) Device re-centering b) Additional mask * different circuit region (eg. SRAM array) may have different device centering conditions c) SRAM stability & yield consideration * Device centering to provide good read stability and writibility margin Time Fort Collins, Jan 27 Page 42

43 Technology development & Stress Engineering (4) [Other consideration] i) Extra fabrication process. It may involve : a) substrate preparation; b) nitride deposition process temperature, thickness, stress level, conformity c) extra annealing this may affect dopant activation / d) lithography; e) dry etch / wet etch; f) implantation. deactivation and device reliability (eg hot carrier); ii) Ground rule consideration, especially in the SRAM cell. iii) Critical path and circuit performance. iv) Stress Monitoring by electrical device data and in-line stress monitoring procedure. v) Fabrication process: cycle time, repeatability, uniformity, cost and yield. Fort Collins, Jan 27 Page 43

44 Outline * Introduction: Strain helps carriers to travel faster * Substrate-induced strain * Process-induced strain - Contact etch-stop nitride liner (DSL) - Stress Memorization Technique (SMT) - Embedded SiGe in S/D (e-sige) * Stress and Device / Circuit Implication * Mobility Improvement beyond Stress Engineering - Channel Orientation - Substrate Orientation (eg. HOT) * Summary Fort Collins, Jan 27 Page 44

45 0 vs 45 deg notch X (100) <011> channel Z (001) < 011> channel 0 o notch Y (010) X (100) <001> channel Z (001) <010> channel 45 o notch Y (010) Fort Collins, Jan 27 Page 45

46 <110> (0deg notch) pmos mobility is very sensitive to longitudinal stress sensitive 10-6 pmos Ioff (A/um) Neutral compressive tensile M 1 FP10x_07,0.08,0.10 M 1 Io n pmos Ion (ua/um) Fort Collins, Jan 27 Page 46

47 <100> (45deg notch) pmos mobility is insensitive to longitudinal stress insensitive pmos Ioff (A/um) Neutral tensile compressive pmos Ion (ua/um) Fort Collins, Jan 27 Page 47

48 Both <110> (0 deg) and <100> (45deg notch) nmos mobilities are very sensitive to longitudinal stress 10-6 nmos Ioff (A/um) Ioff (nmos) e-06 e-07 Tensile 45deg 0deg Ion (nmos) 10-9 Neutral compressive tensile Solid = <110> channel Open = <100> channel nmos Ion (ua/um) Fort Collins, Jan 27 Page 48

49 <100> pmos is not sensitive to STI proximity stress 10-7 <100> p-channel pmos Ioff (A/um) Large Rx overhang Small Rx overhang pmos Ion (ua/um) pmos Ioff (A/um) 1e pfet Ioff/W 1e <110> p-channel Large Rx overhang Small Rx overhang 10 1e pfet Ion/W pmos Ion (ua/um) Fort Collins, Jan 27 Page 49

50 Outline * Introduction: Strain helps carriers to travel faster * Substrate-induced strain * Process-induced strain - Contact etch-stop nitride liner (DSL) - Stress Memorization Technique (SMT) - Embedded SiGe in S/D (e-sige) * Stress and Device / Circuit Implication * Mobility Improvement beyond Stress Engineering - Channel Orientation - Substrate Orientation (eg. HOT, DSB) * Summary Fort Collins, Jan 27 Page 50

51 (100) and (110) wafers (100) plane <011> channel (110) plane <110> channel Note: <110> and <001> channel in (110) substrate have different mobility enhancement. Fort Collins, Jan 27 Page 51

52 Carrier Mobility Dependence on Surface Orientation Holes Electrons Electron mobility is highest on (100) surface Hole mobility is highest on (110) surface Combine the (100) and (110) surfaces to obtain the highest mobility for electrons and holes M. Yang, IEDM 2003, M. Yang, VLSI 2004 Fort Collins, Jan 27 Page 52

53 CMOS fabrication on Substrates with Hybrid Orientation (1) M. Yang, IEDM 2003, M. Yang, VLSI 2004 Fort Collins, Jan 27 Page 53

54 CMOS fabrication on Substrates with Hybrid Orientation (2) M. Yang, IEDM 2003, M. Yang, VLSI 2004 Fort Collins, Jan 27 Page 54

55 CMOS Structure Using HOT Type A Type B pmos on (110) SOI nmos on (100) epi-si nmos on (100) SOI pmos on (110) epi-si Key Process Step Selective Epitaxy layer bonding Type A grow (100) Si in (110) Si Type B grow (110) Si in (100) Si M. Yang, IEDM 2003, M. Yang, VLSI 2004 Fort Collins, Jan 27 Page 55

56 Carrier Mobility Dependence on Surface Orientation PMOS NMOS pmos on (110) surface and nmos on (100) surface Forming hybrid substrate using wafer bonding and Si epitaxy One additional litho level Planar structure, fully compatible with standard CMOS processes M. Yang, IEDM 2003, M. Yang, VLSI 2004 Fort Collins, Jan 27 Page 56

57 Performance of CMOS on Bulk Silicon Substrates pmos pfet Ioff (na/um) e e-06 M1 FP10x_08 M1 Ioff 10 1e e No degradation of Ion by epi-(110). PMOS (100) (110) V dd =1V Compr contact nit liner 1e pfet Ion (ua/um) nmos Ioff (A/um) (110) NMOS (100) Tensile contact nit liner nmos Ion (ua/um) Ioff = 100uA/um Ioff = 10nA/um PMOS Ion +20% +26% NMOS Ion -35% -50% M. Yang, IEDM 2003, M. Yang, VLSI 2004 Fort Collins, Jan 27 Page 57

58 HOT NMOS has same Ion as conventional bulk NMOS and bulk SOI HOT nmos (on BOX) Conventional Bulk NMOS Conventional SOI nmos NMOS Ioff (A/um) Vdd=1V NMOS Ion (ua/um) M. Yang, IEDM 2003, M. Yang, VLSI 2004 Fort Collins, Jan 27 Page 58

59 Carrier mobilities in (100) and (110) substrates are both sensitive to longitudinal stress in channel. Ion change (%) n(100) p(100) A B C D E F Ion change (%) n(110) p(110) A B C D E F Compressive Neutral Tensile Fort Collins, Jan 27 Page 59

60 PMOS on (110) substrate performance is further enhanced by stress engineering Ion = Ioff=100nA/um Fort Collins, Jan 27 Page 60

61 Mobility Enhancement is dependent on device orientation 1000 (100), X,Y (110)-Y (compressive) (110)-X (compres) PMOS Ioff (na/um) (110)-Y (110)-X Solid symbol = X = [110] direction Open symbol = Y = [001] direction X Y PMOS Ion (ua/um) C. D. Sheraw,VLSI 2005 Fort Collins, Jan 27 Page 61

62 Ring Oscillator Delay is improved by higher PMOS Ion with HOT process Quasi Standby Current (A) A n/p=(100) B (HOT) C (HOT+DSL) A B C NMOS (100) SOI Tens liner (100) SOI Tens liner (100) SOI Tens liner PMOS (100) SOI Neutral liner (110) bulk Neutral liner (110) bulk Comp liner Delay (ps/stage) C. D. Sheraw,VLSI 2005 Fort Collins, Jan 27 Page 62

63 DSB Direct silicon Bonding N P N HOT (p=bulk, n = SOI) (110) Ox free interface (100) DSB (n/p = bulk) (110) S T I a-si S T I (110) S T I (100) S T I (110) Handle wafer Si (100) Handle wafer Si (100) Handle wafer Si (100) Step 1: (110)/(100) DSB Step 2: selective implant Step 3: SPE & CMOS SPE=solidd phase epitaxy Fort Collins, Jan 27 Page 63

64 pfet performance comparison pfet Ring pfets on DSB shows 35% enhancement compared to (100) Ring oscillator speed is improved by higher pfet Ion in DSB. DSB=direct silicon bonding SPE=soild phase epitaxy Fort Collins, Jan 27 Page 64

65 (100) vs (110) substrates: vector notation (100) substrate X <011> channel Z (001) don t be confused by <110> channel in (100) Substrate and (110) substrate < 011> channel (110) substrate Y (010) X (100) Z (001) Y (010) <001> channel (bad) <110> channel (good) Fort Collins, Jan 27 Page 65

66 0 deg vs 45 deg on (100) wafer: vector notation (100) plane Z,001 Y,010 X, o 45 o <110> 0 o channel, 0 deg notch (100) plane 90 o 45 o <100> 0 o channel, 45 deg notch Fort Collins, Jan 27 Page 66

67 Outline * Introduction: Strain helps carriers to travel faster * Substrate-induced strain * Process-induced strain - Contact etch-stop nitride liner (DSL) - Stress Memorization Technique (SMT) - Embedded SiGe in S/D (e-sige) * Stress and Device / Circuit Implication * Mobility Improvement beyond Stress Engineering - Channel Orientation - Substrate Orientation (eg. HOT) * Summary Fort Collins, Jan 27 Page 67

68 Summary NMOS PMOS Disadvantage & limitation Biaxial Tensile Strain Extra cost on substrate, difficulty in substrate preparation, integration, & device design. Contact etch-stop liner (DSL) Extra steps in integration, ground rule considera tion SMT o Extra steps in integration e-sige o High process complexity, difficulty in epigrowth, yield Substrate Orientation (HOT, DSB) o Extra Cost on hybrid substrate, extra steps eg. Epi to prepare isolation Channel Orientation (<100>, 45deg) o No further improvement in PMOS current Fort Collins, Jan 27 Page 68

69 Acknowledgement IBM SRDC System and Technology Group, IBM Yorktown Research, ICIS alliance (IBM, Chartered, Infineon, Samsung), ASTA alliance (IBM, AMD, Sony, Toshiba) Fort Collins, Jan 27 Page 69