Development and Characterization of Large Silicon Microchannel Heat Sink Packages for Thermal Management of High Power Microelectronics Modules

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1 Development and Characterization of Large Silicon Microchannel Heat Sink Packages for Thermal Management of High Power Microelectronics Modules Hengyun Zhang*, Qingxin Zhang*, Ser-Choong Chong*, Damaruganath Pinjala*, Xiaoping Liu**, Poh-Keong Chan** *Institute of Microelectronics, 11 Science Park Road, Science Park II, Singapore Tel: (65) ; Fax: (65) ; **DSO National Laboratories, 20 Science Park Drive, Singapore Abstract In this paper, the development of large-sized silicon microchannel heat sink (SMHS) packages for high power dissipation microelectronic modules is presented. The microchannel wafer was designed and fabricated through deep reactive ion etching on the 8 (100) wafer, which included 500 microchannels arranged in parallel and each channel possessed a depth of 400µm. The channel wafer was then bonded to a cover wafer to form the closed flow channel. Two wafer bonding techniques, gold diffusion bonding and bis-benzocyclobutene (BCB) bonding, were evaluated. Large thermo-mechanical stress was induced in the first technique, which may not be suitable for the large silicon wafer bonding. In the second technique, a BCB bonding process was successfully developed by producing a bonding layer of around 5µm of minimal stress and free from micro voids. Fluidic interconnects were formulated through the use of elastic room-temperature vulcanizing silicone material between the cover wafer and the metallic housing to minimize the bonding stress. Both hydraulic tests and thermal modeling were conducted for the fabricated SMHS packages. All the heat sink packages with BCB bonding passed hydraulic tests at around 60 psi at a flowrate of 4 l/min, whereas those with gold diffusion bonding were found to fail at a pressure of psi. The workability of the SMHS package for thermal management of high power microelectronics modules is demonstrated through a thermal model. Keywords: silicon microchannel heat sink (SMHS), gold diffusion bonding, BCB bonding, micro void, thermal management, hydraulic tests Introduction Increasing demand for high performance microelectronics modules requires packaging of multiple chips on large heat sinks. Recently, silicon microchannel heat sinks (SMHSs) based on liquid cooling become an enabling thermal management technology for high performance operation [1, 2]. The advantages of the SMHS lie in factors such as established microfabrication and bonding techniques, devicematched thermal expansion coefficient and patterned mounting of microelectronic chips and modules. In the packaging of the SMHS, wafer bonding techniques such as gold eutectic diffusion process has been used [3] in small wafers. Thermo-mechanical stress could degrade the device quality with the increase in wafer bonding size. The fabrication, packaging and characterization of large sized SMHSs for microelectronic modules mounted with many chips are not well reported in previous studies. In this paper, the development and characterization of large-sized silicon microchannel heat sink packages for high power multi-chip modules are documented. The designed SMHS includes 500 microchannels arranged in parallel, each channel with rectangular cross-section of 400µm deep. The flowchart for the development of the SMHS package is listed in Fig.1. The microchannels were fabricated through deep reactive ion etching (DRIE) from 8 (100) wafers. Such a heat sink design has been targeted to dissipate waste heat of 2kW from operating modules. The fabricated microchannel wafer was bonded to another cover wafer, which was wetetched in advance with two pairs of through holes to form the flow channel and to reinforce the microchannel wafer. Two wafer bonding methods, gold eutectic bonding and bisbenzocyclobutene (BCB) bonding, were utilized and evaluated. The obtained wafer pair was then bonded to an aluminum housing through a room-temperature vulcanizing silicone material to form the fluidic connections. The hydraulic testing and thermal analysis of the SMHSs in the liquid cooling systems was also conducted to examine the workability of the present SMHSs. Fabrication of microchannels The silicon microchannel heat sink was made in two wafer scheme on 8 (100) wafer. The channel wafer consisted of deep silicon trenches serving as the microchannels for heat exchange. The cover wafer with two pairs of inlet/outlet ports was stacked on the channel wafer to form the fluidic connections as well as to reinforce the mechanical strength of SMHS. The schematic of the SMHS fabrication process flow is illustrated in Fig. 2. To fabricate the micro channel wafer, PECVD oxide of 2µm was deposited on wafer front side as hard mask layer. Deep reactive ion etching (DRIE) technique was used to achieve the silicon trenches of 400 microns deep. An inductive coupled plasma (ICP) etching tool from Surface Technology Systems was used in the DRIE process (Bosch Process). A series of short etching and passivation steps were alternatively taken to achieve the required channel depth. The silicon etch rate was about 2-3µm/min which slightly varied with the silicon trench aspect ratio. The scalloping of the silicon channels were eliminated through adjusting the etch rate. In the cover wafer fabrication, a single-mask double-sided etching was implemented. Thermal oxide of 1000 Ångströms and LPCVD nitride of 1000 Ångströms were deposited subsequently on both sides of the wafer as silicon etching protection layer. After patterning both sides of the wafer, the wafer was left into KOH solution to etch silicon from both sides simultaneously till the whole wafer was etched through. Since the wet etching rate was slow, about 1µm/min, etching from double sides of the wafer can reduce the process time by a half. It is recognized that there was a necking of 0.51mm /06/$ IEEE Electronic Components and Technology Conference

2 less in the through holes as shown in Fig. 2(a) due to the wet etching, which was small compared with the minimum dimension of 6mm on the top opening of the wafer and could have negligible effect on the coolant flow. It is noted that the back grinding of the cover wafer was first considered to reduce the wafer thickness and thus the etch time. This technique was found unreliable since microcracks could be formed in the cover wafer after grinding down to half of the wafer thickness ~360mm, which greatly affected the mechanical strength of the cover wafer and the bonded heat sink package. Fig. 3 shows a perspective view of the fabricated channel wafer. Due to the undercutting of the hard mask layer, the etched channel opening was 114µm instead of 100µm in the designed mask. Such a channel configuration only results in a minimal drop of 1-2% in the heat sink thermal performance. After transferring pattern onto wafer surface, the vertical trenches were etched into silicon substrate by using deep reactive ion etching (DRIE) process. Metallic pattern was also deposited onto the backside of the channel wafer for the bonding of the microchips prior to the wafer bonding. wafer bonding [3], extreme mechanical stress exists in the gold diffusion process for large-sized wafers, which degrades the bonding performance of the heat sink package as the size increases. The thermal stress due to the gold bonding process can be roughly estimated by the following equation: G L G L T( αsi α ) F = = Au (1) H H where F is the shear stress, L is the half length of wafer bonding, G is the shear modulus, T =325 o C is the process temperature difference, α Si = 2.8 ppm/ o C and α Au = 23.6 ppm/ o C are the coefficients of expansion of silicon and gold respectively, and H is the half thickness of the bonding layer. The larger the wafer bonding size is, the higher the shear stress is. The calculated value for the present case is 140MPa, which is in the proximity to the silicon strength limit of 240MPa. Silicon substrate thermal oxide/lpcvd nitride layer Start Wafer mask making Channel wafer fabrication cover wafer fabrication Through holes etching by KOH (a) Oxide layer Silicon Wafer bonding through gold diffusion/bcb Deep trench etch by DRIE Micro-channel Wafer dicing Housing bonding hydraulic tests and thermal characterization of SMHS Inlet port (b) Cover wafer BCB layer Outlet port end Channel wafer Fig. 1 Flowchart for development of the SMHS package. Wafer bonding The two wafers were required to bond together using thermal wafer bonding process to form the heat sink structure. Precise alignment of two wafers was required based on the masks on both wafers before bonding. Two wafer bonding methods, gold eutectic diffusion bonding and (BCB) bonding, were employed and evaluated. In the gold diffusion bonding, 400 Ångströms of Ti layer and 1µm of gold layer were sputtered onto the cover wafer surface first. The cover wafer was then compressed onto the channel wafer to form the eutectic bonding at 350 o C. Unlike the case for small sized (c) Fig.2 Schematic drawings of the micro-channel fabrication and bonding processes. (a) Cover wafer fabrication; (b) Channel wafer fabrication; (c) Wafer bonding through BCB. In view of the large thermal stress at the gold diffusion bonding interface, another bonding technique through the use of BCB was utilized to minimize the stress between wafers. BCB has been used successfully in wafer bonding due to its good bondability, moderate process temperature, low stress, low cost and material compatibility [4-5]. In the process, the Electronic Components and Technology Conference

3 bonding temperature was reduced and thus thermal stress was minimized. The process of BCB bonding is summarized as follows. (1) Coat the cover wafer with BCB liquid and let it spin in the coating machine for two minutes to achieve a uniform thin layer of BCB on the wafer. (2)After coating, the cover wafer with BCB is transferred to the vacuum chamber and aligned with the channel wafer. Two batches of wafer pairs were bonded based on different techniques as described below. (2a) In the first batch of wafer bonding, the two wafers were aligned and attached to each other on the bonder, and then the temperature was increased to the bonding temperature level as per the pre-set program in the bonder machine. A vacuum of 10-5 bar (1 Pa) was first achieved. Then the temperature was increased at a rate of 5 o C/min, until the bonding temperature of 250 o C was achieved. In the meantime the bonding force of 5~10 kpa was applied. (2b) In the second batch of bonding, the two wafers were aligned but separated through two spacers in between. The vacuum process was started and held for 30 minutes before the spacers were removed. After that the same temperature and pressure process as in step (2a) was conducted. The degassing process eliminated the micro voids and thus the bondability was improved significantly. The bonding layer was also found to be as thin as 5um. (3) After reaching the bonding temperature of 250 o C, it takes another 1 hour to get the BCB fully cured. (4) The temperature is then reduced to 100 o C and then the clamping force is slowly removed. The wafer is naturally cooled down. This thermal stress was reduced due to favorable material properties and process parameters such as small shear modulus and lower process temperature. (5) The wafer bonding process is repeated until the batch is completed. Only one pair of cover wafer and channel wafer can be processed at one time. It is noted that undesirable micro voids were observed in the bonding interface in Step (2a). The volatile gas from BCB was found being trapped in the bonding layer, which formed micro voids and resulted in a porous bonding layer subjected to liquid leakage. The micro voids were randomly formulated and of various morphologies depending on the locations and patterns. Semi-circular bubbles are indicated in Fig. 4, though more complicated topologies such as strips and tree branches were not uncommon. Another phenomenon due to the formation of micro voids was that the bonding thickness was increased to a visible bonding thickness of 50µm or larger. To avoid the formation of micro voids in the bonding interface between the cover wafer and the channel wafer, improved BCB bonding with additional vacuum pump-down process as described in (2b) was required to conduct before increasing the bonder temperature. Micro voids were thus eliminated due to this degassing process prior to the bonding, as is indicated in Fig. 5. An inspection under microscope showed that a hermetic bonding layer around 5µm was formed, free from micro voids and water leakage. The shear test was conducted for diced wafer pieces of 2mm x 2mm and the results are shown in Table 1. Wfin Wch Fig.3 Microchannel heat sink fabricated on the silicon through deep reactive ion etch process. Heat sink parameters: Wfin=86um, Wch=114um. Fig. 4 The photographic representation of BCB bonding layer with semicircular micro voids under a microscope. The shining spots denote the micro voids. Fluidic interconnections Fluidic interconnects were formulated through another bonding process between the cover wafer and the aluminum housing. The aluminum housing has been designed with two pairs of inlet/outlet ports for uniform distribution of fluid flow inside the microchannels. Bonding materials curing at elevated temperature exerted undesirable large thermal stress between the housing and silicon heat sink. To reduce the thermal stress, two room Electronic Components and Technology Conference

4 temperature curing materials were selected and evaluated. One was the structural epoxy adhesive and the other was the room temperature vulcanizing material RTV3140. The latter was a silicone based elastic material with excellent elongation of 420% before break. This is an advantageous parameter because the thermal stress arising from material mismatching in coefficient of expansion can be absorbed in the elastic deformation without process and operation failures. This material bondability is durable even at relatively high temperature. The shortcoming for this material is that it has a relatively long curing time, which may take 24 hours to cure with 0.5mm thickness at room temperature in open atmosphere. Either epoxy or RTV3140 can be filled in a syringe and dispensed by using Asymtek A-512 Dispensemate fluid dispenser. The housing bonding was implemented through aligning and compressing the SMHS onto the aluminum housing. A strip pattern of 4-5mm wide can be formed after the dispensing and the housing alignment. The assembled work-piece should be exposed in air for two to three days to achieve good curing and bonding quality. ~50um ~5um silicon substrate BCB bulk material (a) Micro void (b) Fig. 5 The BCB bonding layer with and without a prior pump-down process. (a) Bonding without prior degassing process: thick layer with micro voids at the interface; (b) Bonding with degassing process: thin layer with hermetic bonding. Table 1. The shear test results on 2mm x 2mm bare dies. Test parameters: shear height =700um, test speed =100um/s. Shear force at Sample breaking (kgf) Average 7.88 Since the packaging of chips on the SMHS requires another thermal solder process at 150 o C, the housing bonding strength was examined by heating up the whole heat sink package to 180 o C in a convection oven for half an hour and then letting it cool down naturally. The shear test results before and after the thermal process are given in Table 2, which shows a slight decrease for the RTV3140 housing bonding. In comparison, the epoxy was much degraded after thermal process, making it unsuitable for the present heat sink package. Table 2. Shear testing of the housing bonding materials after a thermal process at 180 o C for half an hour. Test die size: 2mmx2mm. Bonding materials RTV 3140 Shear force tested@ room temperature (kgf) Shear forces tested after thermal process (kgf) Epoxy Hydraulic and thermal characterizations In the hydraulic tests, both gear pump and chiller systems were used to provide in the pressure head in the closed-loop systems. For the pump system, the reservoir was open to the atmospheric pressure and thus the measured pressure drops were close to the pressure drops across the SMHS test section. The analytical calculation of the pressure drop across the SMHS can also be conducted based on the following equation: 2 ρu P = (4fappLfin / dh + K) (2) 2 Here P is the pressure drop across the finned structure, ρ the density of fluid, f app the apparent Fanning friction factor, L fin the fin length and d h the hydraulic diameter of the microchannel and K the loss coefficients at the inlet and outlet of the microchannels. Both f app and K can be obtained from [6]. Another test system was to make use of a chiller system to provide chilled water below the room temperature (e.g. 15 o C) to the SMHS. It is noted that the reservoir in the chiller system was a closed chamber with an internal pressure higher than the ambient. Thus there existed a large back pressure in the chiller system, which provides a challenge in the hydraulic tests of the silicon wafer based heat sinks. Both test systems were implemented and tested with the SMHSs as is shown in Fig.6. The flowrates were varied from 0.1 to 4 l/min and the inlet pressure varied from less than 1 psi to 60 psi. The test results are shown in Fig.7, together with the analytical results based on Eq. (2). Good agreement is achieved between the test results in the pump-system and the analytical results. Silicon heat sinks with gold diffusion bonding passed in the pump system test without back pressure, but failed in the Electronic Components and Technology Conference

5 chiller system at a pressure of psi due to the internal stress. On the other hand, all the BCB bonded heat sinks survived high pressure tests around 60 psi at 4 l/min, indicating the success of the heat sink package development. It is clearly seen that the development and utilization of stress-relived bonding techniques play a key role in the handling of large-sized heat sink packages. Thermal modeling is conducted for microchip mounted in the heat sink package with forced convection cooling. Due to symmetry, only part of the heat sink microchannels are modeled based on a commercial software. Since the channel dimensions were one or two order of magnitude lower than the inlet/outlet plenums, the mal-distribution of flow is neglected and the flow has been assumed uniform across the microchannels. The fabricated channel dimensions with a cross-sectional dimension of 114µm (W) x 400µm (H) are used. The inlet chilled water temperature has been set to 15 o C with 50W in each chip. Both the temperature profile and fluid flow are shown in Fig. 8. It is indicated that a maximum chip temperature of 71 o C is reached for each chip at the designed operation condition. The thermal resistance based on the maximum temperature rise over the power dissipation is obtained to be o C cm 2 /W. Pressure drop (Pa) Air vent Pump/chiller reservoir bypass valve Flow meter Pressure transducer Test section filter Fig. 6 Hydraulic testing system for the SMHS. tests w/o back pressure Analysis results w/o back pressure high bck pressure tests Flowrate (l/min) Fig. 7 Hydraulic test results for silicon microchannel heat sinks. Heat generating chips Microchannel with fluid flow Heat sink base Cover wafer plate Fig. 8 Temperature profile for chip packaged on silicon microchannel heat sinks. Conclusions In this paper, the development and characterization of the large-sized silicon microchannel heat sink packages for a large array of microelectronic chips are reported. In the fabrication of the silicon heat sinks, the microchannel wafer and the cover wafer were fabricated in deep ion reactive etching and wet etching techniques, respectively. The two wafers were then bonded through two different processes: gold diffusion bonding and BCB bonding. The BCB bonding was found to give a much reduced thermal stress due to the low process temperature and small thermal stress. The bonded wafer pair was then assembled to an aluminum housing to form the fluidic interconnections, through which the fluid is delivered into the heat sink. All the BCB bonded wafers passed the hydraulic testing conducted at a high pressure of 60 psi with the flowrate up to 4l/min. It is indicated that the development and utilization of stress-relived bonding techniques play a key role in the handling of large-sized heat sink packages. A thermal model incorporating the fabricated heat sink dimensions is developed. The computed result shows that a total power of 500W/cm 2 can be dissipated from a microchip array mounted on the silicon microchannel heat sink. Acknowledgements The authors thank Sandy Wang in conducting the wafer dicing and shear forced testing. References: 1. D. Lorenzen et al, Micro thermal management of highpower diode laser bars, IEEE Trans. Industrial Electronics 48, pp , R. Beach et al, Modular microchannel cooled heat sink for high average power laser diode arrays, IEEE J. Quantum Electronics 28, , S. M. L. Nai et al, Silicon-to-silicon wafer bonding with gold as intermediate layer, EPTC 2003, Y. S. Choi et al, Effects of temperatures on microstructures and bond strengths of Si-Si bonding using bisbenzocyclobutene, Sensors and Actuators A 108, , F. Niklaus et al, Low temperature full wafer adhesive bonding of structured wafers, Sensors and Actuators A 92, pp , H.Y. Zhang et al, Development of Liquid Cooling Techniques for Flip Chip Ball Grid Array Packages with High Flux Heat Dissipations, IEEE Trans. Comp. Packaging Technology, Vol.28, pp , Electronic Components and Technology Conference