FABRICATION OF HIGH PERFORMANCE CHIP-TO-SUBSTRATE INPUT/OUTPUT INTERCONNECTIONS

Transcription

1 FABRICATION OF HIGH PERFORMANCE CHIP-TO-SUBSTRATE INPUT/OUTPUT INTERCONNECTIONS A Thesis Presented to The Academic Faculty by Ate He In Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the School of Chemical and Biomolecular Engineering Georgia Institute of Technology May, 2007 COPYRIGHT ATE HE 2007

2 FABRICATION OF HIGH PERFORMANCE CHIP-TO-SUBSTRATE INPUT/OUTPUT INTERCONNECTIONS Approved by: Dr. Paul A. Kohl, Advisor School of Chemical and Biomolecular Engineering Georgia Institute of Technology Dr. Sue Ann Bidstrup Allen, Co-advisor School of Chemical and Biomolecular Engineering Georgia Institute of Technology Dr. Sankar Nair School of Chemical and Biomolecular Engineering Georgia Institute of Technology Dr. Matthew Realff School of Chemical and Biomolecular Engineering Georgia Institute of Technology Dr. Thomas K. Gaylord School of Electrical and Computer Engineering Georgia Institute of Technology Date Approved: April 4 th, 2007

3 ACKNOWLEDGEMENTS First, I would like to acknowledge my advisor Dr. Paul A. Kohl, without his insight and long term vision, none of this work would have been possible. I am grateful for what he has done for me. I have learned not only knowledge, but also the research habits and characters that are possessed by a great professor. Second, I wish to thank Dr. Sue Ann Bidstrup Allen, my co-advisor, for her guidance, suggestions and all her support for making my Georgia Tech experience so enjoyable. I also would like to thank my committee members, Dr. Thomas K. Gaylord, Dr. Sankar Nair, and Dr. Matthew Realff for their timely and consistent help and valuable advice. I wish to thank Daphne Perry for all her support, assistance and enthusiasm to the success of Dr. Kohl and Dr. Bidstrup s group. I would like to acknowledge Dr. Joseph Paul Jayachandran, Dr. Muhannad S. Bakir, and all my group members for their support during my Ph. D. studies. I also wish to thank Dr. Patrick Thompson from Texas Instruments, Dr. Ed Elce from Promerus LLC for their assistance and support. Special thanks are given to the Interconnect Focus Center and Semiconductor Research Corporation for funding the research. Finally, I want to thank my wife, Wenjun Ma and my parents for their endless support. I can not thank enough for the things that they have done for me. iv

4 TABLE OF CONTENTS Page ACKNOWLEDGEMENTS LIST OF FIGURES LIST OF SYMBOLS LIST OF ABBREVIATIONS iv ix xiii xv SUMMARY xvii CHAPTER 1: INTRODUCTION Introduction to flip chip packaging Summary of research goals Organization of the thesis 4 CHAPTER 2: Background Fabrication of copper pillar chip-to-substrate interconnects Thermomechanical modeling and electrical performance analysis of copper pillar chip-to-substrate interconnects Finite element modeling for copper pillar chip-to-substrate interconnects Parasitic characteristics of copper pillar chip-to-substrate interconnects Nanoimprint lithography for chip-to-substrate optical I/O interconnects 17 CHAPTER 3: fabrication of copper pillar chip-to-substrate interconnects Fabrication of hollow core polymer pillars Introduction to Avatrel 2190P Fabrication of hollow-core polymer pillars Fabrication of copper pillar chip-to-substrate interconnects Bond strength measurements of joined copper pillars Temperature effects on bond strength of copper pillars 40 v

5 3.5 Conclusions 42 CHAPTER 4: Mechanical and electrical performance analysis of copper pillar chip-tosubstrate interconnects Thermo-mechanical analysis of copper pillar chip-to-substrate interconnects GPD model for copper pillar chip-to-substrate interconnects Geometry of the GPD model Material properties Boundary conditions Model validation Design of compliant copper pillar chip-to-substrate interconnects Mesh evaluations Compliant chip-to-substrate copper pillars without polymer collars Compliant chip-to-substrate copper pillars with Avatrel collars Polyimide and SU-8 as polymer collar materials Electrical performance analysis of copper pillar chip-to-substrate interconnects Parasitics of copper pillar chip-to-substrate interconnects Parasitic inductance of chip-to-substrate copper pillar interconnects Parasitic capacitance of copper pillar chip-to-substrate interconnects Characteristic impedance of copper pillar chip-to-substrate interconnects Resistance of copper pillar chip-to-substrate interconnects Electrical performance design of copper pillars Electrical performance design of copper pillars with polymer collars Parasitics of chip-to-substrate copper pillar interconnects with polymer collars Electrical performance design of chip-to-substrate copper pillar interconnects with Avatrel collars 88 vi

6 4.3 Mechanical and electrical designs for copper pillar chip-to-substrate interconnects Mechanical and electrical design for copper pillars without polymer collars Mechanical and electrical design for copper pillars with Avatrel collars Discusses of proposed spaces for processing window and other polymers as collar materials Conclusions 93 CHAPTER 5: Nanoimprint lithography for chip-to-substrate optical INPUT/OUTPUT interconnects Determination of Optimum Imprint Step for Avatrel 2090P Stamp Fabrication and anti-adhesion treatment Optimization of imprint process parameters Combination of nanoimprint lithography and photolithography Off-angle stamp fabrication and imprint Conclusions 109 CHAPTER 6: Conclusion and future work Conclusion Fabrication of copper pillar chip-to-substrate interconnect Mechanical and electrical performance analysis of copper pillar chip-tosubstrate interconnects Nanoimprint lithography for chip-to-substrate optical interconnects Conclusion of the thesis 112 REFERENCES 113 vii

7 LIST OF TABLES Page Table 2.1 ITRS projections for high performance chips 6 Table 3.1 Bond strength of assembly techniques 40 Table 3.2 Shear force for different anneal temperatures 42 Table 4.1 ITRS projections for high performance chips 45 Table 4.2 Model material properties 46 Table 4.3 Stress results from GPD model 59 Table 4.4 Heights of compliant copper pillars 66 Table 4.5 Material properties of polymer collars 67 Table 4.6 Maximum shear stresses for 50 µm diameter, 500 µm tall copper pillars 67 Table 5.1 Mechanical Properties of Avatrel 2090P after the four primary processing steps 97 viii

8 LIST OF FIGURES Page Figure 1.1 Schematic illustrations for different chip-to-substrate/board packaging approaches. (a) Chip-to-substrate wire bonding. (b) Chip-to-substrate flip chip interconnection. (c) Chip on board flip chip interconnection. 3 Figure 2.1 Current density of 50 µm diameter power/ground I/Os projected from ITRS 6 Figure 2.2 Cross-sectional SEM of bonded Cu/Ta-Cu/Ta wafers. Cu/Ta was 300/50 nm, bonded at 400 C. 9 Figure 2.3 Intel copper pillar bumping in 65 nanometer processor technology. 9 Figure 2.4 Illustrations for 3D models. (a) 3D quarter model, (b) 3D octant model, (c) 3D slice model 14 Figure 2.5 Sea of polymer pillars. 19 Figure 2.6 Optical and dual-mode I/O interconnections through SoPP. 20 Figure 2.7 Two main nanoimprint lithography approaches. 22 Figure 3.1 Chemical structure of Avatrel 2190P 26 Figure 3.2 Hollow-core polymer pillar fabrication process flow 28 Figure 3.3 Hollow-core polymer pillars with delaminations with an exposure dose of 150 mj/cm 2 29 Figure 3.4 Hollow-core polymer pillars with crosslinked centers with an exposure dose of 600 mj/cm 2 30 Figure 3.5 SEM micrograph of hollow-core polymer pillars 30 Figure 3.6 Hollow-core polymer pillars 31 Figure 3.7 Cu pillar fabrication and chip substrate assembly process flow 33 Figure 3.8 SEM micrograph of a joined copper pillar (125 µm wide by 98 µm tall) 34 Figure 3.9 SEM micrograph of a sheared off substrate 35 Figure 3.10 Cross section of joined Cu pillars (low magnification) 36 ix

9 Figure 3.11 Cross section of joined Cu pillars (high magnification) 37 Figure 3.12 Schematic illustrations of the bond strength measurement 38 Figure 3.13 Force versus displacement curve for four 55 µm diameter copper pillar joints 39 Figure 3.14 Cracking surface on the substrate 40 Figure 4.1 GPD model in ANSYS 45 Figure 4.2 Boundary conditions of GPD model 48 Figure 4.3 Chip to board attachment through an Avatrel layer 49 Figure 4.4 Structure thermal expansions from 3D quarter model 50 Figure 4.5 Structure thermal expansions from GPD model 51 Figure 4.6 Surface curvatures from measurement and models 51 Figure 4.7 Illustration of thermal deformation 52 Figure 4.8 GPD model with mesh 53 Figure 4.9 A copper pillar with mesh 54 Figure 4.10 Refined mesh near the pillar end 54 Figure 4.11 Shear stress vs. element number on a single copper pillar 55 Figure 4.12 GPD model for copper pillar chip-to-substrate interconnects 57 Figure 4.13 Shear stress distribution on the pillar-to-substrate connection region 57 Figure 4.14 Plane-view of the shear stress distribution on the pillar to substrate interface 58 Figure 4.15 Dimension chart of copper pillar chip-to-substrate interconnects 60 Figure 4.16 Copper pillars with short polymer collars 63 Figure 4.17 The maximum shear stress on copper pillar vs. the width of polymer collars 63 Figure 4.18 The maximum shear stress on copper pillar vs. the height of polymer collars 64 Figure 4.19 Shear stress distribution on the pillar to substrate interface 65 x

10 Figure 4.20 Dimension chart for copper pillar chip-to-substrate interconnects 66 Figure 4.21 Height of compliant copper pillars with difference polymer collars 68 Figure 4.22 Chip-to-substrate power/ground I/O layout 70 Figure 4.23 Self inductance for 200 µm tall pillars 71 Figure 4.24 Single copper pillar 72 Figure 4.25 Two adjacent copper pillars 72 Figure 4.26 Circuit diagram of power/ground I/Os 73 Figure 4.27 Parasitic inductance of power/ground I/Os 76 Figure 4.28 Parasitic capacitance of two copper pillars 78 Figure 4.29 Characteristic impedance of two copper pillars 81 Figure 4.30 Copper pillars with load on chip 81 Figure 4.31 Electrical performance design of copper pillars 84 Figure 4.32 Two copper pillars with polymer collars 86 Figure 4.33 Capacitance curves for two copper pillars with polymer collars 88 Figure 4.34 Electrical performance design of copper pillars with Avatrel collars 89 Figure 4.35 Mechanical and electrical performance design of copper pillars 90 Figure 4.36 Mechanical and electrical performance design of copper pillars with Avatrel collars 91 Figure 4.37 Design and processing spaces for copper pillar chip-to-substrate interconnects 92 Figure 5.1 Load versus displacement curves for Avatrel 2090P (a) after soft bake, (b) after exposure, (c) after post exposure bake, (d) after curing 96 Figure D Profile of the stamp used for imprinting experiments 98 Figure 5.3 SEM picture of 600nm period grooves 98 Figure D Profile of the imprinted image in the polymer after soft bake at room temperature 100 Figure D Profile of the imprinted image in the polymer after soft bake at 100 C 100 xi

11 Figure D Profile of the imprinted image in the polymer with cooling followed by post exposure bake and curing 101 Figure D Profile of the imprinted image in the polymer after post bake 102 Figure 5.8 SEM of the pillar produced without protection layer 103 Figure 5.9 Fabrication flow of imprint lithography with a photo-definition process 105 Figure 5.10 SEM of the pillar produced with SOG protection layer 106 Figure 5.11 SEM of the pillar produced with SOG protection layer 107 Figure 5.12 Silicon stamp with cute angle grooves 108 Figure 5.13 Imprinted polymer structures 109 xii

12 LIST OF SYMBOLS V L I t V dd τ F voltage noise, V inductance, H or length, m current, A time, s supply voltage, V shear stress, Pa force, N A cross sectional area or area, m 2 T E γ H H D d V Z R ω temperature, K elastic modulus, Pa Poisson s ratio or thermal deformation strain thermal deformation, m height, m diameter, m pitch or distance, m voltage, V impedance, Ω resistance, Ω angular frequency, Hz j imaginary unit, square root of -1 M f C mutual inductance, H signal frequency, Hz capacitance, F xiii

13 G ε 0 ε r conductance, S permittivity of vacuum relative dielectric constant (relative permittivity) µ 0 permeability of vacuum µ r relative permeability ε R s Z 0 σ δ s Z L β ρ D S P E r h imaginary part of the complex permittivity surface resistance, Ω characteristic impedance, Ω conductivity, S/m skin depth, m load impedance, Ω phase constant, rad/m electrical resistivity, Ωm infinite small distance, m stiffness, N/m force, N reduced modulus, Pa displacement, m xiv

14 LIST OF ABBREVIATIONS IC I/O ITRS BGA RF COB GPD P/G SIP CTE SEM BT SAB integrate circuit input/output International Technology Roadmap for Semiconductors ball grid array radio frequency chip on board generalized plane deformation power/ground system-in-package coefficient of thermal expansion scanning electron micrograph Bismaleimide Triazine surface activated bonding FR4 Flame Resistant 4 FEA FEM SSN EMI SoPP NIL SFIL UV finite element analysis Finite element model simultaneous switching noise electromagnetic-interference sea of polymer pillars nanoimprint lithography step and flash imprint lithography ultraviolet xv

15 LLC DC PECVD RIE EDTA ILD PMMA SOG BOE limited liability company direct current plasma enhanced chemical vapor deposition reactive ion etching ethylenediaminetetraacetic acid interlayer dielectrics polymethylmethacrylate spin-on-glass buffered oxide etch xvi

16 SUMMARY Novel fabrication technologies for high performance electrical and optical chipto-substrate input/output (I/O) interconnections were developed. This research is driven by the long term performance and integration requirements of high performance chip-tosubstrate I/Os, as well as the package reliability demands from semiconductor manufacturing. An electroless copper plating and annealing process was developed to join copper structures to achieve chip-to-substrate assembly by all copper pillar interconnects. The developed copper pillar interconnects provide much higher current carrying capability for chip-to-substrate power/ground input/output distributions and have low electrical parasitic characteristics for high frequency electrical signal communications. This copper bonding process also demonstrates the capability to compensate for misalignments and height variations of bonded structures. This capability is critical for semiconductor manufacturing, since surface curvature of chips and substrates is inevitable. A finite element generalized plane deformation model was employed to design fully compliant copper pillars to eliminate the need of underfill. Electrical parasitics of copper pillar chip-to-substrate interconnects were studied by the derived formulas for low parasitic requirements. An optimized dimension space for all the criteria was provided on the pillar dimension chart. A novel nanoimprint lithography was developed to combine with photolithography in one process to create high quality features on a macrostructure for chip-to-substrate optical I/O applications. This fabrication process also demonstrated the capability to produce off-angle complex structures. xvii

17 CHAPTER 1: INTRODUCTION 1.1 Introduction to flip chip packaging Performance improvement has dominated research efforts in the microelectronics industry since the first demonstration of the integrated circuit (IC) in 1958 [ ]. Microprocessors clock frequency has increased at an alarming rate due to device scaling. The number of transistors on a chip doubled annually until the late 1970s, when it slowed down to about every two years [1.4]. This theorem, known as Moore s law, continues today [1.5]. Transistor scaling improves performance by increasing the operating frequency, increasing integration capacity to realize complex architectures, and reducing energy consumed per logic operation [1.6]. Also, interconnect scaling was used extensively to reduce cost; however, due to the exponentially increase in chip operating frequency and functionalities, especially in multi-core processor and stacking chip architectures, the current supply to the chip and data communication between the chip and the substrate has increased dramatically. The performance of the chip-to-substrate interconnects started to impose primary limitations to the system performance, signal integrity and power dissipation [ ]. The stringent input/output (I/O) requirements from the International Technology Roadmap for Semiconductors (ITRS) demand the development of new and cost effective high performance chip-to-substrate integrated high frequency signals, low parasitic power/ground and high bandwidth optical I/O approaches [1.12]. Chip-to-substrate interconnects provide power, electrical contacts and mechanical contacts between the chip and the substrate. The two most popular chip assembly 1

18 schemes today, wire bonding and flip chip bonding are illustrated in Figure 1.1 (a) and (b), respectively [ ]. The flip chip configuration is generally more valuable than wire bonding and provides several advantages; (i) The ball grid array (BGA) in the flip chip configuration has a much higher I/O density over peripheral wire bonding. (ii) The electrical connections in the flip chip configuration are considerably shorter than the wires, giving lower interconnect latency and low parasitic characteristics [1.15]. (iii) Chip-to-substrate radio frequency (RF) and optical I/Os can be easily integrated through the flip chip configuration. (iv) The flip chip configuration offers better thermal characteristics since an external heat sink can be directly added above the chip to remove heat. Due to its overwhelming benefits, the flip chip configuration has been widely used in high performance systems, while the applications of wire bonding are limited to low profile chips. Flip chip assembly either uses solder bumps to connect both the chip to the substrate and the substrate to the board in a conventional scheme as shown in Figure 1.1 (b) or directly connects the chip to the board called chip on board (COB) as shown in Figure 1.1 (c). Comparing these two flip chip schemes, COB is a process for attaching the chip directly onto the printed circuit board. It requires minimum board space and the direct interconnection between die and board improves electrical performance [ ]. With the push towards miniaturization in electronic products, applications of COB are expected to increase significantly in the near future [1.20]. In this thesis, the developed higher performance chip-to-substrate power/ ground, electrical signal and optical I/O interconnects are focused in flip chip configuration. 2

19 Figure 1.1 Schematic illustrations for different chip-to-substrate/board packaging approaches. (a) Chip-to-substrate wire bonding. (b) Chip-to-substrate flip chip interconnection. (c) Chip on board flip chip interconnection. 1.2 Summary of research goals To date, solder flip chip techniques have been adequate for use as chip-tosubstrate interconnects; however, it is clear that solder-based materials are not poised to meet the electrical performance and process requirements of tomorrow. It has been suggested that copper will start to replace solders as the material of choice for chip-tosubstrate interconnections; however, all current copper bonding techniques are incompatible with low cost organic board materials. As a result, the primary objective of this research is to develop a novel fabrication process to obtain compliant high performance chip-to-substrate power/ground and high frequency signal copper pillar 3

20 interconnects that fulfill the stringent I/O requirements from ITRS to support the historic rate of progress in semiconductor technology. 1.3 Organization of the thesis Chapter 2: In this chapter, background and motivation for copper pillar chip-tosubstrate interconnect techniques are introduced. The background of the thermomechanical reliability and electrical performance of chip-to-substrate package is discussed. Nanoimprint lithography is also introduced for optical interconnect applications. Chapter 3: In this chapter, a novel copper bonding technique is described to obtain pure copper chip-to-substrate connections. The copper bond strength and processing temperatures have been investigated. Chapter 4: In this chapter, a finite element GPD model is used to design fully compliant copper pillar chip-to-substrate interconnects, eliminating the need for underfill. The parasitics of compliant copper pillars have been studied. Chapter 5: In this chapter, a novel nanoimprint fabrication technique is described to produce nanoscale grating structures on top of microscale structures by a sequence process on a single polymer film for chip-to-substrate optical interconnect applications. Chapter 6: In this chapter, the results and contributions of this research is discussed. 4

21 CHAPTER 2: BACKGROUND 2.1 Fabrication of copper pillar chip-to-substrate interconnects Solder is widely used in the electronics industry for attaching components to substrates or printed circuit boards in a flip-chip configuration, serving as the chip-tosubstrate signal and power/ground (P/G) I/O interconnect material. The melting point of solder, and its ability to adjust to lateral (self-alignment) and vertical (nonplanar) surfaces, make it valuable in BGA packages and epoxy substrates [2.1, 2.2]. However, solder has modest electrical properties and copper-tin intermetallics have poor mechanical properties [ ]. The electromigration resistance of solder materials is low, which limits their maximum allowable current densities to around 10 4 A/cm 2 [2.4, 2.7]. Table 2.1 lists the ITRS projections for high performance chips. The chip supply current (Row 3) increases with decreasing pad pitch (Row 6). For the 50 µm diameter P/G I/O interconnects, the projected I/O current density is plotted in Figure 2.1, which was calculated by considering anticipated number of power and ground I/O interconnects in ITRS [2.8]. It is clear from Figure 2.1 that the required current density of the power I/O interconnects is rapidly approaching the physical limitation of solder materials, and it is expected to surpass it in The current supply limitation of solder materials is severely challenged by current 3D chip stacking technology, which stacks multi-chips to a single substrate to realize a high density and high performance system-in-package (SIP) [ ]. The chip-to-substrate interconnects are required to be able to supply the power needed for all the chips in the stacking package. 5

22 Table 2.1 ITRS projections for high performance chips Year Node MPU (Microprocessor unit) Current, A MPU Power, W Chip-to-Board, GHz Pad Pitch, flip-chip, µm V dd chip supply voltage, V Current density (A/cm2) Figure 2.1 Current density of 50 µm diameter power/ground I/Os projected from ITRS Year Solder connections are also limited to an aspect ratio (height : width) of roughly unity such that high profile contacts (large chip-to-substrate stand-off distances) are very difficult to obtain by solder bumps. High aspect ratio and non-spherical connections are 6

23 needed for high I/O density and mechanical compliance for IC-to-substrate/board connections. Also, solders have poor mechanical strength [2.5, 2.12]. For example, tin and other solder-containing metals form brittle intermetallics with copper which can fracture under high shear and normal stresses and underfill is typically required between the chip and substrate to support the solder connections. Underfill distributes the thermomechanical stresses, originating from the coefficient of thermal expansion (CTE) mismatch between the different materials [ ]. Organic substrates are most often CTE-matched to copper (ca ppm/ o C), and silicon has a CTE of about 2.5 ppm/ o C. An all-copper connection technology between the copper wiring on the IC to the copper wiring on the substrate would provide high conductivity electrical connections, excellent resistance to electromigration, and avoid the formation of brittle intermetallics [2.12]. Further, if the copper connections were formed with a high aspect ratio, mechanical compliance could be designed into the connections so that no underfill would be needed. The elimination of underfill would improve the electrical environment (lower permittivity and no dielectric loss) and potentially lower the cost. Copper wafer bonding (copper-to-copper fusion) can be used to produce allcopper connections. Figure 2.2 shows the scanning electron micrograph (SEM) of a bonded Cu-Cu cross-section by Reif [2.15]. The critical parameters of copper-to-copper bonding involve (i) the method of achieving intimate contact between two clean, purecopper surfaces, and (ii) the bonding temperature, pressure, and cleaning conditions. In order to obtain adequate bonding between two copper surfaces, high temperature annealing (350 C to 450 C) of clean copper surfaces under pressure is required [2.15, 2.16], where the higher end of the temperature range is preferred to create seamless 7

24 copper joints. However, this temperature range is too high for cost-effective organic boards or substrates. Epoxy or Bismaleimide Triazine (BT) boards can not be exposed to temperature exceeding ca. 250 C without experiencing some degradation. If the copper wafer bonding process were used for I/O, there would also have to be excellent alignment between the two parts so that the contact area between the top pads being joined is as large as the pad area since the copper does not flow and readjust like solder. Finally, direct copper-to-copper wafer bonding requires either flat surfaces, or surfaces that can withstand high pressure to make them flat during bonding since there is no mechanism to account for vertical height variations. Surface activated bonding (SAB) has been used for room temperature copper-copper bonding [2.17]. The low bonding temperature in the SAB process was achieved by employing the argon plasma to energize two extremely flat and clean copper surfaces and then push two surfaces together under an ultra high vacuum environment. However, the reported bonding strength of above 6.47 MPa is far below the yield stress of copper [2.17, 2.18]. Over 70 MPa shear strength from SAB has been reported after introducing an aging step of 500 hours at 250 C or 1000 hours at 150 C [2.19]. Similar to the copper wafer bonding, there is no tolerance for spatial misalignments. Solder, on the other hand, can be easily distorted during reflow to elongate or flatten, as needed. One practical interconnect structure currently used has a reflowable solder cap on the copper pillar to improve the I/O density [2.20]. As shown in Figure 2.3, Intel has used copper pillar bumping in the 65 nm processor technology [2.21]. The solder cap avoided the high temperature copper-to-copper bonding step; however, the electrical and mechanical limitations of solder still exist. 8

25 Figure 2.2 Cross-sectional SEM of bonded Cu/Ta-Cu/Ta wafers. Cu/Ta was 300/50 nm, bonded at 400 C. Figure 2.3 Intel copper pillar bumping in 65 nanometer processor technology. 9

26 Accordingly, there is a need for methods to fabricate interconnect structures that provide simple processing to produce interconnects having improved electrical and mechanical properties with fewer steps and reduced costs. There is also a need for such structures and methods capable of compensating for non-planar surfaces encountered during interconnect fabrication. In this thesis, an electroless copper plating and annealing process has been developed to produce all-copper chip-to-substrate interconnections. Copper pillar interconnects were fabricated and electrolessly joined at ambient temperature. An additional annealing step was used to increase the mechanical strength of the joint copper pillars. The atomic mixing of the copper pillars during the plating process allowed for a reduction in annealing temperature. The annealing temperature was lower to 250 C, which is compatible with epoxy boards. The measured bond strength was 148 MPa. 2.2 Thermomechanical modeling and electrical performance analysis of copper pillar chip-to-substrate interconnects Finite element modeling for copper pillar chip-to-substrate interconnects Reliability of chip-to-substrate interconnects is a major concern in the microelectronic industry. The CTE mismatch between the silicon chip (2.5 ppm/ C) and the substrate (4-10 ppm/ C for ceramics and ppm/ C for organic Flame Resistant 4 (FR4)/BT board) causes deformation between the chip and substrate, which generates strains and stresses on the interconnect structures [2.22, 2.23]. Thermomechanical failures will occur when the individual shear stress exceeds the strength of the interconnect joint or when the accumulation of the inelastic strain due to cyclic loadings exceeds the material fatigue strength [2.24]. 10

27 For current chip-to-substrate solder joints, temperature fluctuations caused by either power transients or environmental changes, along with the resulting CTE mismatch between the various packaging materials, results in time and temperature dependent creep deformation of solder. This deformation accumulates with repeated cycling and ultimately causes solder joint cracking and interconnect failure. To minimize development costs and maximize reliability performance, finite element analysis (FEA) has been widely used to evaluate the accumulated inelastic strain of solder bumps. FEA requires empirical fatigue models to predict fatigue life of solder joints [ ]. In order to improve the fatigue life of solder joints, stacked solder spheres, stretched solder columns and copper pillar supported solder joints have been studied [ ]. All the thermo-mechanical analysis of packaging reliability must involve solder materials due to the fabrication challenges of all copper chip-to-substrate interconnects described in the previous section. This thesis, for the first time, uses stress criteria to design compliant chip-to-substrate copper pillar interconnects. Comparing with chip-to-substrate solder connections, copper pillar interconnects are preferred for various thermomechanical reasons. First, copper is much stronger than solder materials. The yield strength of electrodeposited copper is 225 MPa, which is much higher than the ultimate strength of solders [ ]. Second, copper has typical elastic-plastic stress-strain characteristics. The elastic deformation in a thermal cycling will return to its neutral position. Undesired plastic deformations will only generate when the stress exceeds the yield stress of copper. Third, copper is a ductile material. Copper pillars will experience a large deformation period before cracking occurs. This further deformation will reduce the stress and prevent mechanical failures under severe 11

28 conditions [2.36]. Another value of copper pillar interconnects is that the single metal copper avoids forming brittle tin-copper intermetallics. Finally, unlike solder bumps, copper pillars are flexible in aspect ratio [2.37]. As the I/O density increases, the standoff distance of solder joints has to be reduced with decreasing diameter and, as a consequence, the effective dispensing of underfill between chip and substrate may become extremely difficult. The developed fabrication process of copper pillar interconnects makes it possible to maintain or even increase the standoff distance with the reduced diameters. The increased aspect ratio of copper pillars can also reduce the shear stress generated from the thermomechanical deformations. Also, underfill is no longer necessary for copper pillar interconnect packaging, which will improve the electrical performance since underfill materials usually have high dielectric loss and large parasitic characteristics [ ]. Finite element models (FEM) in FEA can be either 1D, 2D or 3D, modeled by lines, shapes or surfaces, respectively. For the stress analysis of chip-to-substrate interconnects discussed in this thesis, only 3D models can be used since stress is a tensor that has both surface components and normal (vertical to the surface) components. As illustrated in Figure 2.4, the 3D quarter model, 3D octant model and 3D slice model are widely used in the microelectronic industry to investigate the thermal performance and thermo-mechanical behavior of IC packages [ ]. The boundary conditions in 3D quarter and octant models are either structure exterior surfaces or symmetry planes. Therefore, the simulation results from 3D quarter and octant models are most accurate, since no simplified assumptions are made to the boundary conditions [2.44]. However, the 3D quarter and octant models require large memory space and calculation time. Due 12

29 to the dimension difference between the micron-scale copper pillars and the millimeterscale chip and board, stress modeling of copper pillars requires a large amount of elements to obtain converged results, especially at the large stress gradient regions near the pillar to substrate interfaces. 3D quarter and octant models can only be used in small I/O number and small chip area cases. A technique called submodeling was developed to reduce memory space needed for 3D models [2.45, 2.46]. The simulation of submodeling consists of two steps. First, a 3D quarter or octant model consisting of all the structures is calculated with a coarse mesh. Although the results of interest on small structures are not converged, the deformations on large structures far from the regions of interest are converged. Then, the submodel contains only the regions of interest and is analyzed with the boundary conditions transferred from the global model. A much finer mesh can be used in the submodel, since the physical dimensions are much smaller. Accurate results are obtained from submodel simulations. Although less memory is used by submodeling technique, the global model is still limited by the element number that can be calculated. Therefore, for high I/O density, large chip area and high aspect ratio pillar chip-tosubstrate I/O situations, 3D slice model is the only choice. 13

30 (a) (c) Figure 2.4 Illustrations for 3D models. (a) 3D quarter model, (b) 3D octant model, (c) 3D slice model 14

31 As shown in Figure 2.4 (c), instead of simulating a large area of the package, which would be required in both 3D quarter and octant models, a 3D slice model only considers the diagonal slice of the package that passes through the thickness of the package assembly, since the maximum strain and stress will always be generate at the corners. The diagonal slice captures all major components as well as a full set of chip-tosubstrate interconnects. The use of a slice model involves a choice on the part of the analyst on the boundary constraints to be applied at the slice plane. The nodes on the two slice surfaces are coupled, so that all the nodes on the same plane have identical deformation in y-direction (normal to the surface) to meet the generalized plane deformation (GPD) constraints. The plane is neither a free surface nor a true symmetry plane. This has the effect that the slice plane is free to move in the y-direction, but the surface is required to remain planar. From its boundary constrains, 3D slice model is also called GPD model [2.44, ]. GPD model is a tradeoff in terms of accuracy and computational complexity, though the reliability analysis of solder packages shows only a 6% difference between GPD model and 3D octant model [2.44]. In this thesis, a GPD model was used to design compliant copper pillar chip-to-substrate interconnects that can withstand the thermo-mechanical deformations of the package without the need of underfill materials Parasitic characteristics of copper pillar chip-to-substrate interconnects Parasitics associated with integrated circuit packaging are beginning to affect the performance of the integrated circuit with the rise in operating frequencies. In the past, the electrical role of the package was limited to provide an electrical connection between the chip and other functional components on the system board. However, as the switching 15

32 rates of the transistors approach a few pico-seconds and as the supply voltage scales down to less than 1 V, the electrical design of the package is becoming more challenging. Package parasitics will decrease the system performance by introducing signal delays, signal and power noises, and power losses. The package has to be designed to achieve low parastics to enable high speed communication and computation [ ]. The parasitic inductance (L), parasitic capacitance (C) and resistance (R) can be used to judge the electrical performance of packages. For chip-to-substrate power/ground I/Os, the IR voltage drop and simultaneous switching noise (SSN) are two main issues in distributing power to the chip. The IR drop is due to the voltage drop on the resistances of the power distribution networks. The resistances of the chip-to-substrate I/Os are negligible compared to the resistance of an on chip power distribution network; therefore, the IR voltage drop on chip-to-substrate power I/Os is very small [2.53]. Simultaneous switching noise is induced by the current change that passes the power distribution network, which is mainly due to the I/O parasitic inductance [ ]. SSN can cause problems in signal timing and integrity, resulting in false switching logic circuits [2.57, 2.58]. The SSN can be expressed by Equation 2.1. di V = L (2.1) dt Where I is the current, t is time and L is the parasitic inductance or loop inductance of the chip-to-substrate I/Os. As predicted in Table 2.1, the current supply to the chip will increase over time and, as a result, the di/dt term increases as well. The decreasing supply voltage V dd reduces the noise margin V. Therefore, the parasitic inductance of the power/ground I/Os, L needs to be kept as low as possible in order to maintain signal integrity. The parasitic inductance is determined by the physical geometry of the 16

33 power/ground interconnect, loop distance and properties of the dielectric materials in between I/Os. In this thesis, the parasitic inductance of copper pillar chip-to-substrate power/ground I/O interconnects was derived based on formulas of self and mutual inductances for pillar structures. The formula was used to investigate the parasitic inductance of the designed compliant copper pillar interconnects. The parasitic capacitance will degrade signal integrity by crosstalk between adjacent interconnects and causes signal delay that is proportional to the RC product. Although the absolute values of the parasitic capacitance and the resistance of chip-tosubstrate I/Os are negligible comparing with on-chip interconnects, the overall system performance will get benefit from lower off-chip RC delays [2.59]. The characteristic impedance of the chip-to-substrate interconnects also needs to be addressed since the mismatch of characteristic impedance between the connections will induce reflection loss for high frequency communications. The resistance, parasitic capacitance and characteristic impedance of compliant copper pillar chip-to-substrate interconnects were studied in this thesis. 2.3 Nanoimprint lithography for chip-to-substrate optical I/O interconnects With the continued growth in the integration density of transistors and clock frequency of microprocessors, the aggregate communication frequency and bandwidth required between chip and substrate is increasing sharply. The ITRS projects the chip to board communication will reach 9.7 GHz by 2010 and over 50 GHz after 2018 [2.8, ]. Metal-based communications between chips and subsystems has very limited bandwidth, which results in limited communication speed [2.60, 2.63]. Optical interconnect technology, in the form of fiberoptics, has been used for decades in long- 17

34 distance applications. Now, optical interconnects are showing promise for ultra-short transmission distance applications due to its ability to support a far higher bandwidth than the metal wires that now carry data from board to board, chip to substrate, and component to component within a chip [ ]. Besides the high bandwidth, optical interconnects have also demonstrated other merits, namely, the potential of lowering the energy consumed, a higher I/O density, a lower electromagnetic-interference (EMI) and a reduced size and weight [ ]. Still, optical interconnect technology in the ultrashort applications poses its own cost problems. The technology depends largely on components made of gallium arsenide and germanium, which are more several times expensive than silicon. There are two optical interconnection techniques that have been developed in order to address chip-to-substrate communications: free-space optics and guided wave optical interconnections using optical fiber or integrated optical waveguides [2.69, 2.74]. Comparing with guided optical waveguides, free-space interconnects require free spaces and near perfect alignment. For current solder packages, underfill materials are needed to occupy the space between the chip and the substrate; it is also quite challenging to fabricate controlled free spaces, and the perfect alignments are impossible to maintain when temperature changes. Therefore, only optical waveguides are suitable for practical chip-to-substrate packages. As shown in Figure 2.5, the so-called sea of polymer pillars (SoPP) has been developed for chip-to-substrate/board optical communications [2.75, 2.76]. SoPP has all the favorable optical interconnect characteristics with the additional desirable features of low cost, high tolerance to CTE mismatches, accommodation of wafer-level testing, and 18

35 low-temperature processing compatibility with semiconductor manufacturing [ ]. The connections of chip-to-board polymer pillars are illustrated in Figure 2.6. Polymer pillars fabricated above optical elements (detectors, sources, mirrors, gratings, etc.) were aligned and connected to the polymer sockets fabricated from the opposite side. Diffractive grating or mirror structures on the polymer pillar tip are used to facilitate surface-normal optical coupling between the polymer pillars and the corresponding board-level optical planar waveguides [2.78]. In this thesis, a novel nanoimprint fabrication method has been developed to obtain the nanoscale grating structures on top of microscale polymer pillars in a sequential process on a single polymer film. Figure 2.5 Sea of polymer pillars. 19

36 Figure 2.6 Optical and dual-mode I/O interconnections through SoPP. Nanoimprint lithography, proposed in 1995, is one of the most promising technologies for next generation lithography, which creates a resist relief pattern by deforming the resist physical shape with embossing, rather than by modifying the resist chemical structure with radiation [2.80]. Nanoimprint lithography is a simple process with low cost, high throughput and high resolution [ ]. The key enhancement offered by the nanoimprint process is its low cost, where the greatest capital cost associated with chip fabrication is the optical lithography tool. In order to achieve nanometer scale resolution, optical lithography requires high powered excimer lasers, immense stacks of precision ground lens elements and the finely tailored photoresists designed for both resolution and sensitivity at a given wavelength [2.85, 2.86]. There is no need for the intensive light sources, expensive optical lenses and costly materials in 20

37 nanoimprint lithography. Besides its simple process and low cost, the resolution of nanoimprint can reach sub 10 nanometer [2.87, 2.88]. There are two main approaches to transfer patterns via nanoimprint technologies from a stamp (mold) to a polymer, shown in Figure 2.7. First, nanoimprint lithography (NIL) presses a stamp into a thermoplastic transfer layer at a temperature near or above the glass transition temperature of the polymer. This transfer layer is readily deformed at the elevated temperature and the imprinted pattern becomes rigid after the transfer layer is cooled down below its glass transition temperature. After the separation between the stamp and the transfer layer, an additional etching step is needed to transfer the pattern from the transfer layer to the desired material [2.80]. On the other hand, step and flash imprint lithography (SFIL) uses a photosensitive transfer layer. When the polymer is imprinted, it is also exposed to ultraviolet light causing the polymer to become more rigid to hold the imprinted pattern. An etching step is also needed to transfer the patterns [2.81]. In both cases, the imprinted polymer retains a physical relief feature that must undergo secondary processes to result in a material with a single pattern type. Due to the limitations of etching, complex structures in the target polymer cannot yet be easily obtained through one imprint step and these methods rely on permanent property changes of the polymer to achieve high resolution. Therefore, multi-level patterns are difficult to produce by these imprint approaches. 21

38 Figure 2.7 Two main nanoimprint lithography approaches. In this research, a novel nanoimprint fabrication method has been developed. The unique feature is that, without embossing on a temporary resist layer, the stamp is pressed directly into the target photosensitive polymer at optimized conditions. Off-angle (nonvertical) and other complex structures can be transferred into the target polymer by one single imprint step. Furthermore, without employing high temperature or UV light, the imprinted pattern can be transferred from the stamp to the target material while retaining the photo-definable property of the polymer. During a subsequent step, the photosensitive nature of the polymer can be used to produce the second-level structure. A 93 µm tall polymer pillar of Avatrel 2090P with a 500 nm wide diffraction grating feature on the top 22

39 surface has been obtained to demonstrate the capability to produce high aspect ratio structures for optical interconnect applications. 23

40 CHAPTER 3: FABRICATION OF COPPER PILLAR CHIP-TO- SUBSTRATE INTERCONNECTS This chapter describes a novel technique to fabricate all-copper chip-to-substrate interconnects. High aspect ratio polymer molds for electroplating were formed using a photodefinable polymer on both the chip and the substrate surfaces. Copper pillars were fabricated by electroplating metal in the polymer molds. The chip-to-substrate all-copper connections were formed by joining the two pillars with electroless copper plating followed by an annealing process. This copper-to-copper bonding of high aspect ratio pillars does not require the use of solder or other non-copper metals. Mechanical shear force measurements were used to characterize the bonding process as a function of annealing conditions. Excellent bond strength of the electrolessly joined pillars was achieved with a 250 C anneal, with the bond strength of the copper pillar interconnects exceeding 148 MPa. High aspect ratio pillars can provide mechanical compliance, and the electroless fabrication method compensates for pillar misalignment and non-planarity of the bonded surfaces. This fabrication method achieved two critical benefits over other copper bonding technologies. First, the process temperature has been reduced to 250 C for high quality copper joints, which is 100 C lower than that needed through copper wafer bonding [ ]. Second, the developed technique enables a copper joining process with tolerances to structure height variations and misalignments. 3.1 Fabrication of hollow core polymer pillars Introduction to Avatrel 2190P 24

41 Avatrel 2190P developed by Promerus LLC (Brecksville, OH) was chosen for producing hollow core polymer pillars as copper pillar electroplating molds due to its excellent photodefinition capability, high resistance to the chemicals used in the process and low dielectric constant. Avatrel 2190P is poly[decylnorbornene-coepoxidenorbornene] copolymer with 30 mol% of the monomer containing epoxy functional groups and 70 mol% of the monomer containing decyl side groups. The solvent used in Avatrel 2190P is decalin. The chemical structure of Avatrel is shown in Figure 3.1. The decyl side groups improve the intrachain mobility, resulting in improved mechanical properties. Epoxy side groups are introduced to provide crosslinkable sites, resulting in improvements in chemical, thermal and electrical properties [ ]. Avatrel 2190P has a dielectric constant of 2.5 and a loss tangent of over the range of 1 MHz to 1.3 GHz. The low dielectric constant reduces parasitics and cross-talk among interconnects and the low loss tangent minimizes the dielectric loss for high frequency signal communications [3.7]. Avatrel 2190P has a high resistance to both strong acids (electroplating solution) and strong bases (electroless plating solution), allowing it to survive all the process steps in the fabrication process. Besides the above merits, Avatrel 2190P also has a low moisture absorption (less than 0.1 weight percent) and a low modulus of 0.5 GPa, which make it an excellent candidate for package applications. Furthermore, Avatrel has a high glass transmission temperature 330 C (thermally stable for high temperature processing), good adhesion to metals, low shrinkage during curing and a large process window [3.5, ]. 25

42 O O CH 3 (CH 2 ) 9 Figure 3.1 Chemical structure of Avatrel 2190P Fabrication of hollow-core polymer pillars The fabrication process for hollow core polymer pillars is shown in Figure 3.2. A seed layer of Ti/Cu/Ti (30 nm/1000 nm/10 nm) was first DC sputtered on a bare silicon wafer. The first layer of Ti was used to improve the adhesion between Cu and the silicon wafer. Additional samples were fabricated with Cr in place of the Ti to further improve adhesion to the wafer. The Cu layer served as the seed layer for subsequent copper electroplating and the second Ti layer was used to improve the adhesion between Cu and the top SiO 2 passivation layer. Without this Ti layer, the copper electroplating solution will penetrate between the copper and SiO 2 through the open copper surfaces causing the SiO 2 layer to crack. After the metal deposition, a 1.5 µm layer of SiO 2 was deposited on top of the titanium surface by plasma enhanced chemical vapor deposition (PECVD) at 250 C. Microposit SC1813 photoresist (Shipley Corporation) was spun on the SiO 2 surface. After photo-patterning the photoresist layer, buffered oxide etch (BOE) was used to etch the SiO 2 and Ti layers in the exposed areas. The remaining photoresist was removed with an acetone rinse. Next, a thick layer of Avatrel 2190P polymer was spun 26

43 on top of the patterned SiO 2 layer. The spin rate was 500 rpm for 10 seconds followed by 1000 rpm for 60 seconds. The spin speed determines the polymer film thickness. Low spin speeds produce thicker polymer films, but any spin speed lower than 800 rpm will produce non-uniform films. After a 40 minute softbake on a hotplate at 100 C, a 250 mj/cm 2 dose UV exposure was performed with 365 nm irradiation. A 20 min. post exposure bake at 100 C was followed by ultrasonic developing to produce high aspect ratio, hollow-core polymer plating molds. A 5-minute oxygen reactive ion etching (RIE) was necessary to clean residue left from the development. The primary concern in this process is the cleanness of the hollow cores. Any residue left at the bottom of the hollow cores will prevent the formation of copper pillars during the following electroplating step and is very difficult to remove. The development technique and exposure dose both factor prominently in the cleanness of the high aspect ratio hollow cores. There are four development methods that are normally employed: spray, puddle, immersion and ultrasonic bath developments. A previous study on Avatrel polymers indicates that spray development provides excellent results for solid structures because of the spray agitation and the continuous use of fresh developer [3.7]. However, the spray method could not provide the developer replenishment needed for hollow-core structure developments. Ultrasonic bath development is a better choice because of the high energy agitation it provides. This agitation helps replenish the developer over the entire length of the structures. Ultrasonic development also improves the pattern uniformity across the wafer. However, the adhesion between the polymer and the substrate needs to be strong for ultrasonic development due to its high energy agitations. In order to improve the adhesion, a larger exposure dose is needed. If the irradiation dose is not large enough to reach the bottom of the polymer layer, delamination will occur at the Avatrel-SiO 2 interface during ultrasonic development. 27

44 Si wafer Ti/Cu/Ti and SiO 2 deposition SiO 2 Ti/Cu/Ti SiO 2 layer patterning Avatrel 2190P coating Avatrel 2190P patterning Figure 3.2 Hollow-core polymer pillar fabrication process flow Figure 3.3 is a microscope picture of 50 µm tall hollow-core polymer pillars with a 3:1 aspect ratio following an exposure dose of 150 mj/cm 2 and ultrasonic bath development. The internal hollow space in these structures, which is surrounded by the polymer ring, is also very sensitive to exposure dose. A dose that is too large will cause partial crosslinking inside the space at the bottom of the hollow-core. Figure 3.4 shows the development results for a higher exposure dose of 600 mj/cm 2. Although the outer 28

45 surface was fine, the internal space was already crosslinked at this dose. It is difficult to etch away this crosslinked polymer residue at the hollow-core bottom, so the optimum exposure dose is the minimum required for adhesion, which is 230 mj/cm 2 to 280 mj/cm 2 for 50 µm tall hollow-core polymer pillars. Figure 3.5 shows a SEM image of hollowcore polymer pillars with a 250 mj/cm 2 exposure dose. Hollow-core structure fabrications limit not only the exposure dose range but also the aspect ratio that can be obtained from photodefinition. The highest aspect ratio for the hollow-core polymer pillars that can be fabricated is 3.5:1, while the aspect ratio of solid polymer pillars can reach over 6:1 [3.8]. Figure 3.6 is a microscope picture following the complete fabrication process depicted in Figure 3.2. The brighter color center holes are the completely uncovered copper surface. The grey field color comes from the Ti layer covered by a layer of SiO 2. The polymer becomes darker due to the surface oxidation during oxygen reactive ion etching. Delaminated pillars Figure 3.3 Hollow-core polymer pillars with delaminations with an exposure dose of 150 mj/cm 2 29

46 Crosslinked centers Figure 3.4 Hollow-core polymer pillars with crosslinked centers with an exposure dose of 600 mj/cm 2 Figure 3.5 SEM micrograph of hollow-core polymer pillars 30

47 Figure 3.6 Hollow-core polymer pillars 3.2 Fabrication of copper pillar chip-to-substrate interconnects The second set of fabrication steps is used to produce copper pillars and achieve chip-to-substrate interconnects. The process flow is depicted in Figure 3.7. Once the hollow-core polymer pillars are obtained, copper electroplating is used to fill the polymer cavities and produce copper pillars. The electroplating solution contained 0.5 M H 2 SO 4, 0.5 M CuSO 4, 0.25 M brightener, and 0.25 M carrier and electroplating was performed at 2 ma constant current for 20 hrs (current density of 1 ma/cm 2 ). The Cu pillars are electroplated about 10 µm over the polymer molds. This extra height provides the necessary spacing for the subsequent electroless copper plating solution to flow properly. The two chips containing pillars are aligned using a flip chip bonder and held in place using wax. The wax is used to temporarily hold the bonded chips and is removed during the copper annealing step. The two pillars are then joined using electroless copper 31

48 plating. An electroless copper bath containing copper sulfate, ethylenediaminetetraacetic acid (EDTA), and formaldehyde is used at room temperature for 16 hours (or 45 C for 6 hours) to join the two pillars with copper. After the two copper pillars are electrolessly plated together, they are annealed at an elevated temperature in a nitrogen environment. 32

49 Electroplating of Cu pillars Flip-chip alignment to the Cu pillars Cu electroless plating to join Cu pillars Figure 3.7 Cu pillar fabrication and chip substrate assembly process flow Figure 3.8 shows the joined copper pillars after a 400 C, one hour anneal and removal of the top substrate. This temperature was chosen because it causes the Avatrel plating mold to decompose leaving the exposed copper pillar. After annealing and 33

50 decomposition of the Avatrel, the top substrate was sheared off so that the joint between the pillars could be examined. The electroless copper bonding material between the two pillars can readily be identified in Figure 3.8 by its elongated horizontal dimension. The fracture of assembled copper pillars with electroless joining occurred at the copper-totitanium interface at the bottom of the copper pillar. Figure 3.9 shows a top view of the surface with one pillar structure remaining on the surface (sheared from the second surface) and one site where the pillar is missing (remaining on the mated surface). In each case the copper joining process is stronger than the pillar-to-substrate adhesion as no pillars fractured at the center electroless copper joint during testing. Therefore, copper pillars were successfully bonded by the developed electroless plating and annealing process. Figure 3.8 SEM micrograph of a joined copper pillar (125 µm wide by 98 µm tall) 34

51 Figure 3.9 SEM micrograph of a sheared off substrate Electroless copper deposition also allows for tolerance to misalignment of the pillars during the joining process. A slight misalignment of the two pillars can be seen in Figure 3.8 upon close inspection. However, the lateral (outward) plating of the electroless copper more than compensated for the spatial misalignment. Despite the misalignment the cross sectional area of the joint between the pillars is greater than the area of the pillars themselves so no loss of conductivity occurs. Finally, the seam between the electroplated copper pillars is dense with minor surface imperfections, and cavities on the sidewalls, which are likely due to gas entrapment during copper plating. Another important aspect of the electroless copper joining process is the ability to fill gaps between the pillars, since the gaps are varying across the whole bonded area due to the inevitable none-planarity surfaces of chips and substrates. The pillars were crosssectioned by grinding and polishing to examine the joint between the two surfaces. Figure 3.10 is a typical cross section showing two pillars (one from each substrate chip) joined 35

52 in the center (wide metal region) by electroless copper. Some voids were observed in the center of the electroless metal as shown in Figure 3.11 at a higher magnification. The size and density of voids in the electrolessly plated region varied for different samples. The conditions for electroless plating, distance between the two pillars, and annealing conditions all were found to affect the void size and density. The results show that the electroless plating process filled the space between the two pillars. Each of the pillars examined was fully joined by the electroless process, although the gap varied from sample to sample. This ability to fill the gap between near-mated pillars is an essential aspect of the chip-to-substrate connection. As a result, the two pillars do not have to touch at each location prior to electroless plating. Figure 3.10 Cross section of joined Cu pillars (low magnification) 36

53 Figure 3.11 Cross section of joined Cu pillars (high magnification) 3.3 Bond strength measurements of joined copper pillars The bond strength of the copper pillar joint is a critical parameter for quantifying the bonding quality and providing the maximum allowable shear stress criteria for thermomechanical designs of copper pillar interconnects. An Instron 5842 was used to measure the bond strength of the copper pillar joints. The measurement setup is illustrated in Figure 3.12, with one side of the assembled silicon chip package glued into a well in an aluminum plate. The depth of the well is 500 µm, roughly equal to the thickness of the silicon chip. The other chip is now aligned above the aluminum plate. After vertically positioning the aluminum plate, the top bonded chip is left suspended above the plate. The bottom of the glued chip touches the side wall of the well in the aluminum plate, preventing vertical movement. A controlled vertical force is exerted on 37

54 the chip that is suspended above the aluminum. The force and displacement data were collected by the Instron instrument. Once the force exceeds the maximum allowable shear force of the copper pillar package, mechanical fractures will generate in the weakest region of the pillars leading to the separation of the two chips. F Figure 3.12 Schematic illustrations of the bond strength measurement The maximum allowable shear stress can be calculated from the maximum force that the assembled chips can withstand using Equation 3.1. F τ = (3.1) A Where τ is the shear stress, F is the force on the chip and A is the total cross sectional area of the bonded pillars. Considering the high ultimate stress of copper, the total cross-sectional area of jointed copper pillars needs to be small; otherwise, the total 38

55 force needed to break good copper joints can easily reach over 100 N (the upper limit of the Instron). Therefore, a chip with four 55 µm diameter pillars, one at each corner, was designed for the bond strength measurement. Figure 3.13 shows the force-displacement curve for a bonded sample after a one-hour 400 C anneal. As explained earlier, the high temperature annealing step is used to decompose the Avatrel polymer in between the bonded chips. The copper pillar joints then contribute all of the adhesion between the two chips. As plotted in Figure 3.13, the shear force to break the bonded chips is 1.40 N. Based on the area of the four joined pillars, the corresponding maximum allowable shear stress is 148 MPa. The copper pillars were broken right at the interface with the titanium adhesion layer, as shown in Figure The shear stress of 148 MPa corresponds to the adhesion strength of copper to this titanium layer. Since the pillar-to-pillar electroless copper metal did not shear in any of the samples tested, the bond strength of copper pillars is larger than 148 MPa. Table 3.1 lists the bond strength of current commonly used assembly techniques. The developed copper electroless bonding technique achieves the highest bond strength [ ] Force (N) Displacement (mm) Figure 3.13 Force versus displacement curve for four 55 µm diameter copper pillar joints 39

56 Figure 3.14 Cracking surface on the substrate Table 3.1 Bond strength of assembly techniques Wire Solder Copper wafer Surface active Electroless bonding joints bonding bonding Cu bonding Bond strength > 89 < 60 N/A > 70 > 148 (MPa) 3.4 Temperature effects on bond strength of copper pillars To investigate the effect of annealing temperature, the same bond strength measurement procedure as described in section 3.3 has been performed on samples that were annealed at different temperatures. The shear force for separating the two substrates was measured and is reported in Table 3.2. The shear force of 1.40 N (entry A ) was for 40

57 the sample annealed at 400 o C. Avatrel was decomposed, and the force reported was the adhesion strength of copper to the titanium on the substrate. Entry B shows the shear force for a set of four pillars plated and annealed at 250 o C. The sample again fractured at the copper-to-titanium interface; however, the Avatrel was present and contact was achieved between the two sides. Thus, some of the 4.84 N force was due to the Avatrel. A second sample was prepared for 250 o C annealing (entry C ); however, chromium was the adhesion layer, rather than Ti, and the Avatrel did not bridge the two sides. The shear force was 1.80 N and the fracture occurred at the copper-to-chromium interface. The value is higher than entry A most likely because the Cr provided greater adhesion. The copper-to-copper joint did not rupture. Finally, a sample (entry D ) with a Ti adhesion layer was annealed at 200 o C and resulted in a lower shear force with the fracture occurred at the metal interface. The lower temperature samples sheared at the copper-tocopper joint. The annealing temperature affects the copper grain size distribution, grain boundary character distribution, and crystallographic texture [ ]. It is most desirable to have the anneal temperature as low as possible to prevent adverse effects occurring within the other materials in a semiconductor device. The measured results demonstrated that excellent copper-to-copper bonding can be achieved through a one hour anneal at 250 o C. 41

58 Table 3.2 Shear force for different anneal temperatures Entry Anneal Anneal Maximum shear Adhesion Temperature ( C) duration force (N) layer A hour 1.40 Ti B hour 4.84 Ti C hour 1.80 Cr D hour 1.13 Ti 3.5 Conclusions This chapter describes a novel fabrication process to obtain all-copper chip-tosubstrate connections. Copper structures were first fabricated through electroplating in a polymer mold. A copper electroless plating step was used to join the copper structures. After annealing under a nitrogen environment the bonded chips were mechanically sheared, and the newly formed copper joint was stable, with bond strength greater than 148 MPa. A process temperature as low as 250 o C, which is in the compatible range of cost effective organic BT/FR4 boards, has been proven effective. This fabrication process also shows the capability to compensate for misalignment and height variations of the bonded structures. 42

59 CHAPTER 4: MECHANICAL AND ELECTRICAL PERFORMANCE ANALYSIS OF COPPER PILLAR CHIP-TO-SUBSTRATE INTERCONNECTS Interconnects between chips and substrates have requirements with respect to mechanical and electrical performance. Due to the CTE mismatch of package materials, thermal strains and stresses will result in the chip-to-substrate interconnect structures during chip operation or environmental temperature changes. This is the main cause of thermo-mechanical failures in chip-to-substrate interconnects. With respect to mechanical performance, it is most desirable to design the copper interconnect structures to be fully compliant without the need for underfill materials, which will result in a reduction in the cost related to the materials and processes, as well as an improvement in the electrical performance of the package by reduce the dielectric loss. The key electrical considerations for high performance systems relate to parasitic inductance, capacitance, and resistance. These electrical properties are fundamentally related by the geometric parameters for the interconnect system (I/O pitch, diameter, and aspect ratio) and physical properties of the interconnects (electrical conductivity, CTE, Young s modulus, Poisson s ratio, and yield stress). In order to assess the available design space from all of the criteria, a thorough and in-depth modeling study is being performed in this chapter. 4.1 Thermo-mechanical analysis of copper pillar chip-to-substrate interconnects GPD model for copper pillar chip-to-substrate interconnects Geometry of the GPD model 43

60 A finite element 3D slice (GPD) model by ANSYS was used in this thesis to investigate the thermo-mechanical reliability of chip-to-substrate copper pillar interconnect packages and design fully compliant chip-to-substrate copper pillar interconnects to eliminate the need for underfill. The physical dimensions of the package studied in this thesis are based on ITRS projections. Table 4.1 lists chip sizes and chip-tosubstrate I/O numbers from ITRS for high performance microprocessors [4.1]. The chip size and I/O number are projected to be 310 mm 2 and 3072 respectively for the next decade. Assuming chip-to-substrate I/Os are uniformly distributed on the chip area, the I/O pitch will be 318 µm. The thickness of the board and chip are 700 µm and 900 µm respectively. A 3D slice model or Generalized Plane Deformation (GPD) model named from its boundary constraints is shown in Figure 4.1. This model simulates a diagonal slice of the package. The diagonal slice contains all the components and a full set of chipto-substrate interconnects. The I/O number is 28 and the distance between adjacent I/Os is 452 µm. Only a half pillar is modeled at the left end due to the symmetry of the pillar at the center of the whole chip. The length of the slice is mm and the width of the slice is 452 µm. The dimensions of copper pillars are variables. 44

61 Table 4.1 ITRS projections for high performance chips Year Node Chip size at production, mm Total pads number Signal I/O number Power and ground pads Figure 4.1 GPD model in ANSYS Material properties 45

62 All the mechanical properties of the materials used in the analysis for compliant copper pillar chip-to-substrate interconnects are listed in Table 4.2 [ ]. The temperature-dependent properties are listed in multiple rows. BT board was used in the model. Table 4.2 Model material properties T (K) E (GPa) CTE (10-6 /K) γ (Poisson s ratio) BT Board T 25.5 XY-15 Z Cu Si Sn3.5Ag0.75Cu T T Boundary conditions The boundary conditions of GPD model are not as apparent as those of 3D quarter and octant models. As illustrated in Figure 4.2, the single point P in the center of bottom left-most region (the center point of the whole chip) is constrained in all three directions to prevent rigid body motion. The symmetry surfaces A, B and C are fixed in the x direction from symmetry boundary conditions. The nodes on the side walls of the slice 46

63 (along the z direction) are coupled. They have identical deformation in the y direction to maintain surface planarity [ ]. The temperature range used to study the stress in the copper pillar induced from CTE mismatches between silicon chip and BT board was from -55 o C to 125 o C. The neutral position of the whole package is at room temperature, since the electroless copper bonding of copper pillars was performed at room temperature. The whole package contracts when the temperature decreases from 25 o C to -55 o C and expands back to neutral position when temperature increases back to 25 o C and continues to expand to as it is heated, reaching its maximum deformation at 125 o C. The maximum stress was generated from the larger temperature gap. The neutral position is at 25 o C. The temperature gap between 25 o C to 125 o C is larger than 25 o C to -55 o C. Therefore, the compliant design of copper pillar interconnects is based on temperature changes from 25 o C to 125 o C. 47

64 A B z x C y P Figure 4.2 Boundary conditions of GPD model Model validation The thermal deformation of an assembled package based on Avatrel was used to evaluate the accuracy of the GPD model. As illustrated in Figure 4.3, a layer of Avatrel 2090P was first spun on a 30 mm width square BT board with the spin rate of 1000 rpm for 50 seconds. After being soft baked at 100 o C for 10 minutes, a 20 mm width square silicon chip was attached at the center. After a one hour cure at 160 o C on a hotplate, the silicon chip was successfully bonded to the board by the Avatrel layer. The thicknesses of the chip, Avatrel layer, and BT board were 470 µm, 50 µm, and 1.18 mm, respectively. The deformation curvature of the top surface of the silicon chip was measured by 48

65 FLEXUS F2320 when the whole package was heated from 25 o C to 98 o C. The thermal deformation curves were also modeled by 3D quarter chip model and GPD model. Chip Avatrel BT board Figure 4.3 Chip to board attachment through an Avatrel layer Figure 4.4 shows the structure thermal deformations from 3D quarter model and Figure 4.5 shows the results from GPD model. The color changing from blue to red indicate increasing thermal deformation. The surface deformation curves from models and measurement were compared in Figure 4.6. The blue line at the bottom in Figure 4.6 is the measured surface curvature. The pink line in the middle and the black line at the top in Figure 4.6 are the simulated surface curvatures from 3D quarter model and GPD model, respectively. The surface thermal deformation strain was used to evaluate the model accuracy, which is defined by Equation 4.1. H γ = (4.1) L Where γ is the thermal deformation strain, H is the deformation in the z direction, and L is original distance from the center point to the edge as illustrated in 49

66 Figure 4.7. The differences between the simulated and measured thermal deformation strains are only 0.06% for quarter model and 0.13% for GPD model. These results prove that GPD model is an accurate model for thermo-mechanical analysis [4.12]. Figure 4.4 Structure thermal expansions from 3D quarter model 50

67 Figure 4.5 Structure thermal expansions from GPD model Surface deformation (µm) Measurement 3D quarter model GPD model Distance from center point (mm) 10 Figure 4.6 Surface curvatures from measurement and models 51

68 H L Figure 4.7 Illustration of thermal deformation Design of compliant copper pillar chip-to-substrate interconnects Mesh evaluations Stress modeling was used to design fully compliant structures. If the maximum stresses generated on the structures are below the yield stress of the material, the structures are compliant for the simulated conditions since all the deformations are elastic. A mesh technique called mapping was used in the model for high aspect ratio copper pillar interconnects. 2D mesh was first performed on one end of each of the pillars. Then, surfaces on the substrate that are connected to pillars were mapped according to the mesh on the pillar ends. 3D elements were finally generated by sweeping from the meshed areas along the 3D structures. Figure 4.8 shows a high quality mesh through mapping. The mesh on pillar to substrate interface region is shown in Figure 4.9. The pattern of meshes gradually changes from the circular shape around the center pillar to the rectangular shape of the substrate. One challenge of stress modeling is that it requires an enormously large number of elements to obtain convergence of results due to 52

69 the presence of large stress gradients in small regions. In order to reduce the number of elements used for the whole pillar, mesh refineries were performed at the high stress gradient regions. For copper pillar interconnects, the high stress gradient regions are located at near pillar to substrate interface regions as shown in Figure Figure 4.8 GPD model with mesh 53

70 Figure 4.9 A copper pillar with mesh Figure 4.10 Refined mesh near the pillar end 54

71 The maximum shear stress with increasing element number was plotted in Figure The copper pillars modeled were 30 µm in diameter and 180 µm in height. In order to avoid result singularity, the maximum stress was an average value of the element that generates the largest stress with its adjacent elements. The results show that the shear stress did not converge until the element number exceeds per pillar for this case. The required mesh density changed with varying pillar dimensions. Therefore, mesh evaluation was needed for every simulation that modified the pillar dimensions. Maximum shear stress (MPa) Element number Figure 4.11 Shear stress vs. element number on a single copper pillar Compliant chip-to-substrate copper pillars without polymer collars The maximum thermal deformation was always observed at the corners of the package, resulting in the maximum stress being generated at the corner pillars. Figure 4.12 shows the thermal deformation of a package with 30 µm diameter, 630 µm tall copper pillar interconnects. The maximum shear stress was located at the last pillar as 55

72 shown in Figure Figure 4.14 is the shear stress distribution on the copper pillar to substrate interface. For fully compliant chip-to-substrate copper pillar interconnect design, the maximum stress induced from the thermal deformation on the corner pillar should be less than the maximum stress allowed by the compliance criterion. There are three stress limits on the copper pillar: the adhesion strength between the copper to the substrate, the bond strength of the copper joints, and the yield stress of copper. The bond strength of the copper joints is equal to the yield stress of copper for high quality bonding. The maximum allowable stress is limited to the lowest one among the above three stresses for compliant copper pillar designs. The yield stress of electrodeposited copper is 225 MPa. The bond strength of copper joints through developed electroless copper bonding is larger than the adhesion strength between copper and the substrate, which is 148 MPa [4.13, 4.14]. Therefore 148 MPa is the maximum allowable shear stress for compliant chip-to-substrate copper pillar interconnects. Besides the shear stress criterion, the total stress, which also includes the normal stress, should be less than the yield stress of copper as well. 56

73 Figure 4.12 GPD model for copper pillar chip-to-substrate interconnects Figure 4.13 Shear stress distribution on the pillar-to-substrate connection region 57

74 Figure 4.14 Plane-view of the shear stress distribution on the pillar to substrate interface The shear stress is affected by the aspect ratio (diameter: height) of the copper pillars. With the same diameter, higher pillars are more compliant. The shear stresses generated on taller pillars are lower than those on shorter pillars under the same temperature excursions. The normal stresses are more related to the total metal areas that contribute to the chip-to-substrate connection than the aspect ratio of the pillars. The maximum shear stress, normal stresses, and total stresses of different diameter pillars are listed in Table 4.3. The normal stress increases as the diameter of copper pillars decreases due to the decreasing total copper area that contributes to the attachment. The normal stresses in all cases studied were smaller than the maximum shear stresses on the pillar. The total stresses of the pillar are less than the yield stress of copper. As a result, if the maximum shear stress on the pillar is less than the stress criterion of 148 MPa, the normal 58

75 stress and total stress on the pillar was always less than the yield stress of copper. Therefore, the objective for compliant chip-to-substrate copper pillar interconnect design is to obtain a curve that has the shear stress criterion on the pillar dimension chart. As plotted in Figure 4.15, the top blue line is the pillar dimensions to have maximum shear stress of 148 MPa. The dimension region above this line will have higher aspect ratio and, as a result, less shear stress than 148 MPa. Copper pillars with dimensions in this region can be used as compliant chip-to-substrate interconnects. Table 4.3 Stress results from GPD model Diamter Height Maximum shear stress Normal stress Total stress (µm) (µm) (MPa) (MPa) (MPa)

76 MPa Pillar height (um) MPa 225 MPa Fixed diameter of 50 µm MPa Pillar diameter (um) Figure 4.15 Dimension chart of copper pillar chip-to-substrate interconnects The height required for the compliant criterion is 1556 µm for 10 µm diameter copper pillars. This height requirement decreases dramatically as the diameter increases to 50 µm, after which, the height reduction is very small. For 50 µm diameter pillars, the height needs to exceed 513 µm to satisfy the compliance criterion. One way to reduce the height needed for compliant copper pillars is to improve the adhesion strength. The ideal case would be that the adhesion strength is equal or larger than the yield stress of copper. Without considering the normal stress contribution, the compliant criterion becomes to be 225 MPa. The bottom red line in Figure 4.15 is the dimension curve for the maximum shear stresses of 225 MPa. For 50 µm diameter pillars, the height needed for compliant copper pillar interconnects decreases from 513 µm to 170 µm. On the other hand, if the adhesion strength is much less than the yield stress of copper, as reported by SAB for 60

77 example, the criterion for the compliant pillar interconnects will be as low as 70 MPa [4.15]. The height required for 50 µm diameter pillars from this low shear stress criterion was close to 2100 µm, as plotted in the Figure The aspect ratio is over 40:1, which is very challenging for current fabrication techniques. Therefore, the adhesion strength is the most important parameter to determine the aspect ratio needed for compliant copper pillars. Another consideration is the effects of the generated stresses on the chip-tosubstrate interconnect to the reliability of interlayer dielectrics (ILD) on the chip. There are many studies focused on the package effects on the reliability of ILDs, but no quantitative stress data have been reported [ ]. In order to evaluate the maximum allowable stress on chip-to-substrate interconnects for ILD reliability concerns, a simple solder joint case was modeled. For current lead-free solder bump packages, the ILDs on the chip must withstand the stress generated from the solder bonding process. The maximum temperature change for solder joints occurs as the joints cool from the solder reflow temperature to room temperature. The shear stress on the solder bump generated from this process can be used as an approximate reference for ILD reliability. Sn 3.5 Ag 0.75 Cu solder bumps with dimensions of 80 µm in diameter and 100 µm in height were used. The mechanical properties of Sn 3.5 Ag 0.75 Cu solder are listed in Table 4.1. The peak reflow temperature for Sn 3.5 Ag 0.75 Cu solder is 260 C [4.8]. The maximum shear stress from GPD model of this solder case is 416 MPa, which is much higher than the yield stress of electrodeposited copper. This indicates that the criterion used in the compliant chip-to-substrate copper pillar design is reasonable for ILD reliabilities Compliant chip-to-substrate copper pillars with Avatrel collars 61

78 Polymer collars around the chip-to-substrate interconnects can enhance the interconnect reliability and reduce the aspect ratio needed for compliant copper pillar interconnects [4.20, 4.21]. Both the mechanical properties and the dimensions (the width and the height) of polymer collars affect the shear stresses induced on the copper pillars. Avatrel was studied as the polymer collar material. Avatrel has an elastic modulus of 0.5 GPa. CTE and Poisson s ratio of Avatrel is 120 ppm/k and 0.30 respectively [4.22, 4.23]. Figure 4.16 shows a short polymer collar around the roots of copper pillars of 30 µm in diameter and 630 µm in height. For 30 µm tall Avatrel collars, the maximum shear stresse on the copper pillars was plotted as a function of the width of the collar, as shown in Figure As the width of the polymer collars exceed 15 µm, there is no further improvement by increasing the width of the collar. Figure 4.18 plots the maximum shear stress versus the height for the Avatrel polymer collar with 20 µm in width. After the height of the collar higher than 45 µm, the maximum shear stress will not change with the increase in the height of the polymer collars. Therefore, if the dimensions of the polymer collars exceed 15 µm in width and 45 µm in height, there is no improvement by adding more polymer to the copper pillar structures. 62

79 Figure 4.16 Copper pillars with short polymer collars Maximum shear stress (MPa) Width of the polymer collar (um) Figure 4.17 The maximum shear stress on copper pillar vs. the width of polymer collars 63

80 Maximum shear stress (MPa) Height of the polymer collar (um) Figure 4.18 The maximum shear stress on copper pillar vs. the height of polymer collars Although only a short polymer collar is needed for the stress reductions on the copper pillars, tall polymer collars were used in the model for compliant copper pillar designs from fabrication process considerations. The copper pillars were formed by electroplating inside the polymer collar and jointed through electroless copper plating. There is no need to add an extra step to reduce the height of polymer collars. A 25 µm gap between the two polymer collars around the same copper pillar was used in the model. The shear stress distribution on the pillar end which is the interface between copper pillar and substrate is shown in Figure The center small circular region, as indicated in Figure 4.19, is copper pillar and the large ring around it is Avatrel collar. The maximum shear stress is located on the copper pillar. 64

81 Copper pillar region Polymer collar region Figure 4.19 Shear stress distribution on the pillar to substrate interface Figure 4.20 plots the copper pillar dimension curves for the maximum shear stress of 148 MPa. The top curve is for copper pillar alone and the bottom one is for copper pillar with Avatrel collars. The height reduction by Avatrel collars is more effective for smaller diameter copper pillars. As listed in Table 4.4, for 10 µm diameter copper pillars, the height needed with Avatrel collars is reduced by about 23%. As the copper diameter increases beyond 50 µm, the height reduction is stable at 13%. The height of compliant chip-to-substrate copper pillar interconnects can be reduced by 13% from Avatrel collars. The compliant dimension region is enlarged by adding Avatrel polymer collars. 65

82 Height of the pillar (µm) Without Avatrel collars With Avatrel collars Diameter of the pillar (µm) Figure 4.20 Dimension chart for copper pillar chip-to-substrate interconnects Table 4.4 Heights of compliant copper pillars Diameter (µm) Height of copper pillar without polymer collar (µm) Height of copper pillar with polymer collar (µm) Polyimide and SU-8 as polymer collar materials The mechanical properties of polyimide and SU-8 are listed in Table 4.5 [ ]. Compared to Avatrel, polyimide has a higher elastic modulus (harder), and SU-8 is the hardest among all three. 50 µm diameter, 500 µm tall copper pillars with different polymer collars were modeled. The shear stress results are listed in Table

83 Table 4.5 Material properties of polymer collars E (GPa) CTE (10-6 /K) γ (Poisson s ratio) Avatrel Polyimide SU Table 4.6 Maximum shear stresses for 50 µm diameter, 500 µm tall copper pillars Maximum shear stress (MPa) Shear stress reduction No polymer collar 150 0% Avatrel % Polyimide % SU % The maximum shear stress was reduced about 6.11% by Avatrel collars, 27.77% by polyimide collars, and 32.49% by SU-8 collars. As the modulus of the polymer collar is increased, the shear stress generated on the copper pillars decreases and as a result, the theight required for compliant interconnect is reduced. Figure 4.21 plots the heights needed for 50 µm diameter copper pillars of different polymer collars by the maximum shear stress of 148 MPa criterion. The aspect ratio of the compliant chip-to-substrate copper pillars reduces from 10.3 for copper pillars without polymer collars to 8.8 with Avatrel collars, 4.4 with polyimide collars, and 2.1 with SU-8 collars. 67

84 Height of the pillar (µm) No Polymer Avatrel Polyimide SU-8 Figure 4.21 Height of compliant copper pillars with difference polymer collars Polymer collars can reduce the stress on the copper pillar chip-to-substrate interconnects for temperature changing conditions. Consequently, the height for compliant copper pillars will reduce by adding polymer collars. The reduction in height is strongly related to the elastic modulus of the collar materials used. In summary, increasing the modulus of the polymer collars, reduced the height that is necessary for the reliability design. 4.2 Electrical performance analysis of copper pillar chip-to-substrate interconnects Interconnects have parasitic inductance, capacitance and resistance associated with them. Parasitics of chip-to-substrate interconnects are determined by the interconnect dimensions, electrical properties of the interconnects, and the electrical properties of the medium between interconnects. It is most desirable to have air as the medium between the chip-to-substrate interconnects due to the maximum reduction in dielectric constant. The parasitic inductance is important for power integrity, the parasitic 68

85 capacitance affects the signal integrity, and resistance contributes to the signal RC delay and conductor loss Parasitics of copper pillar chip-to-substrate interconnects Parasitic inductance of chip-to-substrate copper pillar interconnects The layout of chip-to-substrate P/G I/Os is shown in Figure Each power (ground) I/O is surrounded by four ground (power) I/Os. As there are a large number of P/G I/Os on chip surface, if each I/O carries the same amount of current, the parasitic inductance associated with a pair of P/G I/Os can be calculated based on the group of structures shown in Figure Electrical current, I, is fed into the center power I/O, and returns evenly through the four neighboring quarter ground I/Os (0.25I). The parasitic inductance of P/G I/Os can be derived from a group of a center pillar with four quarter pillars around it. In order to derive a closed form formula for the parasitic inductance, the quarter pillars were replaced by whole pillars with the same cross-section area as shown in Figure RAPHAEL, a software for structure inductance and capacitance simulations, was used to evaluate the offset comes from this assumption. Figure 4.23 plots the self inductance for the quarter pillar and the whole pillar with the same crosssection area. The height of simulated pillars is 200 µm. The blue line is the self inductance of the quarter pillar and the purple line is the self inductance of the whole pillar. The inductances of the two structures are very close. The inductance differences increase as the diameter increases. The maximum difference is 2% for100 µm diameter pillars. Therefore, the assumption to use whole pillar with the same cross-section area for quarter pillars is accurate for inductance calculations. 69

86 1/4I 1/4I I 1/4I 1/4I 1/4I I M 1 1/4I 1/4I 1/4I M3 M 2 Figure 4.22 Chip-to-substrate power/ground I/O layout 70

87 70 Self inductance (ph) Diameter (µm) Figure 4.23 Self inductance for 200 µm tall pillars The parasitic inductance for the group of the center power pillar with four smaller ground pillars is derived based on the self inductance and mutual inductance of pillar structures. The self inductance for pillar structure can be calculated by Equation H 3 4 L = 0.002H[ln( ) ] 10 ( H ) (4.2) D 4 Where H is height of the pillar and D is diameter of the circular cross-section as shown in Figure 4.24 [4.27]. The mutual inductance between two pillars can be calculated by Equation 4.3. M 2 2 H H d d 4 = 0.002H[ln( + 1+ ) 1+ + ] 10 ( H ) (4.3) 2 2 d d H H Where H is the height of the pillar and d is the distance between the center points of two pillars as shown in Figure 4.25 [4.27]. Even in the case in which the two pillars are nearly in contact, this equation is sensibly accurate [4.27]. 71

88 D H Figure 4.24 Single copper pillar d D H Figure 4.25 Two adjacent copper pillars If no loss is assumed in the connections between power I/O and four ground I/Os, the circuit diagram can be drawn as shown in Figure The four ground pillars have the same height with the center power pillar, but only 1/4 the cross-section area, as a result, the resistance of the ground pillar is four times that of the center pillar. If the resistance of the center power pillar is R, the resistance of the ground pillar will be 4R. The voltage drop on whole circuit can be divided into two parts: the voltage drop on the power I/O and the voltage drop on the ground I/O as shown in Equation 4.4. V = V + V (4.4) circuit power ground 72

89 1/4 I L ground 4R Ground I/O 4R 1/4 I L ground Ground I/O 1/4 I L ground 4R Ground I/O _ I 1/4 I 4R L ground Ground I/O V R L power + Power I/O Figure 4.26 Circuit diagram of power/ground I/Os For the whole circuit, the voltage drop equals to the product of current and circuit impedance as shown by Equation 4.5. The impedance of the circuit shown in Figure 4.26 can be expressed by Equation 4.6. The total circuit resistance can be calculated by Equation 4.7. Substitution of Equation 4.6 and Equation 4.7 into Equation 4.5 gives Equation 4.8. V circuit = IZ circuit (4.5) Z circuit = R + jωl (4.6) circuit parasitic 1 R circuit = R + 4R = 2R (4.7) 4 V = 2 IR + jω (4.8) circuit IL parasitic Where V circuit is the voltage drop on the whole circuit, I is the current, Z circuit is the impedance of the circuit, R circuit is the resistance of the circuit, ω is angular frequency, j 73

90 the imaginary unit, which is the square root of -1, and L parasitic is the parasitic inductance of the P/G I/Os. Equation 4.9 to Equation 4.13 are for the center power pillar derived from the same procedure as described for the whole circuit except that the effective inductance of the power pillar is calculated by Equation V power = IZ power (4.9) Z power = R + jωl (4.10) power power _ eff R power = R (4.11) L 1 = L 4 M 1 (4.12) 4 power _ eff power V 1 = IR + jω ( IL power 4 IM 1) (4.13) 4 power Where V power is the voltage drop on the power I/O, Z power is the impedance of the power I/O, R power is the resistance of the power I/O, L power is the self inductance of the power I/O, M 1 is the mutual inductance between the power I/O and an adjacent ground I/O as shown in Figure 4.22, and L power_eff is the effective inductance of the power I/O. The same derivative procedure for each ground pillar gives Equation 4.14 to Equation The effective inductance of each ground pillar is calculated by Equation V ground = IZ ground (4.14) 4 Z ground = R + jωl (4.15) ground ground _ eff R ground = 4R (4.16) 74

91 L ground _ eff Lground + M 3 + 2M 2 M1 = (4.17) V ground = I 4R + jω ( ILground + IM IM 2 IM 1) (4.18) Where V ground is the voltage drop on one ground I/O, Z ground is the impedance of one ground I/O, R ground is the resistance of one ground I/O, L ground is the self inductance of one ground I/O, L ground_eff is the effective inductance of one ground I/O, M 2 is the mutual inductance between the two nearest ground I/Os, and M 3 is the mutual inductance between the two ground I/Os at opposite corners among the four I/Os around the center power I/O. Substitution of Equation 4.13 and Equation 4.18 into Equation 4.8 gives Equation IR + jω = 2IR + ( ILpower 4 IM 1) + I 4R + jω( ILground + IM IM 2 IM 1 jωil parasitic ) (4.19) After rearrangement of Equation 4.19, the parasitic inductance of copper pillar power and ground I/O can be expressed by Equation L = M 3 (4.20) parasitic L power + Lground 2M 1 + M 2 + The parasitic inductance of copper pillar chip-to-substrate interconnects can be calculated by the combinations of Equation 4.20, Equation 4.2, and Equation 4.3. In order to evaluate the parasitic inductance of compliant copper pillar chip-to-substrate interconnects, the parasitic inductance of solder bumps was used as reference. 96 ph was reported for the parasitic inductance of 125 µm diameter eutectic solder bumps [4.28]. Figure 4.27 plots the dimension curves of copper pillar with the parasitic inductance of 96 ph, 200 ph, and 300 ph respectively. The parasitic inductance increases as the height of copper pillar increases. The dimensions of copper pillars need to be in the regions 75

92 below the constant inductance curve in order to keep the parasitic inductance of the interconnects below the inductances on the curves. For solder bumps, the parasitic inductance is very small due to its low aspect ratio (about 1). For compliant copper pillar interconnects, the aspect ratio is much higher than 1, which causes the increase in parasitic inductance. As plotted in Figure 4.27, the parasitic inductance increases to 300 ph for copper pillars with aspect ratio of 8. The increased parasitic inductance is a penalty for compliant copper pillar chip-to-substrate interconnects. Although the parasitic inductance is increased to 300 ph range, it is still much smaller than the parasitic inductance of wire bonding packages [4.29, 4.30] Pillar height (um) L 300 ph 200 ph ph Pillar diameter (um) Figure 4.27 Parasitic inductance of power/ground I/Os 76

93 Parasitic capacitance of copper pillar chip-to-substrate interconnects The parasitic capacitance of two chip-to-substrate copper pillar signal I/Os, as shown in Figure 4.25, can be calculated by Equation 4.21 to Equation 4.24 through lumped-element circuit for high frequency signals [4.31, 4.32]. πε 0ε r C = d d ln[ + ( ) D D 2 H 1] ( F) (4.21) µ 0µ r d L = ln[ + π D d ( ) D 2 1] H ( H ) (4.22) 2Rs R = H πd ( Ω) (4.23) πωε G = d d ln[ + ( ) D D 2 H 1] ( S) (4.24) Where d is the distance between two centers of the adjacent pillars, D is the diameter of the pillar, H is the length of the pillar, ε 0 is the permittivity of vacuum, ε r is the relative permittivity, µ 0 is the permeability of vacuum, µ r is the relative permeability, ω is angular frequency, ε is imaginary part of the complex permittivity, L is the selfinductance of the two copper pillars, C is the capacitance, R is the resistance, G is the shunt conductance due to dielectric loss in the material between the pillars, and R s is the surface resistance of the pillars. In order to evaluate the parasitic capacitance of compliant copper pillar chip-tosubstrate interconnects, the parasitic capacitance of solder bumps was used as reference. 8.8 ff was reported for the parasitic capacitance of 125 µm diameter eutectic solder bumps [4.28]. Figure 4.28 plots the dimension curves for parasitic capacitance of 8.8 ff, 77

94 7 ff, and 5 ff. The dimensions of copper pillars in the region below the constant capacitance lines in the Figure 4.28 have less parasitic capacitance than 8.8 ff, 7 ff, and 5 ff, respectively. Pillar height (um) ff 7 ff 5 ff Pillar diameter (um) Figure 4.28 Parasitic capacitance of two copper pillars Characteristic impedance of copper pillar chip-to-substrate interconnects The characteristic impedance is defined by Equation 4.25 [4.33]. R + jωl Z 0 = ( Ω) G + jωc (4.25) 78

95 For compliant copper pillar chip-to-substrate interconnects, the shunt conductance is 0, as shown in Equation 4.26, since only air is in between the two pillars. Z 0 is simplified to Equation G = 0 (4.26) R + jωl Z 0 = (4.27) jωc Further simplification to Z 0 needs to compare the absolute number of R and ωl. R can be calculated by Equation The surface resistance can be calculated from its definition Equation R s 1 = (4.28) σδ s Where σ is the conductivity of copper, which is (S/m) and the skin depth is defined by Equation 4.29 [4.33]. 2 1 δ s = = (4.29) ωµσ π fµ σ R s can be expressed as a function of signal frequency in Equation Substitution of Equation 4.30 into Equation 4.28 gives Equation R s 1 π fµ σ π 4π = = = f = πf (4.30) 7 σδ s σ R 2R H D s = H = f (4.31) π D ωl can be calculated by Equation d d 2 d d 2 6 ω L = 2 fµ 0 ln[ + ( ) 1] H = ln[ + ( ) 1] H 10 f (4.32) D D D D Dividing R by ωl results in Equation

96 R ωl = d ln[ + D 7 d ( ) D 2 H D f 0.5 1] H 10 6 f = d D ln[ + D d ( ) D 2 2 1] f 0.5 (4.33) From the ITRS 2006 update, the chip-to-board signal frequency increases from 9.31 GHz in 2010 to GHz by 2020 (in the order of ) [4.1]. The diameter of the copper pillar, D, is in the range between 15 µm to 100 µm (in the order of 10-4 ). For chipto-substrate I/Os, the pitch distance, d, is larger than D, and as a result, the natural R logarithm term is larger than 1. The whole denominator term is in the order of 10, so ωl is about three order of magnitudes smaller than 1, which means R << ωl. Therefore, the resistance term can be neglected in Equation The characteristic impedance for copper pillars with air medium can be simplified to Equation 4.34 Equation L Z 0 = (4.34) C Substitution of Equation 4.21 and Equation 4.22 into Equation 4.34 gives Z 0 = L C = µ 0µ r d d ln[ + ( ) π D D πε ε d ln[ + D 0 r d ( ) D 2 2 1] 1] H H 1 = π µ ε 0 0 d ln[ + D d ( ) D 2 1] (4.35) d = ln[ + D d ( ) D 2 1] ( Ω) The characteristic impedance of copper pillars is a function of pillar diameters and I/O pitches. For the pitch of 318 µm (discussed in section 3.1), the characteristic impedance is a function of the diameter as plotted in Figure

97 Characteristic impedance (Ω) Diameter of copper pillars (um) Figure 4.29 Characteristic impedance of two copper pillars The characteristic impedance of copper pillars is higher than the standard 50 Ω lines. The impedance effects need to be evaluated, since the characteristic impedance is not matching. As illustrated in Figure 4.30, copper pillar interconnects are connected to the metal wires on the chip. The input impedance of the copper pillars with an arbitrary load impedance can be calculated by Equation V, I Z 0, β + _ Z L H Figure 4.30 Copper pillars with load on chip 81

98 Z in Z L + jz 0 tan( βh ) = Z 0 (4.36) Z + jz tan( βh ) 0 L Where Z L is the load impedance, Z 0 is the characteristic impedance of copper pillars, H is the height of the pillars, and β is the phase constant, which is defined by Equation 4.37 [4.33]. β = ω LC (4.37) Substitution of Equation 4.21 and Equation 4.22 into Equation 4.37 gives Equation β 0 r 0µ r = ω LC = 2πf ε ε µ H (4.38) Substituting Equation 4.38 into Equation 4.36 gives Equation Z in = Z 0 Z Z L 0 + jz + jz 0 L tan( βh ) tan( βh ) = Z 0 Z Z L 0 + jz + jz 0 L tan( tan( H H 2 2 f ) f ) (4.39) The term of H 2 f is a very small number, and as a result, tan( H 2 f ) H 2 f. Using this approximation, the input impedance can be calculated by Equation Z Z L + jz 0 tan( H f ) Z L Z 0H fj = Z 0 Z (4.40) 8 Z + jz tan( H f ) Z Z H fj in 2 0 L 0 L Z 0 is in the order of 10 2, Z L is in the order of 10, H 2 is in the order of 10-6, and f is in the order of The combination term of ZH 2 fj is in the order of 10-2, which is four or three order of magnitudes sm aller than Z 0 and Z L. Therefore ZH 2 fj term in the equation can be neglected. The input impedance is equal to the load impedance that the copper pillars connected as shown by Equation

99 Z Z Z = Z in L 0 L (4.41) Z 0 The result from Equation 4.41 shows that although the characteristic impedance of the chip-to-substrate copper pillar interconnects is in the range between 200 Ω to 500 Ω, it will not affect the characteristic impedance of the signal lines when added to the lines because of its short height (less than 1 mm). Impedance matching is not an issue for chip-to-substrate copper pillar interconnects Resistance of copper pillar chip-to-substrate interconnects The resistance of chip-to-substrate copper pillar interconnects is very small compared with ωl, as discussed in section 4.2.3; therefore, the resistance contribution to the impedance of chip-to-substrate interconnects is negligible. Compared with solder bumps, copper pillars have lower in electrical resistivity, but higher aspect ratio. The DC resistance is defined by Equation ρh R = A (4.42) Where ρ is electrical resistivity of the materials, H is the height of the interconnect, and A is the cross-section area of the interconnect. The electrical resistivities of copper and solder are Ωm and Ωm respectively [4.33]. For the same diameter solder bump and copper pillar interconnects, the resistance is determined by the product of electrical resistivity and aspect ratio. Solder bumps have an aspect ratio of 1. The resistance of copper pillars will be smaller than solder bumps if the aspect ratio of copper pillars is below the quotient of solder and copper electrical resistivities, which is

100 4.2.2 Electrical performance design of copper pillars In order to maintain the parasitics of the chip-to-substrate copper pillar interconnects at a low level. The dimensions of copper pillars should be within the overlap region of parasitic inductance and parasitic capacitance. As shown in Figure 4.31, the purple region below the constant parasitic capacitance curve is the dimensions with less parasitic capacitance than 8.8 ff. The light green region below the constant parasitic inductance curve has less parasitic inductance than 300 ph. The overlay region has both a parasitic capacitance less than 8.8 ff and a parasitic inductance less than 300 ph C=8.8 ff Low parasitic C Low parasitic L Pillar height (um) L=300 ph Pillar diameter (um) Figure 4.31 Electrical performance design of copper pillars Electrical performance design of copper pillars with polymer collars 84

101 Parasitics of chip-to-substrate copper pillar interconnects with polymer collars The parasitic inductance and resistance of copper pillar interconnects are not affected by adding polymer collars around them. The parasitic capacitance increases though since polymers have a higher dielectric constant (relative permittivity) than air. The capacitance calculation of two copper pillars with polymer collars is complex due to the bended electrical field lines between the two circular conductors. A simple way to estimate the capacitance between two pillars is to obtain an effective dielectric constant to represent the combination effect of polymer collar and air. The polymer collar has the largest volume occupation in an infinite small region between the two pillars, marked by D in Figure The effective dielectric constant calculated based on this region is higher than the actual dielectric constant, and consequently, the calculated capacitance is higher. This overestimated parasitic capacitance provides a safe margin in the design space. Therefore, the parasitic capacitance calculated based on this overestimated effective dielectric constant can be used for electrical performance design purpose. As shown in Figure 4.32, the capacitance of the small region between the two pillars can be calculated as a series of three capacitors by Equation C 1 and C 3 are the capacitance of polymer collars. C 2 is the capacitance of the air between the polymer collars. Each capacitance can be treated as two parallel plates since the electrical field lines are straight. Capacitance of two parallel plates can be expressed as Equation Substitution of Equation 4.44 into Equation 4.43 allows the effective dielectric constant to be expressed by Equation The parasitic capacitance of copper pillars with polymer collars can be calculated by Equation 4.21 using the effective dielectric constant calculated by Equation 4.46, which is rearranged from Equation

102 D Avatrel Air d 1 d 2 d 3 d C 1 C 2 C 3 Figure 4.32 Two copper pillars with polymer collars 1 C = + + = + (4.43) C C C C C ε A C 0 ε = r (4.44) d 86

103 Where ε 0 is the permittivity of vacuum, ε r is the relative permittivity of the medium, A is the area, and d is the distance between the two plates. d ε 2d1 d 2 == + (4.45) A ε ε A ε ε A ε 0 eff 0 polymer 0 air ε eff dε polymer = (4.46) 2 d + d ε 1 2 polymer Where d is the distance between the two copper surfaces, d 1 and d 3 are the thickness of the polymer collars, and d 2 is the distance between the two polymer collar surfaces as shown in Figure The dielectric constant of Avatrel is 2.5 [4.23]. The parasitic capacitance of 8.8 ff is used as reference (discussed in section ). The constant parasitic capacitance curves are plotted in Figure Line (a) is for copper pillars without polymer collar. Line (b), (c), and (d) are the dimension curves with polymer collars. The width of the Avatrel collars is 20 µm, 30 µm, and 40 µm for (b), (c), and (d) respectively. The region with low parasitic capacitance than 8.8 ff decreases with the increasing polymer collar width. 87

104 (a) (b) (c) (d) Pillar height (um) Pillar diameter (um) Figure 4.33 Capacitance curves for two copper pillars with polymer collars Electrical performance design of chip-to-substrate copper pillar interconnects with Avatrel collars The constant parasitic curves for copper pillars with Avatrel collars are plotted in Figure The dark pink region has the parasitic capacitance less than 8.8 ff for copper pillars with Avatrel collars. Comparing with the light purple region for copper pillars without polymer collars, the aspect ratios decrease for the same parasitic capacitance. The design space for both parasitic capacitance criterion and parasitic inductance criterion is the overlap region between the dark purple and light green as plotted in Figure The electrical performance design space of the copper pillars becomes smaller with Avatrel collars. 88

105 ght (µm) Pillar hei C= 8.8 ff Low parasitic L Low parasitic C without Avatrel Low parasitic C with Avatrel L= 300 ph Pillar diameter (µm) Figure 4.34 Electrical performance design of copper pillars with Avatrel collars 4.3 Mechanical and electrical designs for copper pillar chip-to-substrate interconnects Mechanical and electrical design for copper pillars without polymer collars From the results in the previous sections, we can combine the mechanical and electrical design space together to obtain the dimension space of copper pillars to satisfy both mechanical reliability requirements and electrical performance requirements. Figure 4.35 plots the design curves for copper pillars without polymer collars. The blue region is mechanically compliant for the criteria of maximum shear stress less than 148 MPa. The purple region has parasitic capacitance less than 8.8 ff. The green region has parasitic inductance less than 300 ph. The overlap region in the middle satisfies all three requirements. This region covers the diameter from 48 µm to 100 µm with the height 89

106 from 508 µm to 657 µm. Copper pillars with the dimensions in this region are low in electrical parasitics and mechanically compliant. Pillar Height (µm) Mechanical compliant region Low parasitic L region Low parasitic C region Pillar diameter (µm) Figure 4.35 Mechanical and electrical performance design of copper pillars Mechanical and electrical design for copper pillars with Avatrel collars The design space for copper pillars with 20 µm width Avatrel collars is plotted in Figure Compared with Figure 4.35, the mechanical compliant curve and parasitic capacitance curve move downwards, while the parasitic inductance curve keeps unchanged. The overlap region that satisfies all the requirements is enlarged due to the mechanical improvement by Avatrel collars. The optimum design space covers the diameter from 38 µm to 100 µm with the height from 441 µm to 617 µm. Copper pillars with Avatrel collars with dimensions in this region are compliant and have low electrical parasitic characteristics. 90

107 Pillar height (µm) Mechanical compliant region Low parasitic L region Low parasitic C region Pillar diameter (µm) Figure 4.36 Mechanical and electrical performance design of copper pillars with Avatrel collars Discusses of proposed spaces for processing window and other polymers as collar materials From the results discussed in section and section 4.3.2, the reduction in pillar height by Avatrel collars not only enlarges the design space for compliant high performance chip-to-substrate interconnects, but also facilitates the pillar fabrication. For the developed fabrication technology described in Chapter 3, the dimension space for the processing window is limited by the aspect ratio of 7 and the maximum height of 300 µm. As plotted in Figure 4.37, the region below the black line is the processing window. The copper pillars with dimensions in this region can be fabricated. Since the fabrication feasibility is mainly limited by the mechanical compliant criteria, parasitic capacitance 91

108 criteria were not plotted in Figure The blue region is the mechanical compliant region for copper pillars with Avatrel collars. The region above the light black dash line is the mechanical compliant region for copper pillars with polyimide collars. The region above the dark dash line in the bottom is the mechanical compliant region for copper pillars with SU-8 collars. These two dash lines were extended from a single simulated point with 50 µm diameter. They were used here to estimate the mechanical improvements by polyimide and SU-8 collars. The light purple region has parasitic inductances less than 300 ph and the dark purple region has parasitic inductances less than 96 ph. Pillar height (µm) Compliant region (Avatrel) Parasitic L less than 300 ph Parasitic L less than 96 ph Processing window Compliant region (polyimide) Compliant region (SU-8) Pillar diameter (µm) Figure 4.37 Design and processing spaces for copper pillar chip-to-substrate interconnects 92

109 From Figure 4.37, the dimensions of compliant copper pillars with Avatrel collars can not be produced by the fabrication process described in Chapter 3. The compliant regions of copper pillars with polyimide and SU-8 collars are overlapped with the processing window. The dimensions of copper pillars with polyimide or SU-8 collars in the overlapped region are mechanically compliant and within the capability space for the developed fabrication process. Another benefit from polyimide and SU-8 collars is that the reduced heights have less parasitic inductance characteristics. For 50 µm diameter copper pillars with polyimide and SU-8 collars, the heights required for the compliant criterion are 221 µm and 105 µm, respectively. The parasitic inductances are less than 96 ph, as indicated in Figure Therefore the improvement in mechanical compliance of copper pillars is critical for both electrical performance and fabrication process considerations. 4.4 Conclusions This chapter discussed the mechanical and electrical performance of copper pillar chip-to-substrate interconnects. A finite element GPD model was employed to design fully compliant copper pillars to eliminate the need of underfill. Electrical parasitics of copper pillar chip-to-substrate interconnects were studied by the derived formulas for low parasitic requirements. An optimized dimension space for all the criteria was provided on the pillar dimension chart. Polymer collar effects on copper pillar mechanical and electrical performance were studied. The available dimension space for copper pillars with polymer collars was also provided on the pillar dimension chart. From the results in this chapter, copper pillar chip-to-substrate interconnects can have high electrical performance with high mechanical reliability. 93

110 CHAPTER 5: NANOIMPRINT LITHOGRAPHY FOR CHIP-TO- SUBSTRATE OPTICAL INPUT/OUTPUT INTERCONNECTS In this chapter, a new fabrication method is described to form high aspect ratio, complex structures for chip-to-substrate optical I/O applications. This fabrication method combines nanoimprint lithography and photolithography to produce macro-scale features with micro-scale structures on them in a single process sequence containing only one ultraviolet exposure step. A prefabricated stamp was used to directly emboss a photosensitive polymer prior to ultraviolet exposure without compromising the photosensitivity of the polymer. A temporary glass layer was deposited over the imprinted structure to preserve the fine features so that a large-scale photo-definition process could be completed. The photosensitive polymer Avatrel has been chosen to fabricate optical interconnects because of its excellent optical properties [ ]. The mechanical imprint behavior of Avatrel has been studied during different steps of the photo definition process. This investigation assessed the feasibility of mechanically imprinting a fine surface relief feature directly into a photosensitive polymer while maintaining the photopattern capabilities of the polymer. 5.1 Determination of Optimum Imprint Step for Avatrel 2090P The photodefinition process of Avatrel 2090P includes five major steps: soft bake, UV exposure, post exposure bake, develop, and cure. Avatrel 2090P uses a different solvent, mesitylene, compared with decalin used in Avatrel 2190P. The mechanical properties of the polymer change during every step except during development. A 94

111 Hysitron TriboIndenter was used to capture the mechanical property change of Avatrel after soft bake, UV exposure, post exposure bake, and cure to determine the most effective state to imprint. During the indentation experiments, a 200 µm spherical load tip was used to apply a load force. The load force was ramped from 0 mn to 15 mn at a rate of 1.5 mn/s and the peak load was held for 5 seconds before the force was removed. Figure 4.1 shows the force-displacement curves for Avatrel 2090P after four different points in the polymer process sequence: (a) soft bake at 100 o C for 10 minutes, (b) exposure to 365 nm UV at 1000 mj/cm 2, (c) post exposure bake at 100 o C for 20 minutes, and (d) curing at 160 o C for 60 minutes. The mechanical properties of the Avatrel 2090P were obtained from the force displacement curves using the analysis method developed by Oliver and Pharr [5.6, 5.7]. The reduced elastic modulus and stiffness can be calculated from the measured load versus displacement curves from equation 5.1. S dp 2 = = Er A (5.1) dh π Where P is the load force, h is the displacement, S=dP/dh is the experimentally measured stiffness of the upper portion (10%) of the unloading data, A is the projected contact area (dependent on the load tip), and E r is the reduced modulus defined by Equation E r 2 (1 γ 2 ) (1 γ i ) = + (5.2) E E i Where E and γ are Young s modulus and Poisson s ratio for the sample, and E i and γ i are the same parameters for the indenter. A summary of the values are given in Table 5.1. The polymer was most easily deformed after the soft bake, and the exposure 95

112 steps indicated by the relatively low modulus and stiffness. After the curing reaction, Avatrel has a high modulus and harder to indent. According to the residual depth data, the most effective state to imprint Avatrel is after the soft bake step. The indentation image depth is about 2.5 times greater than after the exposure step, 1.4 times greater than after the post exposure bake step, and 2 times greater than that after the curing step for the same indentation force. When determining the optimum step for imprinting, it is important to minimize interference between the photo-definition step and the imprint step. If imprinting was performed after the photo-definition step, the elevated pressure during the imprint step could deform the photo-pattern. Thus indentation was performed directly after the polymer soft bake step and before the UV exposure step. Load Force, un Avatrel Polymer (d) (c) Displacement, nm (a) (b) Figure 5.1 Load versus displacement curves for Avatrel 2090P (a) after soft bake, (b) after exposure, (c) after post exposure bake, (d) after curing 96

113 Table 5.1 Mechanical Properties of Avatrel 2090P after the four primary processing steps Avatrel 2090P After After After After soft bake exposure post bake cure Reduced modulus Er (GP) The residual depth (nm) Contact stiffness (µn/nm) Stamp Fabrication and anti-adhesion treatment The silicon imprint stamps were fabricated by photolithography for micron scale use and e-beam lithography for submicron use followed by reactive ion etching. For the micron scale features, photoresist was spun on the silicon wafer and patterned using UV exposure. For the submicron features, polymethylmethacrylate (PMMA) was coated onto the silicon wafer and patterned using electron exposure. The patterns were transferred to the silicon by standard reactive ion etching and were used for imprinting after resist/pmma removal. Figure 5.2 shows the topography of a micron scale silicon stamp captured by a Wyko Non-contact Optical Profilometer. The features in the silicon stamp were 98 µm wide and 2 µm high with a 225 µm spacing. Figure 5.3 is an SEM image of submicron silicon grooves with 320 nm width, 1.5 µm depth, and 280 nm spacing. 97

114 Figure D Profile of the stamp used for imprinting experiments Figure 5.3 SEM picture of 600 nm period grooves To facilitate separation between the stamp and the imprinted polymer, the silicon stamps were covered with a monolayer of (3,3,3-Trifluoropropyl) dimethylchlorosilane (TFS) through a 40 minute chemical vapor deposition process at 60 o C [5.8, 5.9]. The 98

115 surface treatment process successfully helped to reduce both the separation force and distortion of the imprinted structures during the separation. 5.3 Optimization of imprint process parameters When determining the optimum imprint parameters, it is important to maintain the fidelity of the imprint process, that is, ensure that the features on the stamp are accurately reproduced on the imprinted substrate. As discussed in section 5.1.the optimum step for imprinting is after the soft bake. The effect of temperature during the imprint process was studied to optimize the imprinted image. The topography of the stamp was shown in Figure 5.2. The dimensions of silicon bumps are 98 µm in width, 2 µm in depth, and there is a 250 µm gap between two adjacent bumps. Figure 5.4 shows the profile of Avatrel imprinted at room temperature at 40 N/cm 2 pressure, and the fidelity of the imprint is poor. Although the width of the imprinted trench is about 98 µm, the height is only 30 nm, which is only about 1.5 percent of the stamp height. As the imprint temperature was increased, the polymer more easily deformed and the fidelity improved. Figure 5.5 shows the topography of Avatrel imprinted at 100 o C. The fidelity of the pattern transfer from the stamp to the polymer was excellent. The width of the polymer trench is 98 µm and the height is 1.9 µm. The surface is flat and the sidewalls are sharp with only slight rounding at the corners. 99

116 Figure D Profile of the imprinted image in the polymer after soft bake at room temperature Figure D Profile of the imprinted image in the polymer after soft bake at 100 C It is also important to maintain the imprinted patterns without deformation during the subsequent post bake and curing steps. Cooling with a force applied to the stamp was critical to the release process. If the stamp was released while the polymer film was hot, 100

117 stiction and pattern distortion occurred immediately and further during the post exposure bake and curing steps. Contraction of the polymer during the cooling step (CTE induced effect) and a lower degree of plastic flow (lower temperature as compared to the glass transition temperature) improved the fidelity of the image. Figure 5.6 shows the profile of Avatrel patterns after post exposure bake and curing. The lateral fidelity of the imprinted pattern was maintained, but the vertical depth was reduced by about 20%. Both the top and bottom surface were slightly rounded. Figure D Profile of the imprinted image in the polymer with cooling followed by post exposure bake and curing To confirm the indentation results in section 5.1, imprint experiments were also performed on polymers after exposure, after post exposure bake and after curing. No pattern resulted when the polymer was imprinted directly after UV exposure. Figure 5.7 shows the profile of the Avatrel surface when imprinted after the post exposure bake. The 101

118 surface topography was similar to Figure 5.7 when imprinting was performed after the polymer curing step. In Figure 5.7, the width of the trench is 98 µm, but the height is 0.4 µm which is only 25% of the stamp height. These results verified that imprinting Avatrel 2090P after the soft bake step was the most effective point in the process. Imprinting after soft baking, without using a polymer transfer layer, was also shown to not interfere with the photo-sensitive nature of the polymer. Imprinting after soft baking also allows the use of relatively low temperatures and pressures as compared with other imprint processes [ ]. Figure D Profile of the imprinted image in the polymer after post bake 5.4 Combination of nanoimprint lithography and photolithography While a high fidelity imprint structure could be formed after the soft bake step, the solvent development of the photo-exposed polymer can cause the dissolution of the imprint pattern in the polymer. The polymer which was imprinted after soft bake step was taken through the full exposure and developing process. Features were imprinted 102

119 into Avatrel after soft bake using a sub-micrometer stamp. The resulting features consisted of lines with dimensions: 0.5 µm in width, 1.0 µm in depth, and 11.5 µm in pitch. The sample was then taken through UV exposure and development resulting in sharp-walled pillar structures shown in Figure 5.8. The sharp-walled pillar structure is nicely resolved, but no surface relief pattern formed on the top surface of the pillar. The sub-micrometer indent structure was dissolved during the solvent development step. Figure 5.8 SEM of the pillar produced without protection layer It was necessary to protect the indented surface from the developing solution to preserve the fine indent pattern until the entire fabrication process was completed. A variety of materials can be used for preserving the indented structures. The protection layer needs to be insoluble in Avatrel developer, have a high elastic modulus so it does not flow during the heating steps, and be transparent to UV light so that the polymer can 103

120 be photo-exposed through the protection layer. Among the successful protection layers were silicon dioxide and spin-on-glass (SOG). The Honeywell Accuglass T12B SOG layer provided a thin, transparent layer with mechanical rigidity. With the successful inclusion of a thin, hard protection layer on top of the imprinted polymer, a full process flow could be assembled. The full sequence for producing a surface relief feature onto Avatrel is shown in Figure 5.9. A double-layer of Avatrel 2090P was spin coated using two spin speeds: 500 rpm and 1000 rpm to improve polymer uniformity. The first polymer layer was soft baked at 100 C for 8 minutes before the second spin application. It was then soft baked for two hours at 80 C to evaporate the solvent. A 500 nm deep diffractive grating feature was then imprinted into the polymer film. The imprint stamp was treated with TFS and the imprint followed the steps described in the previous section. A 0.5 µm SOG protection layer was spin-coated onto the imprinted polymer surface at a spin speed of 4000 rpm for 30 seconds. The SOG was soft baked at 80 C for 5 minutes, followed by deposition of another Avatrel 2090P layer at a spin speed of 4000 rpm. After soft baking the Avatrel at 90 C for 10 minutes, the sample was UV exposed at a dose of 1400 mj/cm 2 in 365 nm wavelength light through a photo mask to define the pillars. After a 20 minutes post exposure bake at 100 C in the oven, the top Avatrel 2090P layer was spray developed for 20 seconds. The Avatrel pattern on top of the SOG layer (pillar pattern) was used as a mask to remove the SOG from the field region using buffered oxide etch. A low power oxygen plasma etch step removed the residue in the field region. Finally, the lower, thick Avatrel 2090P layer was spray developed with the SOG layer protecting the indented features. The temporary SOG protection layer and the upper Avatrel 2090P residue were removed by etching in 104

121 dilute HF. The Avatrel pillars were cured by heating at 160 C for 1 hour with 3 C/min ramping in a nitrogen filled furnace. Si Spin coating HF etching Avatrel 2000P Imprint Stamp Develop Avatrel 2090P Emboss BOE etching Separate Develop top Avatrel 2090P Mask Spin on glass SiO 2 Spin coating UV exposure Avatrel 2090P Figure 5.9 Fabrication flow of imprint lithography with a photo-definition process 105

122 Figure 5.10 shows a polymer pillar with the imprinted diffractive grating feature on a photo-defined pillar structure. The imprint feature was successfully protected by the SOG layer as shown by Figure 4.8 and Figure The final pillar is 93 µm tall and 67 µm in diameter. The top indented region is: 0.5 µm in width, 0.5 µm in depth and 11.5 µm in pitch. This fabrication sequence successfully combined imprint lithography and traditional photolithography to produce fine-scale features on large-scale structures in a single process sequence with one UV exposure step. Figure 5.10 SEM of the pillar produced with SOG protection layer 5.5 Off-angle stamp fabrication and imprint Off-angle and non-symmetric structures can serve as high efficiency optical interconnects. One advantage of the developed imprint process is that these complex structures can be transferred directly from the stamp to the polymer without affecting the photo-definition of those materials, which can be employed later to fabricate waveguides. The waveguides with interconnect components at the end or on the top can be obtained 106

123 conveniently by the combining imprint lithography and photolithography. Although the optimized slope angle and dimensions for high efficiency optical interconnects are not determined yet, this work will examine the effects for an off-angle structure imprinted with an arbitrary slope angle. Figure 5.11 shows an acute angle stamp fabrication process flow by silicon anisotropic wet etching. A (100) surface orientation silicon wafer was first covered with a thin SiO 2 layer by PECVD for 20 minutes. After conventional photolithography of a photo-resist layer on top of the SiO 2 layer, a buffered oxide etch (BOE) etching step was used to pattern the SiO 2 layer. After photo-resist removal, the silicon sample with the SiO 2 mask was immersed into a 45% (wt) KOH solution at 90 C for 20 minutes. The (111) orientation slant surfaces were etched at an exact angle of After the removal of the SiO 2 mask by HF, an acute angle of silicon stamp was obtained. SiO 2 Deposit Si BOE Etch KOH Etch HF Etch Figure 5.11 SEM of the pillar produced with SOG protection layer 107

124 Figure 5.12 is an SEM picture of the acute angle groove stamp with 9 µm gaps and 11 µm spacing. Figure 5.13 is a SEM picture of the imprinted polymer which used the same imprint process as in the previous section. The slant surfaces in the imprinted polymer were smooth with only 2 to 4 slope angle deviations from that of the silicon stamp. The acute angle in the imprinted polymer is a little bit rounder than that in the silicon stamp, but the fidelity of the imprint is good considering the non-vertical geometry. These results demonstrate the capability and fidelity of the developed imprint method for off-angle structure fabrication applications. Figure 5.12 Silicon stamp with cute angle grooves 108

125 Figure 5.13 Imprinted polymer structures 5.6 Conclusions A new fabrication method has been developed that combines nanoimprint lithography and photolithography in one process. The imprint step has been used to create high quality features in a polymer while not affecting the photo-definable nature of the polymer. A spin-on-glass layer was used to protect the fine structures during photoprocessing of the polymer pillars. This fabrication method allows the production of finestructures on a macrostructure. An example of such a structure is a large polymer pillar with a diffractive grating imprinted onto it. The macrostructure and nanostructure was produced in a single process sequence with one UV exposure step. This fabrication process also demonstrated the capability to produce off-angle complex structures. 109