Electrical Overstress Course
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1 EOS Training Course Dr. Lim Soo King Dip Sc (Merit); B Sc (Hons); Dip Mgt (Dist) M Sc; PhD; MIPM Associate Professor Universiti Tunku Abdul Rahman 31 Jul 06. 1
2 Objectives of the Course Understand the phenomena of EOS. Ability to set-up an effective EOS program for the organization. To improve the cost, quality, cycle time, and reliability. To reduce customer complaint. Reduce the wastage due to EOS. Dr. Lim Soo King 2
3 Introduction Dr. Lim Soo King 3
4 Outline of the Course Introduction. Theory of EOS. Characteristics of EOS. Miniaturization of device. Device structures. Causes of EOS. Dr. Lim Soo King 4
5 Outline of the Course Failure mechanism of EOS. Theory of failure. EOS test methodology. EOS prevention Reference. JVC case study. Dr. Lim Soo King 5
6 Introduction EOS is defined as electrical overstress. Semiconductor devices have a limited ability to sustain electrical overstress. The device susceptibility to EOS increases as the device is scaled down to submicron feature size. 37% for the IC failures can be attributed to ESD/EOS events. Dr. Lim Soo King 6
7 World Revenue of Semiconductor Bil $ '86 '90 '92 '94 '96 '98 '00 '02 '05 '06 Dr. Lim Soo King 7
8 Roadmap of Device Year Channel length (µm) Equivalent oxide thickness (µm) Transistor density (cm 2 ) 6.6M 18 M 44 M 109 M 269 M 664 M Dr. Lim Soo King 8
9 Field Return Failure Mode Dr. Lim Soo King 9
10 Theory of EOS Dr. Lim Soo King 10
11 Theory of EOS Intentionally left blank Dr. Lim Soo King 11
12 Theory of EOS An EOS failure is typically catastrophic and causes irreparable damage to the device. ESD and EOS are interrelated. Device weaken by ESD would have EOS easily. It is the large scale ESD. The duration of EOS events ranges from milliseconds to seconds (typical > 50 µsec). Dr. Lim Soo King 12
13 Characteristics of EOS Dr. Lim Soo King 13
14 Characteristics of EOS Intentionally left blank Dr. Lim Soo King 14
15 Characteristics of EOS Time duration a few ns to a µs to resulting ESD. Time duration > 50 µs to < 100 µs causes junction punch through. Time duration > 100 µs causes melt metal, fused wire, and bond wire. Dr. Lim Soo King 15
16 Miniaturization of Device Dr. Lim Soo King 16
17 Miniaturization of Device Intentionally left blank Dr. Lim Soo King 17
18 Miniaturization of Device The permissible critical field strength of expitaxial layer can be only 100V depending on thickness and doping level. Shallow junction depth. Junction breakdown voltage is usually around 20V. Dr. Lim Soo King 18
19 Device Structure Dr. Lim Soo King 19
20 Device Structure CMOS output consist of p-channel and n-channel MOSFET Dr. Lim Soo King 20
21 Device Structure CMOS output consist of p-channel and n-channel MOSFET Dr. Lim Soo King 21
22 Device Structure Intentionally left blank Dr. Lim Soo King 22
23 Device Structure Power MOSFET device structure - BJT and diode parasitic components Dr. Lim Soo King 23
24 Device Structure IGBT device structure Dr. Lim Soo King 24
25 Causes of EOS Dr. Lim Soo King 25
26 Causes of EOS Intentionally left blank Dr. Lim Soo King 26
27 Causes of EOS Device designed with parasitic component which is the source of EOS. Bad fabrication control Over etch. Photo resist residue. Violation of design rule. Dr. Lim Soo King 27
28 Causes of EOS Intentionally left blank Dr. Lim Soo King 28
29 Causes of EOS No common ground test system and device. Inductive effect. Resistive effect. Improper shutdown of device Wrong power sequencing. Hot-plug the device. Dr. Lim Soo King 29
30 Causes of EOS Poor quality system. Burn-in spike. Poor specifications. Wrong orientation. PCB signal integrity. Transient overshoot and undershoot controlled within absolute max. rating. Dr. Lim Soo King 30
31 Causes of EOS Intentionally left blank Dr. Lim Soo King 31
32 Causes of EOS Noisy power source Transient spike. 5 V part with a 2.5 V spike 50% EOS. 2.5 V part with a 2.5 V spike 100% EOS. 1.5 V part with a 2.5 V spike 167% EOS. Dr. Lim Soo King 32
33 Failure Mechanism of EOS Dr. Lim Soo King 33
34 Failure Mechanisms Thermal-Induced failure Doping level. Junction depth. Device characteristic particularly dimension. Electro-migration High electric field. Migration of metal ion from high field to low field area. Dr. Lim Soo King 34
35 Failure Mechanisms Intentionally left blank Dr. Lim Soo King 35
36 Failure Mode Dr. Lim Soo King 36
37 Failure Mode Dr. Lim Soo King 37
38 Failure Mode Dr. Lim Soo King 38
39 Failure Mode Intentionally left blank Dr. Lim Soo King 39
40 Failure Mode Secondary breakdown Metallization burn Dr. Lim Soo King 40
41 Failure Mode Diffusion damage Dr. Lim Soo King 41
42 Failure Mode I/O resistor damage Dr. Lim Soo King 42
43 Failure Mode Thermal EOS base-emitter region Dr. Lim Soo King 43
44 Failure Mode Thermal EOS melt wires Dr. Lim Soo King 44
45 Failure Mode Thermal EOS latch-up Dr. Lim Soo King 45
46 Failure Mode Blown metal line Melt contact and bus Melt bond pad Dr. Lim Soo King 46
47 Theory of Failure Dr. Lim Soo King 47
48 Theory of Failure Intentionally left blank Dr. Lim Soo King 48
49 Theory of Failure Current Density High current density that melts aluminum metallization and blows gold/al bond wire. Dr. Lim Soo King 49
50 Theory of Failure - Undershoot Intentionally left blank Dr. Lim Soo King 50
51 Theory of Failure - Undershoot Simultaneous switching causing current from package, wire to be greater than forward current of diode resulting net current flow in package parasitic resistive and inductive components. This would cause the device s ground well below the system. Dr. Lim Soo King 51
52 Theory of Failure - Undershoot The voltage difference between power pin and device ground will be far exceeding its normal V CC voltage. This would cause EOS. The illustration is shown in next few foils. Dr. Lim Soo King 52
53 Theory of Failure - Undershoot Intentionally left blank Dr. Lim Soo King 53
54 Theory of Failure - Undershoot Dr. Lim Soo King 54
55 Theory of Failure - Undershoot Intentionally left blank Dr. Lim Soo King 55
56 Theory of Failure - Overshoot As illustrated in pervious graph, overshoot would result the ground of the device being shifted upward. The voltage across the device is less than V CC. Soft-bit would be resulted as a problem. Dr. Lim Soo King 56
57 Theory of Failure Latch-up This is true for CMOS and IGBT devices. It is caused by input voltage is greater than the power supply voltage by at least 0.7V. 0.7 V is the forward voltage V F of a diode. The p-channel MOSFET acts lateral pnp transistor. The n-channel MOSFET act as vertical npn transistor. These two transistors are connected as thyristor. Dr. Lim Soo King 57
58 Theory of Failure Latch-up Intentionally left blank Dr. Lim Soo King 58
59 Theory of Failure Latch-up This event creates tremendous increase of current that the power density would melt the Al metallization or blow wire. Unclean power supply voltage would cause latch-up. Noise input such as overshoot would cause latch-up. The illustration of latch-up is shown in the following foils. Dr. Lim Soo King 59
60 Theory of Failure Latch-up Dr. Lim Soo King 60
61 Theory of Failure Latch-up Intentionally left blank Dr. Lim Soo King 61
62 Theory of Failure Latch-up V BE of npn transistor > 0.7V, leakage current, latch-up occurs. Dr. Lim Soo King 62
63 Theory of Failure Electro-migration High electric field. Electro-migration forces metal ions to move downstream mainly along the grain structure. Dr. Lim Soo King 63
64 EOS Test Methodology Dr. Lim Soo King 64
65 EOS Test Methodology Purpose is to weed out the infant mortality failure due to fab, assembly, handling, etc. Applying HBM, MM, CDM, field induced model, floating induced model according to Mil-std-883 E method Burn-in or dirty burn-in according to Milstd Final test. Dr. Lim Soo King 65
66 Bathtub Curve of Device Intentionally left blank Dr. Lim Soo King 66
67 EOS Prevention Dr. Lim Soo King 67
68 EOS Prevention Intentionally left blank Dr. Lim Soo King 68
69 EOS Prevention Prevent power surge by using uninterrupted power supply. Power line of PCB should be designed not too close to prevent high induced voltage. Use isolation when necessary. Use capacitor filtering (0.01µF) connecting to the power supply of device. Dr. Lim Soo King 69
70 EOS Prevention Intentionally left blank Dr. Lim Soo King 70
71 EOS Prevention Measure the parasitic resistance and inductance of the device package to minimize voltage difference between device ground and system ground. Prevent hot-plug of device into or out of PCB or test socket. Prevent high tension inductive field such as from computer terminal. Use shielding technique to eliminate interference. Dr. Lim Soo King 71
72 EOS Prevention Intentionally left blank Dr. Lim Soo King 72
73 References ESDA S DOD-HBK-263 B. Mil-std-1686A. 883 E method Mil-std Dr. Lim Soo King 73
74 Q and A Session Dr. Lim Soo King 74
75 Intentionally left blank Dr. Lim Soo King 75
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