Kerf! Microns. Driving Forces Impact of kerf is substantial in terms of silicon usage 50 % of total thickness for 100 mm wafers
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1 2nd. Annual c-si PVMC Workshop at Intersolar NA, San Francisco, CA, July
2 Microns Kerf! Driving Forces Impact of kerf is substantial in terms of silicon usage 50 % of total thickness for 100 mm wafers Impact of kerf gets larger as wafer thickness is reduced Slice + Kerf- mm Wafer thickness - mm Kerf Loss- mm Wafer thickness roadmap - - International technology roadmap for PV Issues As wafer thickness is reduced wafer demount from slicing fixture becomes more difficult- larger breakage related yield loss Costs of wafering consumables slurry, fixed abrasive wires, coolant. fixturing Handling and processing thin wafers not easy!! 2
3 Crystalline silicon wafer value chain kerfless wafer opportunities Poly chunks Fractional distillation column for TCS production Siemens reactors Poly rods Wire saw Squarer Cropper Crystal Growth Current industry practice Thick (>150 mm) wafers Exfoliated wafers from thick wafers H implant Stress induced exfoliation Epitaxy on porous silicon-exfoliation Direct production of shaped crystals from the melt Silicon ribbons Wafer casting Direct wafers 3
4 Direct production of silicon sheets, ribbons from the melt The Edge Defined Film fed Growth (EFG) process and the string ribbon process were the first technologies to have been developed for the kerf free production of wafers. Neither technology met the cost, efficiency and productivity goals and were not competitive with conventional ingot based processes. These technologies have been have been discontinued 4
5 EFG process was in development for over 15 years the longest running technology development effort for a kerfless approach 5
6 Exfoliation Approaches Implant hydrogen into silicon wafer. Exfoliate thin sheets at hydrogen induced microvoids Micro voids Hydrogen ç ç ç ç ç ç ç ç ç ions ç ç ç ç ç ç ç Substrate Substrate Epitaxial growth of thin (~ 50 micron) silicon layers on porous silicon followed by exfoliation at the porous layer Porous silicon Epitaxial layer Substrate Substrate 6
7 Efficiency - % Driving Forces for Epitaxial wafers Polyless, ingot less, kerfless! Thin wafers (thicknesses of ~ 50 microns - sufficient thickness for maximum theoretical efficiency) can be produced Wafer thickness - microns >50 microns Throwing away Silicon <50 microns Throwing away red light Any wafer thickness/size possible Broad range of dopant concentration Very uniform dopant incorporation across and through thickness of the wafer Feasibility of forming in- situ junctions during epitaxy No oxygen in the wafers 7
8 History Early work by Cannon for manufacturing SOI wafers involving porous silicon, epitaxy, wafer bonding and layer transfer Handle wafer Epitaxial device layer Porous Silicon SiO2 Silicon substrate Cannon scaled the technology to 300 mm. However did not meet cost, quality and commercial requirements and the technology was discontinued. Epitaxial wafers for solar are based on the Cannon approach with individual variations by different organizations 8
9 Engineering porous silicon Low porosity layer consolidates into single crystal sheet to enable epitaxy Low porosity layer Epitaxial layer High porosity layer Si substrate H anneal 1100 C Si substrate Hydrogen anneal at elevated temperature in epi reactor prior to silicon deposition High porosity layer consolidates into voids to enable exfoliation 9
10 Cross section of textured epitaxial film, porous Si and silicon substrate ~3-4 mm Textured surface Epitaxy ~ 49 mm Epitaxial layer Porous Si Substrate Si Substrate {111} facets on the surface by anisotropic etching for light trapping only possible with {100} oriented single crystals. Oriented, single crystal epitaxy on porous silicon is readily achieved as evidenced by the texturing 10 and XRD.
11 High efficiency Thin, epitaxial Si solar cells (ISFH) Free standing Prog. Photovolt: Res. Appl. 2012; 20:1 5 11
12 Epitaxial Wafers Barriers to Mainstream Manufacturing Custom designed epitaxial reactors no equipment manufacturing capability today. Scaling and capacity addition are major issues Porous silicon formation by anodic etching requires highly boron doped ( ~ e18 atoms/cc) wafers with typical thicknesses of ~600 to 1000 mm to enable multiple reuse of the substrate to achieve cost goals. Such wafers are not common commodities (unlike lightly doped solar wafers)- cost, supply line issues future vertical integration? Substrate wafers have to be reused multiple times ( 50 to 100) to achieve cost goals Consumables use, energy use, cost, availability gases ( Tri Chloro Silane, Hydrogen), chemicals ( HF, solvents), replacement parts (E.G graphite components of high temperature tools such a epitaxial reactors), chamber clean issue, etc. have to be addressed Different approaches for dealing with very thin wafers are being investigated with no clear cut winner Potential reliability issues with very thin ( ~ 50 mm) solar cells. 12
13 Metrology Challenges A fast, accurate approach for characterizing surface recombination velocity. This becomes particularly important as wafer thickness is reduced A reliable method for differentiating bulk recombination from surface recombination Method for characterizing light trapping effectiveness for various approaches to light trapping Mechanical property characterization of thin wafers fracture strength, time induced crack propagation, etc. 13
14 Emerging Crystalline Si PV technologies Barriers/Challenges Technology readiness Data on critical issues such as process consistency and repeatability, yields, tool uptime and reliability, costs of consumables needs to be available Cost models fail to account for all costs unanticipated costs when scaled Transition from R&D into manufacturing Unrealistic Expectations Lack of manufacturing experience and knowledge Premature transition into pilot production/manufacturing Equipment Purpose built, one of a kind equipment is the hallmark of all kerfless wafer technologies. ( true for all new PV technologies!) E.G. high energy ion implanters, epitaxial reactors, MOCVD tools (compound semiconductors), handling equipment for very thin wafers Supply line Frequently overlooked in planning Unanticipated supplier problems- sole source, costs above expected, quality and delivery issues, unique materials or processes increase costs and risk Capital Probably one of the biggest barriers of all. Competitive position with incumbent technologies, bankability Markets, customers Time to market, customer acceptance, competitiveness, reliability, security of supply, scaling
15 Conclusions: Kerfless wafer production has been a long standing desire of the silicon PV industry Several technologies have been developed and abandoned over the years Complexities of new technologies and the relentless progress of the incumbent technology has prevented any alternatives from gaining a foothold Opportunities for kerf less processes still exist but one needs to go beyond hope, hype and vision Vision without Execution is Hallucination! Thomas Edison 15
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