3D technologies for integration of MEMS

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1 3D technologies for integration of MEMS, Fraunhofer Institute for Electronic Nano Systems Folie 1

2 Outlook Introduction 3D Processes Process integration Characterization Sample Applications Conclusion Folie 2

3 Introduction New applications / different functionalities / interaction with the environment driving factors for Smart Systems / MEMS Memory Interposer / substrate passives Logic Hetero-Integration: lateral vertical (3D) CEA LETI Examples for Smart Systems using MEMS Why going 3D? Hetero Integration of different functionalities System-size, short signal paths, (costs) Better system-performance Reduced size through vertical (3D) Integration CEA LETI Folie 3

4 3D Integration for MEMS 3DIC Challenges compared to 3DIC Different functionalities (optics, mechanics, fluidics) Material compatibility (Si, glass, ceramic, polymers, Me) Samsung (16Gbit DRAM) Additional requirements: e.g. hermiticity Different technologies, sensible components High Aspect Ratio (HAR) Trough Silicon Vias (TSV) with large dimensions (400 µm x µm) IBM (TSV in 32nm CMOS) MEMS TSV Typical MEMS with comb structures Principle of integrated MEMS (Sensor + ASIC as cap) CMOS based Image detector with HAR TSVs Folie 4

5 Through Substrate Vias (TSV) Via drilling Dry etch Process ( Si-Wafers ) Deep reactive Ion etching (DRIE) using the BOSCH process Wafer sizes: mm Etch rates: 0,5 10 µm/min Very HARs possible (20 and more) 80 µm 4.2 µm Wet etch Process ( Si / glass ) KOH-Chemistry for Si-wafers Low ARs and larger foot prints HF-Chemistry for FOTURAN glass Photo patterning, HARs Alternative Processes LASER drilling Erosion / powder blasting 340 µm 420 µm 3.9 µm 212 µm 1250 µm 350 µm Folie µm Different TSV profiles etched by DRIE (AR= 5 15) 40 µm 90 µm V-grooved TSV in silicon etched by KOH TSV in FOTURAN by photo-patterning + HFetching (AR=3-4) TSV in glass drilled by powder blasting HAR High Aspect Ratio

6 Through Substrate Vias (TSV) Conductive filling Metallization processes Physical vapor deposition / Sputtering (PVD) Chemical vapor deposition ( CVD ) Electrochemical / Electroless deposition ( ECD / ELD ) Atomic layer deposition ( ALD ) Electrografting ( EG ) Liquid metal fill PVD for TSVs with low AR (<3) PVD for V-Groove-TSV Printing head PVD for Interposer Alternative methods Printing&Sintering of conductive pastes (e.g. Aerosol, inkjet, screen printing) Carbon Nano Tubes (CNT) growth or application of a CNT-dispersion Folie 6 Chip Aerosol jet: Substrate Printed Interconnect Printing across topography Vias with CNTs for on chip interconnects (TSV in development)

7 Through Substrate Vias (TSV) CVD + ECD Copper CVD for very HAR (up to 20) Examples of Cu-MOCVD for TSVs MOCVD using CupraSelect TM pre-cursors Parameters: T = C / p = 1 20 Torr 220nm 100% Adaption regarding layout and TSV geometry 220nm Seed layer for electroplating 100% 15 x 1 µm Complete fill for small TSV (diameter < 5 µm) TiN-based barrier / adhesion layers by CVD Seed layer (AR=8) 215nm 98% Filled TSV (AR=15) Electrochemical / electroless deposition (ECD / ELD) Thick metal layers (Cu, Ni, NiP, Au, Sn, Pd) Low process complexity/-temp/-times/-costs Applications besides TSV metallization: Folie 7 Redistribution layer (RDL) Bond metallization (Cu-Cu, Cu-Sn) Under Bump metallization (Cu-Ni-Au) Examples of Cu-ECD for TSVs Bottom-up process 60 µm² x 220 µm (AR: 3,5) Conformal ECD for partial filling 80 x 420µm (8µm Cu) (AR=5)

8 Waferbonding Method selection for 3D integration Requirements for 3D integration Low temp. (<400 C) + material compatibility Mechanical stability; hermetic sealing Realization of electrical contact proper selection of suitable methods: Thermo compression Al -Al Au-Au Cu-Cu Ti-Si Si + metal Eutectic Bonding Au-Si Au-Sn Cu-Sn-Cu Reactive bonding Si + metal Direct Copper to Copper bonding Thermo-Compression bonding method Inter-diffusion+ common grain growth Compatible to Cu-TSV technology Process: Pre-treatment 15 kn, <400 C, 60 min High shear strength; hermetic sealing Solid-liquid interdiffusion (SLID) Bonding Inter-diffusion + formation of inter-metallic phases (e.g.: Cu 3 Sn, Cu 6 Sn 5 ) Suitable for Cu metallization and Cu TSVs Materials: Cu-Sn-Cu, Au-Sn-Au, Cu-In-Cu Folie 8 Process: Pre-treatment 3 bar, <350 C, 10 min Low temp. (200 C) possible Si + metal Cu-Cu Interface Cu Wafer 1 Wafer 2 Cu 3 Sn Cu 6 Sn 5 5 µm Si Cu-Cu bond interface (FIB + EBSD ) Cu-Sn-Cu bond (SEM + EBSD )

9 Waferbonding Using nano-scaled material systems that exhibit heat in a self-propagating reaction heat-source for bonding (e.g. SLID bonding) Very low temperature impact on substrate Very quick bonding method (<1s) Bonding process Using standard bonding tools Initiation of reaction e.g. by el. impulse Example results for reactive multilayer bonding Substrate A Au Sn 1) 2) Reactive bonding Schematic of working principle: 1. Applying reactive system 2. Bonding process through ignition 0 µs 100 µs 200 µs Multi layer 1 µm 1 µm Substrate B Au-Sn: Before bonding (left) and after bonding (right) Ceramic-Covar (TO-package) 300 µs 400 µs 500 µs 600 µs 700 µs 800 µs High speed imaging Velocities up to 50 m/s 2 mm Folie 9

10 Process integration Technology approaches Approach A TSVs before thinning 1. TSV etch 2. TSV fill+ RDL Approach B TSVs after thinning Back side RDL/ bond frame Wafer Bonding 3. Front side passivation 3. Thinning 4. Thinning 4. TSV etch 5. Back side RDL / bond frame 5. TSV Isolation Folie Wafer 6. Bonding TSV fill + RDL

11 Process integration A: TSV before thinning 1.? TSV depth variations B) TSV reveal by planarization TSV etch TSV fill+ RDL Front side passivation Wafer thinning Back side RDL / bond frame Folie 11 Wafer Bonding TSV-Reveal options A) B ) C ) Patterned Si-etch Planarization TSV protrusion TSV-embedding in oxide Planarization Ring type TSV Partially filled TSV C) TSV reveal by protrusion Si-spin etching SiO 2 CMP Backside- RDL

12 Process integration B: TSV after thinning 1. Most critical steps for this approach TSV-etching: notching effect (due to required over-etching at center) Oxide etch: opening oxide at TSV bottom leave oxide at top/side walls Si-DRIE Notching effect Wafer Bonding TSV Etching (DRIE) Thinning TSV etch HF vapor etch of th. SiO 2 SiO 2 deposition (TEOS Ozone) SiO 2 - RIE Top+ sidewall damage TSV Isolation 5. Folie 12 TSV Metal + RDL Contact opening: SiO 2 etch (RIE) Remove Residues at the bottom Silicon Th. SiO 2 PECVD SiO 2 Resist Cu-RDL

13 Process integration A+B: Comparison Approach A: TSVs before thinning High temperature processes possible (thermally grown oxide) TSV-etch depth variations lead to unconnected TSVs at wafer edge Wafer center Cu RDL Cu (TSV) Approach B: TSVs after thinning Wafer edge TSV-etch leads to undercut / notching Compensated by conformal processes (TEOS SiO2, CVD TiN/Cu) High yield of TSV front to backside connection Cu RDL Cu (TSV) Cu ECD SiO 2 front side MOCVD TiN SiO 2 (TEOS) Folie 13

14 Characterization Electrical measurement Test Pattern for Electrical Characterization A) Van der Pauw (single TSV) B) TSV Chain (4, 20, 50, 100, 200) C) References (line resistance, Kelvin) D) Comb structures (isolation meas.) E) EM test structure Electrical Characterization Single contact: (calc.: 4 mω) Folie 14 R=10 mω 4-contact chain: R=76 mω (calc.: 42 mω; incl. line resistance) R [mohm] Test patter for electrical characterization Ring-TSV: 80 µm 360 µm deep Wafer edge 10 mω # of TSV TSV-Resistance (Ring type TSV; approach A)

15 Sample applications Hermetic integration MEMS RF-switch for satellite applications RF-Relay sealed with glass cap and TSV-backside contacts TSVs with Al or W metallization Using high resistivity substrates and glass caps as well as TSVs with smooth sidewalls reduced insertion loss (-1,03 26 GHz) RF-MEMS switch for satellite applications: Simplified sketch RF-Measurements Hermeticity testing using Si-membrane Membrane deflection indirect measure for leakage Cu-TSVs before wafer bonding Thermo compression (Cu-Cu) bonding under vacuum Folie 15 Backside wafer thinning + TSV reveal Test patterns for electrical measurement Membrane wafer for hermeticity testing TSV patterns for electrical Measurement X-Ray CT image membrane Cu-Cu Bond TSV TSV reveal at the wafer backside

16 Sample applications M(O)EMS using glass cap Applications that require transparent caps for optical sensing or optical alignment Implementation of Through glass Vias (TGVs) Glass cap wafer Sensor SOI-wafer TGV Sketch of a M(O)EMS using glass cap with TGVs Systems using standard glass (e.g. BSG) Through glass via (TGV) by LASER, sand blasting, wet/dry etching mostly lower aspect ratios Anodic direct bonding to silicon Metallization e.g. via PVD Inertial MEMS Glass wafer (BSG) Silicon wafer Anodic bonding of BSG to Si FOTURAN glass for HAR TGVs Photo patterning and wet etching of TGVs Bonding to Silicon: critical temperature regime (very slow heating/cooling; max. 200 C) Folie 16 Further processes: TSV metallization/ Si-thinning FOTURAN glass: Si-glass compound 115µm 570 µm FOTURAN Silicon 100µm 350 µm 1250 µm TGVs with Cu-CVD metal

17 Contact us BOOTH # Fraunhofer ENAS Dept. Back end of Line Technologie Campus 3 D Chemnitz Phone: Fax: lutz.hofmann@enas.fraunhofer.de Thank you for you attention! For further information please visit Booth or refer to: Fraunhofer ENAS in Chemnitz (Germany) lutz.hofmann@enas.fraunhofer.de Folie 17

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