NiPt salicide process improvement for 28nm CMOS with Pt(10%) additive

Transcription

1 NiPt salicide process improvement for 28nm CMOS with Pt(10%) additive Jerander Lai, Yi-Wei Chen, Nien-Ting Ho, Yu Shan Shiu, J F Lin Shuen Chen Lei, Nick ZH Chang, Ling Chun Chou, C C Huang, and J Y Wu United Microelectronics Corp., No 18, Nanke 2nd Rd. Tainan Science Park, Tainan County, 741, Taiwan Tel: Ext: 12502; Fax: ; jerander_lai@umc.com Introduction Nickel Silicide (NiSi) is one of the popular silicide candidates for advance CMOS because of its low resistivity and low silicon consumption characteristics, but poor thermal stability is the drawback. Pt impurity in NiSi process has been reported to improve NiSi thermal stability [1-5]. R.N. Wange et al. proposed that Pt additive could reduce the driving force of delta Gibbs free energy and increase the interfacial energy from the NiSi orientation change of MnP-type structure to P63/mmc [1]. Takao Marukame et al. addressed that the additive Pt could grow thin PtSi layer around NiSi/Si interface to inhibit the migration of Ni atom to Si [2]. Additionally, they also demonstrated dipole comforting Schottky junction of Ni(Pt)Si/Si for extremely low interface resistance by forming PtSi interface in both As and B atoms dopant. This study successfully demonstrates 50~80% NiSi defect reduction and P-FET 3% device gain improvement on 28nm node by using Pt (atom. 10%) additive in NiPtSi silicide process. Additionally, thermal stability improvement was typically discussed in higher temperature range from 650C to 900C, and the stability was generally shown in Rs-temperature diagram and NiSi defect reduction. Here we discovery some NiSi characteristic changes with higher Pt % additive in lower annealing temperature (<270C), and the results show that lower thermal budget is required to get same NiSi thickness and better Rs distribution with higher Pt% additive. P. 1

2 Experimental and Metrology Experimental Silicidataion was done on P-type Si and 28nm structure wafers. Two different Pt% additives of NiPt, 5 atom% and 10 atom%, with various thicknesses were sputtered on the substrates. Silididations were done following the sequences shown in Figure 1. P-type Si NiPt /TiN RTP (<270C) Strip: SPM P-type Si NiPt /TiN RTP (<270C) Strip: SPM 28nm NiPt /TiN RTP (<270C) Strip: SPM Metrology Semiquantitative analysis of EDS (Energy Dispersive Spectrometer) scanning was applied to draw the depth profile of Ni/Si ratio of that was assisted with GIXRD (Glancing Incidence X-ray Diffraction) to check Nickel silicide phase. Electron beam inspection (EBI) was implemented after contacts formation on 28nm structure wafers to identify Bright Voltage Contrast (BVC) defects that are highly correlated NiSi defects [6]. EDS scan GIXRD Figure 2 Figure 3 (a) RTP2 (>400C) EDS scan X-TEM Figure 4 Figure 5 (b) MSA CONTWCMP EBI WAT Figure 7 Figure 6 Figure 8, 9 (c) Figure 1 Experimetal process flow P. 2

3 Characteristics with Pt additive The depth profile of Scanning EDS showed higher Ni/Si ratio but thinner silicide with NiPt(10 atom%) additive (Figure 2) after RTP1 (<270C) annealing and SPM stripping (Figure 1a). Ni3Si phase was found with GIXRD analysis (Figure 3) Figure 2 EDS scan; More Ni rich silicide was formed with NiPt 10 atom% additive after RTP1 annealing. Figure 3 GIXRD; Ni3Si phase was found in NiPt (10 atom%) split after RTP1 annealing P. 3

4 Characteristics with Pt additive Figure 4(a) EDS scan; NiPt(10 atom %) performed sharper NiSi/Si interface after RTP2 Figure 5 XTEM images after >400C annealing; (a) NiPt(10%) gets uniform NiSi/Si interface image. (b) NiPt(5%) Figure 6 NiPt(10 atom%) splits show better Rs distribution on 28nm structure wafers NiPt(10 atom%) showed thicker NiSi and sharper NixSiy profile at Ni/Si interface (Figure 4a) after RTP2 (>400C) annealing (Figure 1b). The sharper interface indicated that uniform Nickel-monosilicide was formed at the interface and the XTEM images (Figure 5) proved it. Additionally, better Rs distributions on 28nm node structure wafers were found among NiPt (10 atom %) with different NiSi thickness splits (Figure 6). It is suspected that sharper interface and uniform Nickel-monosilicide phased was formed by using Pt(10 atom %) additive NiPt P. 4

5 NiSi defect reduction Figure 7 NiPt(10%) got 50~80% NiSi defect reduction Figure 4(b) EDS scan; More Pt species piling up at silide/si interface Figure 8 NiPt(10%) performed lower and better distribution in SRAM bulk leakage The BVC data inspected with EBI after contact process showed about 50~80% NiSi defect to be reduced (Figure 7), and better SRAM bulk leakage, lower and tighter distributions, was performed after increasing Pt additive from 5 atom % to 10 atom % (Figure 8). The reasons were proposed by Takao Marukame, et al. [2] that some Pt species piling up at bottom of silicide which can suppress Ni migration to Si and get better thermal stability P. 5

6 P-FET performance improvement Figure 9 NiPt(10%) had 3% device gain improvement on P-FET Device Ion-Ioff performance can be improved by reducing Schottky barrier height (SBH) [7] which is dependence on the metal work function. Pt (5.12~5.93 EV) has higher work function than Ni (5.04~5.35 EV) [8], it s positive for P-type Si to improve P-FET device performance. Figure 9 showed there was about 3% P-FET performance to be improved by using NiPt (10 atom %) on 28nm node. P. 6

7 Conclusions and reference Conclusions Nickel Silicide is popular for advance CMOS process because of its low resistivity and low silicon consumption characteristics, but poor thermal stability is the drawback. This study highlighted that NiSi thickness is increased by increasing Pt% and successfully demonstrated the thermal stability improvement, 50~80% NiSi defect reductions and lower SRAM bulk leakage, by using 10 atom % Pt additive of NiPt alloy. Additionally, this study also demonstrated 3% P-FET device gain on 28nm node. Finally, NiPt with 10 atom % Pt additive can be concluded to own many benefits for Nickel salicide process. References 1. R.N. Wange, etc. Applied Surface Science 207 (2003) Takao Marukame, etc. Electron Devices Meeting, IEDM 2008., pp Yifei Huang, etc ICSICT '06. 8th International Conference on, pp. 475-p477 4.L. J. Jin, etc. Journal of Applied Physics Volume: 98, Issue: 3,(2005) pp D. Z. Chi, etc. Junction Technology, IWJT '04. pp Kirin Wang, Hermes Liu, J.H. Yeh, Mingsheng Tsai, Post-WCMP Leakage Detection and Monitoring on 65-nm Devices Using an Advanced e-beam Inspection System, Semiconductor Manufacturing, P. 7

8 Thank You! P. 8