3D technologies for More Efficient Product Development

Transcription

1 3D technologies for More Efficient Product Development H. Ribot, D. Bloch, S. Cheramy, Y. Lamy, P. Leduc, T. Signamarcheix, G. Simon Semicon Europa, TechArena II, 09 October 2013

2 Photonics in Product development: Fiber To The Curb? Fiber To The Building? Fiber To The Best Place! Fiber To The Home? Fiber To The Board Fiber To The Si Interposer? 2

3 3D technology in Product development: 3D To The PCB 3D To The chip 3D To The Best Place! 3D To The Package 3D To The IC 3D To The Transistor 3

4 Product can emerge from just a few technology BBs DIABOLO concept for Smart Fabrics Top cover Components (active chip) UHF RFID device with a 15cm antenna length connection Leveraged 3D process - WL grooves deep etching - WL alignment / bonding - WL bumping/ grinding One dimensional approach in order to be thread compatible First applications : RFID and LEDs PASTA European Project MiNaPAD Forum 2012 J Brun 4

5 External Quantum Efficiency [%] Product can emerge from just a few technology BBs 4-junction solar cell GaAs GaAs GaAs 4J InP InP InP InP 100 lot10b-03-x04y Wavelength [nm] 4-junction solar cell for Concentrated Photovoltaïc Epitaxy limitation Direct bonding of Semiconductors (DSB) takes over 44,7% efficiency measured Potential for > 50% efficiency 5

6 Product can emerge from just a few technology BBs Innovative Power Converter Leveraged 3D processes Temporary bonding WL grinding, copper CVD Direct Cu on Cu Bonding First demonstration of power module integration Under progress: nmos/pmos and diode/pmos integration A Vertical Power Device Conductive Assembly at Wafer Level using Direct Bonding Technology, L. Banaissa et al, ISPSD 2012 True 3D Packaging Solution for Stacked VerticalPower Devices», N. Rouger et al, ISPSD

7 Use 3D and smart interposer for more compact Product Ultra compact 60 GHz Transceiver 6,5x6,5mm² interposer: 3 times smaller than state of the art (STm, Image, Hittite) 6,5mm Excellent thermal dissipation Silicon Interposer 12mm Integration of 60GHz IC transceiver High performance antennas on Si Interposer 7Gbps, BER~10e-5, 1m wireless link between 2 Si interposers Silicium L. Dussopt et al. LETI Innovations days

8 Use TSV for low power and high bandwidth memory to logic connections TSV s : Ø 10 μm, AR 8, Pitch 40 μm, Number 1016 Chip to Chip Cu Pillars : Ø20 μm, Height 20 μm, Pitch 40 μm, Number 1016 SoC to Substrate Cu Pillars : Ø55 μm, Height 40 μm, Pitch >200 μm, Number 933 Si - Wide I/O Memory Wide IO : 4X power reduction TSV 80µm Si - SoC Cu Pillar Dutoit et al., VLSI Circuits

9 Use Passive interposer for High Performance Computing Products chip : Process development 200mm Test vehicule 100um thickness - 680mm² HD Silicon interposer 4 chips - Si interposer -BGA 2013 : Process development 300mm Demonstrators MPW 80um thickness 420mm² Si 100µm Si Chip Si-IP Cu Ni SAC Solder TSV AR 8-10 Copper Cu pillars 50µm pitch Routing: 4 x layers Damascene thick copper 1.4μm L/W 0.5/0.5μm Chip 2 Chip 1 Organic package Chip Si-IP K. Miyairi et al. IMAPS San Diego 2012 J. Charbonnier et al., ESTC Amsterdam

10 3D IC Technologies for Advanced Computer Architectures Top dies: x~9 28 nm; 16 mm² Many-core compute fabric Interposer: 65 nm, ~160 mm² Interconnect hub with test & DFT architecture 3D enablement designs: micro-buffers, serdes, ESD, power management Computing dies: many-cores with 3D adaptations Tap controller High Speed links: NoC Routers Serial, parallel Repeaters Active interposer with 3D enablement designs Memory die: Wide IO (optional) Leveraged 3D Technologies: 3D design flow : partitioning, design, simulation, DFT High density 3D interconnects (10 to 20µm pitch) Architecture paradigm for next generation computing Scalability is key : simple core, more cores Active interposer will offer high performance core-to-core connections 10

11 FASTEST PACED R&D is still slower than DONE R&D Integrate «off the shelf» 3D building Blocks into Product development for improved TTM 11

12 Anticipate on Technology Building Blocks Focus on BB that can make a difference on future products: IP, performance, cost, yield, TTM. Increase Maturity level of technology BBs before attempting their integration into complex assembly flow. 12

13 Technology Building Blocks that make a difference Direct bonding for advanced substrates Smart Stacking TM with oxide layer bonding Smart Stacking TM with metallic layer bonding bonding with Cu, W, Ti plain metal layers has been demonstrated Low temperature direct bonding 3D Stacking Technologies for high density device integration, L. Di Cioccio et al, 224th ECS Meeting, 2013 The Electrochemical Society 13

14 Technology Building Blocks that make a difference Technology for very low Pitch interconnection High volume manufacturability (HVM) (300mm compatibility, high speed P&P) Cu pillars TLP(Cu/Sn) Advanced technologies Pre-applied underfill Potentially 1fF Si Cu Current technologies Room T Insertion Si SiO 2 Direct bonding WtW or DtW µm range 30-5 µm range Down to 1µm 14

15 Technology Building Blocks that make a difference Room T Insertion for ULTRA low Pitch interconnection Bonding force T amb Features: 10µm pitch Room temperature No flux Pre-applied underfill capability Good throughput Connect. Yield Shorts CH103 Mean R. = 183 m W Rmin (m W) Rmax (m W) 100% 0% Force 8 mn Connection yield (%) Good yie ld 100% connected cells AlCu cap e1=300 nm WSi core 10µm Al 0.5Cu microtubes: - 2.2µm high nm AlCu thickness Al 0.5Cu pads: µm in diameters, µm in thickness ECTC 2013, F. Marion et al 15

16 Technology Building Blocks that make a difference Direct Bonding for ULTRA low Pitch interconnection Si Cu Si Direct bonding WtW or DtW Composite Cu/SiO2 interface SiO 2 SEM of bonded patterned structure (hybrid oxidemetal) at 400 C 14µm pitch along x 7µm along y Post bonding annealing Min (Ω) Max (Ω) Average resistance (Ω) DC5 Standard deviation (%) 400 C for 2h transmission electron imaging of the copper pad bonding Perfect ohmic contact: 22.5mW.µm2 (Equivalent to bulk copper) Measured resistance of interconnect daisy chain: 88.5% yield, 1,2% standard deviation Roadmap to Pitch lower than 2 µm, In Progress 200 C direct bonding copper interconnects : Electrical results and reliability, L. Di Cioccio et al, IEDM

17 Technology Building Blocks that make a difference Back to Face interconnection BCB or DAF or PI* Die To wafer bonding LTO PECVD SiO2 insulation PVD Ti/Cu seed layers High thickness negative photoresist ECD Cu Electrical Test on daisy chains 1000 cycles -40/+125 C TC *DAF= Die Attach Film, PI= Polyimide ECTC 2013, G. Pares and al 17

18 Technology Building Blocks that make a difference Temporary bonding optimization Zone bond Vs. Wafer Support System Optimize material & process choice as a function of overall integration scheme ECTC 2013, A. Jouve et al 18

19 Technology Building Blocks that make a difference Innovative characterization In operando analysis in SEM of failure mechanism of 3D interconnexion caused by electromigration: identification of interconnection weak point RDL not TSV was identified as the weak point e- TSV (seen from the top) Weak interface, growth mecanism, voids agregation, displacement of metal are monitored in real time! RDL 3 lacunes t 66 h t 160 h t 300 h t 400 h t 590 h First in Operando SEM Observation of Electromigration-Induced Voids in TSV Structure, S. Moreau et al, ISTFA 2013, 19

20 Conclusion: Path to widespread adoption of 3D technology into Products Prove competitive advantage of 3D over incumbent technologies Have Product Architect verify where 3D technology makes sense Initiate 3D BBs development ahead of Product Development Accelerate New Product Creation Process (from design to process and test) for industrial partner by using mature 3D BBs, when possible Increase /maintain 3D BBs maturity by: Testing for robustness before and after integration Conduct process integration on test vehicles to improve yields Shift from «3D Toolbox» to «3D Know-How» 20

21 Thank you for your attention