Thin Wafers Bonding & Processing

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1 Thin Wafers Bonding & Processing A market perspective 2012

2 Why New Handling Technologies Consumer electronics is today a big driver for smaller, higher performing & lower cost device configurations. These new options, in turn, are pushing demand for thin (< 100 µm) and even ultra-thin semiconductor wafers (< 40µm) for: Reduced thickness and package Better heat dissipation for thermal management Increased TSV density But as wafer thickness decreases to 100µm and below, manufacturing challenges arise: Wafers are less stable Wafers are more vulnerable to stress Dies can warp & break Special thin wafer handling processes (such as temporary bonding) are thus necessary

3 Thin Wafer Applications HBLEDs Interposers Photovoltaic Power Devices THIN WAFERS MEMS RF 3D Stacking of memory, logic CMOS Image Sensors

4 Thin Wafer Roadmap TODAY (2012) TOMORROW (2017) MEMS substrates µ MEMS capping µ ASIC MEMS µ CIS Packaging 200µ CIS BSI <10µ MEMS substrate MEMS capping ASIC MEMS CIS Packaging CIS BSI 150µ 50µ 100µ 75µ 3µ Memories µ Memories 25µ Logic 300µ Logic 200µ Power Devices 75µ Power Devices 30µ RF Devices 300µ RF Devices 50µ LEDs 100µ LEDs 80µ PV µ PV µ

5 Thinned Wafers vs. TOTAL Number of Shipped Wafers By 2017, we estimate the ratio of THIN wafers vs. TOTAL number of wafers (in 300 mm eq.) to be 74%. Ratio Thinned Wafers/TOT IC Wafers (300 mm eq.) 80% 70% 60% 50% 40% 30% 20% 10% Thinned Wafers vs. TOTAL IC Wafers (300 mm eq.) 2011 vs Forecast comparison 0% Est 2012 ratio for thin wafers 39% 43% 47% 53% 61% 69% 74% CAGR 14%

6 Thin Wafer Shipment in 300 mm Eq. Memory and logic wafers account for the largest segment of thin wafer shipments: in 2017, we estimate the ratio to be 76% Thin wafers shipment forecast in 300 mm eq. Wafer shipment in kuints (300 mm eq.) Interposers 70,8 207,3 507, , , , ,9 LED 1 226, , , , , , ,1 RF 275,9 297,6 318,7 340,6 362,6 394,7 410,8 Power 3 380, , , , , , ,6 Logic , , , , , , ,0 Memories , , , , , , ,0 CIS 1 570, , , , , , ,2 MEMS 1 114, , , , , , ,3 CAGR 83% 22% 7% 11% 9% 28% 18% 18%

7 Thin Wafer Shipment Forecast by Wafer Diameter Forecast in k units 12 wafers will account for the largest share of thin wafers (memory & logic application). By 2017, it will be 56% of total thin wafers (in units) Thin wafers forecast in kunits kunits " " " " " CAGR 22% 16% 15% -16% 2%

8 2011 Wafer Size Breakdown by Wafer Thickness Percentage in number of wafers 2011 wafer shipment by wafer size/thickness TOT ~38,390k Wafer shipment (kuints) TOT ~14,749k TOT ~306k TOT ~2,334k 0 <10µ 10 99µ µ 200µ+ 12" " " < 5"

9 2017 Wafer Size Breakdown by Wafer Thickness Percentage in number of wafers 2017 wafer shipment by wafer size/thickness TOT ~103,447k Wafer shipment (kuints) TOT ~16,745k TOT ~5,539k TOT ~2,158k 0 <10µ 10 99µ µ 200µ+ 12" " " < 5"

10 Thin Wafer Processors Production Volume (> 10k WSPY) > 1M WSPY 500k WSPY 100k WSPY < 50k WSPY MEMORIES LEDs MEMS POWER 3D WLCSP 3DIC INTERPOSERS

11 Example 1 Discera generation comparison - Temporary bonding is now used There are major differences between both generations: 1. TSV connection from the bottom 2. Si fusion bonding (instead of glass frit with seal ring ~200µ) 3. Temporary bonding step for TSV wafer thinned down 106µ

12 Example 2 Power Semiconductor Devices Power semiconductor devices PIN Diode Schottky diode Power MOSFET FET IGBT BJT Thyristor: TRIACS No thin wafer No thin wafer Thin wafer required JFET HFET Thin wafer required No thin wafer No thin wafer No thin wafer Thin wafer required (but R&D only 2012) IGBT has been developed to combine the advantages of both power MOSFET and BJT

13 Thin Wafer for Power at Renesas Trench-filling epitaxial technology, ultra-thin wafer process technology and space-saving packaging yield more compact systems with high efficiency

14 Example 3 Thinning, an Enabling Technology for 3D ICs Wafer technology: - Substrate: Silicon, SOI? - Thinning: Grinding, CMP and plasma technologies - Handling: how to handle wafer/dies as thin as 15 µm? Is a hard wafer carrier solution is required? Thickness Budget < 1 mm DRAM & NAND memory New materials: - High viscosity underfiller - Thermal management - New dielectrics Logic embedded Substrate interposer: - Silicon interposers? - Embedded components & passives? Via last (in BE) or Via first (in FE)? Via specifications depend on application: - Diameters: from 5 to 100 µm - Depth: from 10 to 100 µm - Via densities: from 10 2 to >10 5 holes / chip 3D Vias making: - Drilling: Laser or DRIE? Profile control, high etch rates - Filling: Cu, W, PolySi, conductive polymers - Coating: conformal coatings for seed layers, film isolation - Electroplating speed requirements to meet Bonding technology: - Technology: Metal Thermo compression, Direct Oxide (SiO 2 ), Adhesive bonding - Integration scheme: C2C, C2W or W2W? Face to face or face to back? YIELD & TEST issues - Accuracy: high throughput C2W equipments is are required to bond at ±1 µm accuracies - How many dies to stack?

15 Why Temporary Bonding? Temporary (de-)bonding drivers Thinning and back side processing of wafers: vertical integration High topography wafers Double-side processed Handling delicate thin wafer Advanced Packaging 3D stacking: High density of integration Reduced package size (< 100µm) TSV pitch & diameters Aspect ratio drives wafer thickness MEMS Reduce total package size of the device HBLED Protect front side structure for wafers that are double-side processed Power devices Reduced resistance Functional integration increased RF devices

16 Applications of Bonding / Debonding for Wafer Level Packaging Wafer-Scale Applications / Platforms Wafer-Level Electrical Redistribution Wafer-Level Interface / Encapsulation Flip-chip & Wafer-Level Stacking / Integration WL-CSP Fan-in FO-WLP Capping Optics Fluidic Embedded 3D IC Si on Si IC in PCB / TSV flip-chip fcbga Courtesy of DALSA Only debonding from metal carriers (ewlb by Infineon) as of D capping and packaging with TSV Permanent bonding for CIS and MEMS Packaging Thin Wafer Handling Needed Temporary bonding and de-bonding

17 Thin Wafer Handling Solutions Thin wafer handling With carrier Without carrier With intermediate layer Without intermediate layer Adhesive tape Temporary bonding/debonding Mobile Electro Static Wafer Nitto denko Lintec Materials 3M TOK Brewer Science Lintec Nitta Haas Nitto Denko Promerus Shin Etsu JSR Thin Materials AG Equipment EVG SUSS MicroTEC TEL TOK 3M AML Equipment & materials TOK 3M Carriers/Equipment FhG/ProTec ProTec/ProTec Peripheral Ring Disco (TAIKO process) DoubleCheck Semitool (AMAT)

18 Brewer Science (BSI) Temporary Bonding Processes & tools Bonding process/ Carrier Si/Glass Equipment Dupont Glass Spin coater TMAT Thermal bonding Si/Glass Bake plate Aligner TOK Glass Temporary bonder Thinning systems ZoneBond (BSI) Si/Glass Inspection systems WSS (3M) UV light Glass

19 Brewer Science (BSI) Debonding Processes & tools Debonding processes Thermal Slide-off Equipment Thermo-slide debonder Cleaning system TMAT ZoneBond (Brewer Science Inc) Mechanical release with tape frame Frame mounted wafer Debonder cluster Cleaning system for the device wafer WSS (3M) Dupont YAG Laser with tape frame Excimer Frame mounted wafer Debonder cluster Frame mounted wafer Debonder cluster Cleaning system for the device wafer TOK Chemical (solvent) release Debonder system Cleaning system

20 Number of Thin Wafers Going Through Temporary Bonding We estimated the number of thin wafers going through temporary bonding to be > 10M in This would be ~8% of the TOTAL number of thin wafers Number of thin wafers going through temporary bonding Wafers shipments (kwafers) Others (RF, MEMS 8" eq.) Power 12" Power 8" Power6'' & below D IC 12'' D IC 8'' D IC 6'' CAGR 18.3% 77.8% 30.5% 4.5% 96.3% 54.5% -1.4%

21 Ratio Bonded Thin Wafer vs. Total Thin Wafer Graph below shows the relative ratio between the total number of thin wafers and the number of temporary-bonded thin wafers. 10% 9% 8% Ratio Bonded vs. TOTAL thin wafers % Bonded vs. Total thin wafers 7% 6% 5% 4% 3% 2% 1% 0% Ratio Bonded vs. TOTAL thin wafers 4% 4% 5% 5% 5% 7% 8%

22 Temporary Bonder and Debonder Market $300 Temporary bonders/debonders market value CAGR is 37% $250 $200 US$M $150 $100 $50 $ Temporary bonders market value $39 $44 $56 $88 $115 $195 $

23 Final Conclusion As chips get thinner and wafer diameter increases, thinning/handling procedures are required. Temporary bonding equipment is still a small market today but it is expected to grow as needs for thin wafer handling grows. Power and 3D ICs applications are currently driving this market. We believe 3D ICs will then become the predominant application for temporary bonders >

24 Thank you

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