Cost of Integrated Circuits
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- Corey Snow
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1 Cost of IC Design 1 Cost of Integrated Circuits NRE (Non-Recurrent Engineering) costs fixed design time and effort, mask generation independent of sales volume / number of products one-time cost factor indirect costs (the company overhead) R&D, manufacturing equipment etc. Recurrent costs variable silicon processing, packaging, test proportional to volume proportional to chip area 2 1
2 NRE Cost is Increasing 3 Total Cost Cost per IC cost per IC variable cost per IC fixed cost volume Variable cost cost of die variable cost cost of die test cost of final test yield packaging 4 2
3 Die Cost Wafer Single die cost of die cost of wafer dies per wafer* die yield Going up to 12 (30cm) From: 5 Yield Number of good chips per wafer Y 100% Total number of chips per wafer Wafer cost Die cost Dies per wafer Die yield Dies per wafer wafer diameter/2 die area 2 wafer diameter 2 die area 6 3
4 Defects defects per unit area die area die yield 1 3, complexity of mfg. process defects per unit area = 0.5 to 1 /cm 2 cost of die = f (die area) 4 7 Some Examples (1994) Metal Line Wafer Def./ Area Dies/w Die Chip layers width cost cm 2 mm 2 Yield afer cost 386DX $ % $4 486 DX $ % $12 Power PC $ % $53 HP PA $ % $73 DEC Alpha $ % $149 Super Sparc $ % $272 Pentium $ % $417 Wafer cost Die cost Dies per wafer Die yield 8 4
5 Cost per Transistor cost: -per-transistor Fabrication capital cost per transistor (Moore s law) Today: ~10,000 transistors/ (~100n$ / transistor) Layout 10 5
6 Top View 11 Design Rules: Terminology 1/2 12 6
7 Design Rules: Terminology 2/2 13 Design Rules Intra-layer: widths, spacing Inter-layer: enclosures, overlaps Transistor rules Contact and via rules Well and substrate contacts min(width) Contact/via Pitch (pseudo-rule) Special rules (sub-0.25µm) Area, antenna rules, density rules min(overlap) min(spacing) 14 7
8 Example Design Rules: NWELL (Definitions) Design Rule Tables (N Well Example) 15 Example Design Rules: NWELL (Physical View) 16 8
9 Example Design Rules: Metals Similar tables for other layers (Poly, Active, etc.) 17 Inter Layer: Vias and Contacts Older Technology Newer Technology 18 9
10 Layout Layer Basics: Transistors 19 Transistor Layers Conceptual view Cadence representation 20 10
11 Example: Transistor Rules POLY.SE.1_POLY_SE.2 0.1um Transistor POLY.E um N-Well NBL.SE.3 0.5um 21 Example: Well and Substrate OXIDE.W.1 0.1um CONT.SE.1 0.1um NW.E um OXIDE.W um Substrate N-Well 22 11
12 CMOS Inverter schematic V DD layout N Well V DD PMOS PMOS 2 In Out Contacts NMOS Polysilicon In Out Metal 1 symbol NMOS GND 23 Layout Editor View (10 years ago): MicroMagic 24 12
13 Layout Editor View (today): Cadence Virtuoso (90nm technology) Out In1 In2 vdd gnd 25 Design Rule Checker Minimum M2 spacing 0.2 m 26 13
14 Stick Diagram 27 Stick Diagram V DD GND 3 In Out 1 Stick diagram of inverter A stick diagram is like a layout: Contains the basic topology of the circuit The relative positions of the objects are roughly correct i.e. Transistor 1 is to the right of transistor 2, and under transistor 3 Each wire is assigned a layer, and crossing wires must be on different layers Unlike a layout: Wires are drawn as stick figures with no width (dimensionless) The size of the objects is not to scale If you forgot a wire you can squeeze it in between two other wires It does not have to be beautiful CAD tools are good but it is still faster to draw a stick diagram first with pencils and paper Can even be used to estimate the size! 28 14
15 Basic Layout Planning Here are a few simple guidelines to CMOS layouts You need to route power and ground. (in metal) No one will auto connect it for you. Try to keep nmos devices near nmos devices and pmos devices near pmos devices. So nmos usually are placed near Gnd, and pmos near Vdd Run poly vertically and diffusion horizontally, with metal1 horizontal (or the reverse, just keep them orthogonal) Good default layout plan is line of diffusion Keep diffusion wires as short as possible (just connect to transistor) All long wires (wire that go outside a cell, for example) should be in either m1 or m2. Try to design/layout as little stuff as possible (use repetition/tools) Critical issue 29 Line of Diffusion Layout For a single gate, draw the diffusion on a single line (for each flavor of transistor) May need to draw two segments for some gates. Use metal to connect between the S/D nodes. NOTE: Layout is primarily determined by metal layers and not active
16 Example of Stick Diagrams: NAND and NOR Poly vertical, diffusion and metal horizontal Include substrate contacts Real cell would need input on metal, Long poly wires are bad Vdd Out Out NOR Gnd NAND 31 Example of Stick Diagrams: Complex Gate 32 16
17 Manufacturing Flow 33 A Modern CMOS Process gate-oxide TiSi 2 AlCu Tungsten n+ p-well p-epi poly n-well p+ p+ Dual-Well Trench-Isolated CMOS Process 34 17
18 Transistor Layout Cross-Sectional View poly p-well n+ poly Layout View p-well 35 Photo-Lithographic Process oxidation optical mask photoresist removal (ashing) photoresist coating stepper exposure process step Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development spin, rinse, dry acid etch 36 18
19 Patterning of Si-substrate (a) Silicon base material Si-substrate (b) After oxidation and deposition of negative photoresist Si-substrate (c) Stepper exposure Photoresist UV-light Patterned optical mask Exposed resist Si-substrate Si-substrate Si-substrate Chemical or plasma etch Hardened resist (d) After development and etching of resist, chemical or plasma etch of (e) After etching Hardened resist (f) Final result after removal of resist 37 CMOS Process Walk-Through p-epi p+ (a) Base material: p+ substrate with p-epi layer p-epi p+ SiN 3 4 (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer) p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask 38 19
20 CMOS Process Walk-Through (d) After trench filling, CMP planarization, and removal of sacrificial nitride n (e) After n-well and V TP adjust implants p (f) After p-well and V TN adjust implants 39 CMOS Process Walk-Through poly(silicon) (g) After polysilicon deposition and etch n+ p+ (h) After n+ source/drain and p+ source/drain implants. These steps also dope the polysilicon. (i) After deposition of insulator and contact hole etch
21 CMOS Process Walk-Through Al (j) After deposition and patterning of first Al layer. Al (k) After deposition of insulator, etching of via s, deposition and patterning of second layer of Al. 41 Advanced Metalization 42 21
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