WorkShop Audace. INSA ROUEN 8 juin 2012

Transcription

1 WorkShop Audace INSA ROUEN 8 juin 2012

2 Global Standards for the Microelectronics Industry JEDEC standards for product level qualification Christian Gautier

3 Content JEDEC overview Environmental reliability stress test description JESD47H Stress-Test-Driven Qualification of Integrated Circuits Physical Failure Modes per Stress Test & Acceleration factor JEP 122 Failure Mechanisms and Models for Semiconductor Devices 3

4 JEDEC (Joint Electron Device Engineering Council) Independent semiconductor engineering trade organization Founded in members companies (semiconductor manufacturers and suppliers) 48 committees and subcommittees JC-22 : Diodes and Thyristors JC-11 : Mechanical (Package Outlines) Standardization JC-15 : Thermal Characterization Techniques for Semiconductor Packages JC-25 : Transistors JC-14 : Quality and Reliability of Solid State Products 4

5 Committee JC-14 Quality and Reliability of Solid State Products Responsible for standardizing quality and reliability methodologies for solid state products used in commercial applications such as computers, automobiles, telecommunications equipment, etc, 5 subcommittees JC-14.1 : Reliability Test Methods for Packaged Devices JC-14.2 : Wafer-Level Reliability JC-14.3 : Silicon Devices Reliability Qualification and Monitoring JC-14.4 : Quality Processes and Methods JC-14.7 : Gallium Arsenide Reliability and Quality Standards 5

6 Subcommittee JC-14.3 Silicon Devices Reliability Qualification and Monitoring JESD47H.01 Stress-Test-Driven Qualification of Integrated Circuits - April 2011 Baseline set of acceptance tests for use in qualifying electronic components. These tests are capable of stimulating and precipitating semiconductor device and packaging failures. The objective is to precipitate failures in an accelerated manner compared to use conditions. JESD94 Application Specific Qualification using Knowledge Based Test Methodology July 2008 Provide a method for developing an application specific reliability evaluation methodology It assumes that the failure mechanisms and models, relevant to the product being tested, are a known entity JEP 122G : Failure Mechanisms and Models for Semiconductor Devices October 2011 List of failure mechanisms and their associated activation energies or acceleration factors 6

7 Content JEDEC overview Environmental reliability stress test description JESD47H Stress-Test-Driven Qualification of Integrated Circuits Physical Failure Modes per Stress Test & Acceleration factor JEP 122 Failure Mechanisms and Models for Semiconductor Devices 7

8 Application Conditions Application Conditions Applications Operating Life (POH)* Field Lifetime (Years) Environmental & Power Cycles Environmental Relative Humidity Environmental Temperature Range ( C) Operational Temperature Cycle Range ( C) Chip Junction Temperature (Tj) Device Nominal Operating Range(% RH) Typical/ Max. Voltage ( C) (V) Desk Top Computer 13,000 hr 5 years Main: 1/ day 10-80% C Main: C 70 C / 105 C 12.0 V with Energy Saving Mini: 17/ day Mini: C Features Short: 1/ day Short : C High End Server 94,000 hr 11 years 4 / year 10-80% C C 70 C / 105 C 1.2 V Avionic Electronics in Cockpit >150,000 hr ~ 23 years Power: 21, / day 5-80% C 0-50 C 70 C / 105 C 3.3V / 5V Telecom Hand Held 43,800 hr 5 years Talk: 20 / day Standby/Off: 1/ day Telecom Uncontrolled 131,000 hr 15 years Talk: 20 / day Environ: 1/ day Telecom Controlled 131,000 hr 15 years Talk: 20 / day Environ: 1/ day 10-95% C Talk: C Standby / Off: C 85% C Power: Δ 85 C Environ: Δ 25 C 70% 0-70 C Power: Δ 85 C Environ: Δ 6 C 30 C / 70 C 1.8V / 3.3V 85 C / 110 C 1.2 V 85 C / 110 C 1.2 V Automotive Underhood (Grade 0) 8200 hr 15 years Power: 5 / day 0-100% C C 100 C / 150 C 12.0 V * POH (Power-On-Hours) value assumes worst case 100 % power-on over the life of the application; actual application use POH may be less From JESD-94: Application Specific Qualification Using Knowledge Based Test Methodology 8

9 Environmental reliability stress test flow JESD47H Stress-Test-Driven Qualification of Integrated Circuits Finished product Electrical measurement/inspection* Preconditioning Electrical meas. / Inspection* Thermal cycling Humidity Unbiased Humidity Biased Temperature Unbiased Temperature biased Electrical measurement/ Inspection* *Inspection e.g. SCAT 9

10 PRECON Test JEDEC /JESD22-A113 Scope To assess the sensitivity of non-hermetic packaged solid-state devices, after shipment (environmental stresses), to PCB mounting (hot convection reflow soldering) Conditions are according to the observed Moisture Sensitivity Level (MSL) PCB 10

11 PRECON Flow SCAT (option) Simulate Temp. changes by transport TMCL (option) (-40 C/60 C, 5X) Remove all moisture from the package Dry Bake (MSL1/2 not needed) (125 C, 24 hr) Temp. & Hum. Soak imulate Moisture absorption in floor 85 C/85% MSL1 168 hrs 85 C/60% MSL2 168 hrs 30 C/60% MSL3 192 hrs 30 C/60% MSL4 96 hrs 30 C/60% MSL5 48 hrs 30 C/60% MSL6 6 hrs Simulate soldering process Convection reflow + Flux dip Electr. M. (option) SCAT (option) 11

12 TMCL test(temperature CycLing) JEDEC /JESD22- A104 Scope This test is conducted to determine the ability of components and solder interconnects to withstand mechanical stresses induced by alternating high- and low-temperature extremes. 125 C Air From the spec: DTcold =(+0,-10 C)/ DThot =(+15,-0 C) Visual inspection before and after the test Tstress < Tg (glass transition temperature) - 55 C Air 12

13 PPOT/UHST test JEDEC/JESD22-A118/A102 Scope This test method applies primarily to moisture resistance evaluations and robustness testing. Samples are subjected to a condensing or non condensing, highly humid atmosphere under pressure to force moisture into the package to uncover weaknesses such as delamination and metallization corrosion From the spec: DT= +/- 2 C and DH= +/-5% Condensed water ( 1M/cm) NOT allowed to fall onto the specimen Contamination control is important : - cabinets: regular cleaning - handling: suitable handcovering Tstress < Tg (glass transition temperature) 13

14 Effect of PPOT/UHST Accelerated intrusion of moisture towards electrochemically sensitive areas (e.g. die surface: bond pad corrosion) through the surrounding moulding compound or directly via gaps, cracks and delaminated areas (as a result of Precon) Moisture 14

15 Test THB/HAST JEDEC/ JESD22 -A101/110 Scope To evaluate the reliability of non-hermetic packaged solid-state devices in humid environments where temperature, humidity, and bias accelerate the penetration of moisture From the spec: DT= +/- 2 C and DH= +/-5% Contamination control is important! Read point measurements (for all hum. tests): - 48 hr (144 hr in sealed moisture bags) 15

16 Effect of THB/HAST Accelerated intrusion of moisture & drift of impurities; extra driving force: E-field towards electrochemically sensitive areas; extra driving force: V (e.g. die surface: bond pad corrosion) through the surrounding moulding compound or directly via gaps, cracks and delaminated areas (as a result of Precon) E max = V / d min Humidity V 16

17 HTSL test JEDEC/ JESD22-A103 Scope To asses the endurance of IC products when exposed to a high temperature for a long time period From the spec: DT =(-0,+10 C) Read point measurements before 168 hours + visual inspection before and after test 17

18 HTOL test JEDEC/JESD22-A108 Scope This test is used to determine the effects of bias conditions and temperature on solid state devices over time. It simulates the devices operating condition in an accelerated way. From the spec: DT =+/-5 C Read point measurements before 168 hours (96 hours if V>10V) 18

19 Environmental Tests & Conditions Environmental Stress Test Preconditioning Temperature Cycling Test Pressure Cooker test Unsaturated Pressure Cooker Temperature Humidity Bias Highly Accelerated Stress Test High Temperature Storage Test High Temperature Operating Life Abbr. Specification Stress Conditions Requirements PRECON TMCL PPOT UHST THB HAST JESD22-A113 JESD22-A104 JESD22-A102 JESD22-A118 JESD22-A101 JESD22-A110 per MSL, 1/2(a)/3/4/5(a)/6-65 C to +150 C, Unbiased (condition C) 121 C, 100 % RH, Unbiased 130 C, 85% RH, Unbiased 85 C, 85% RH, Biased 130 C, 85% RH, Biased HTSL JESD22-A C HTOL JESD22-A C (junction), Biased pass level 500 cls 3 x 0/25 96 hr 3 x 0/25 96 hr 3 x 0/ hr 3 x 0/25 96 hr 3 x 0/ hr 3 x 0/ hr 3 x 0/77 19

20 PRECON : Hot convection reflow Heller 1700EXL Convection Reflow Oven with 7 temperature zone 20

21 Temperature ( C) Temperature cycling system test 2 chambers oven (air to air) Transfer time between chambers : 10 s Rapid Thermal Variation within cold chamber with ramps up to 20 C/mn Regulation : +/- 1 C Net volume : 350 dm Package temp Cycles Time (minutes) 21

22 HAST/Autoclave systemtest Conditions : up to 160 C/up to 100%HR Regulation : +/- 0.1 C & +/- 0.1%HR Net volume : up to 30 dm 3 22

23 Temperature/Humidity system test Conditions : up to 180 C/up to 95%HR Regulation : +/- 0.3 C & +/- 2%HR Net volume : up to 540 dm 3 23

24 Temperature system test Condition : up to 200 C Regulation : +/- 1 C Net volume : up to 700 dm 3 24

25 Content JEDEC overview Environmental reliability stress test description JESD47H Stress-Test-Driven Qualification of Integrated Circuits Physical Failure Modes per Stress Test & Acceleration factor JEP 122 Failure Mechanisms and Models for Semiconductor Devices 25

26 Acceleration by DT / Temperature cycling Coffin-Manson model AF AF DT stress DT use q DT DT stress use q : Acceleration Factor : Temperature swing during stress test : Temperature swing during use : Coffin Manson exponent; failure mechanism dependent This model can be used to calculate life times for known failure mechanisms at use conditions, and to compare different stress conditions The temperature ranges must be corrected for the stress-free temperature range 26

27 Acceleration by DT / Coffin-Manson exponent (JEP 122) 27

28 Acceleration by T / Dry heat test Arrhenius model : AF E exp k act B 1 T use T 1 stress AF E act T stress T use k B Acceleration factor Activation energy; failure mechanism dependent Temperature during stress test Temperature during use Boltzmann s constant = 8.62 x 10-5 ev/k 28

29 Acceleration by RH, T, V / Damp heat test Peck model AF f V RH RH stress use n E exp k act B T 1 use T 1 stress f(v) AF RH stress RH use E act T stress T use k B n Unknown function of voltage Acceleration Factor Relative humidity during stress test Relative humidity during use Activation energy; failure mechanism dependent Temperature during stress test Temperature during use Boltzmann s constant = 8.62 x 10-5 ev/k Peck exponent; failure mechanism dependent 29

30 Acceleration by RH, T, V / Peck exponent AF f V RH RH stress use n E exp k act B T 1 use T 1 stress Failure Mechanism Exponent Activation Energy (ev) Reference Aluminum corrosion when chlorides are present JEP122 f(v) =C(onstant), corrosion rate determined by electrochemical potential E-field, corrosion rate determined by ionic transport 30

31 Examples of Mechanical Failure Modes // PRECON Solder flow out Delamination Change in body flatness Internal package crack Popcorn gap 31

32 Examples of Thermo Mechanical Failure Modes // TMCL External package crack Solder fatigue/ ball crack Delamination Wire break Passivation crack Die crack 32

33 TMCL: solder ball crack (JEP 122) Ductile solder fatigue-induced crack network 33

34 TMCL: die crack (JEP 122) Brittle failure (Si fracture) 34

35 TMCL: passivation crack (JEP 122) Brittle failure (top-side passivation fracture) 35

36 TMCL: delamination & solder fatigue cracking (JEP122) Interfacial delamination 36

37 Examples of Moisture Related Failure Modes Dry corrosion Dendrite formation & leakage Electrochemical migration between leads on a QFP (JEP 122) Aluminum bond pad corrosion (JEP 122) 37

38 Examples of Storage Related Failure Modes // HTSL Dry corrosion Stress voiding Tin whiskers Higher magnification of Al SM voids (JEP 122) Metal lines with Al SM voids (JEP 122) 38

39 HTSL : Tin whiskers growing (JEP122) 39

40 Examples of HTOL Related Failure Modes Electromigration Oxide breakdown EM void in a Cu line under a via (JEP 122) Time-Dependent Dielectric Breakdown gate oxide (JEP 122) 40

41 THANK FOR YOUR ATTENTION