EE-612: Lecture 28: Overview of SOI Technology
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1 EE-612: Lecture 28: Overview of SOI Technology Mark Lundstrom Electrical and Computer Engineering Purdue University West Lafayette, IN USA Fall 2006 NCN Lundstrom EE-612 F06 1
2 outline 1) Basic structures and SOI advantages 2) SOI film technologies 3) Partially depleted SOI 4) Fully depleted SOI 5) Advanced SOI devices Lundstrom EE-612 F06 2
3 acknowledgements 1) Professor Jerry Fossum The approach and several of the figures were taken from a talk, SOI MOSFET Physics Underlying the Good and Bad of SOI CMOS, that Prof. Fossum delivered at Purdue University, in March, ) Jianan Yang Several of the figures on SOI film technology are from Dr. Yang s Ph.D. thesis proposal 3) Professor Gerry Neudeck The SEG/ELO material was obtained from Prof. G. W. Neudeck. Lundstrom EE-612 F06 3
4 basic structures Front gate (Gf) FOX S Body D FOX BOX Substrate (Gb) Partially depleted (PD) body (similar to bulk MOSFET but the body floats) Lundstrom EE-612 F06 4
5 basic structures Front gate (Gf) FOX S B BOX D FOX Substrate (Gb) Fully depleted (FD) body Lundstrom EE-612 F06 5
6 benefits of SOI -Simple IC processing (isolation) -Higher density -Reduced S/D junction capacitance (speed/power) -Low soft-error rate -No latch-up -No (normal) body effect Lundstrom EE-612 F06 6
7 Vdd benefits of SOI input output Vss P N P N N-well N P P-well Parasitic bipolar devices latchup Lundstrom EE-612 F06 7
8 benefits of SOI (ii) input Vdd output Vss BOX No parasitic bipolar devices no latchup Lundstrom EE-612 F06 8
9 soft errors in bulk CMOS alpha particles Vdd input output Vss N-well P-substrate Alpha particles soft errors Lundstrom EE-612 F06 9
10 soft errors in SOI input Vdd output Vss BOX Low soft error rate Lundstrom EE-612 F06 10
11 layout for bulk CMOS n-well Lundstrom EE-612 F06 11
12 layout for SOI Vdd Vss P+ N+ Simpler isolation simpler process smaller layout Lundstrom EE-612 F06 12
13 benefits of SOI? Simple IC processing (isolation) / but big change Higher density Reduced S/D junction C / low anyway Low soft-error rate No latch-up / not a problem now No (normal) body effect / FB effects are worse Lundstrom EE-612 F06 13
14 outline 1) Basic structures and SOI advantages 2) SOI film technologies 3) Partially depleted SOI 4) Fully depleted SOI 5) Advanced SOI devices Lundstrom EE-612 F06 14
15 SOI film technology 1) SIMOX: Separation by ion Implantation of Oxygen 2) BESOI: Bonded and Etch back 3) ELTRAN: Epitaxial Layer TRANsfer by bonding and etch back of porus Si 4) Smartcut: (separation by H 2 implantation) 5) ZMR: Zone-melting recrystallization 6) SEG/ELO: Selective epitaxial growth and epitaxial lateral overgrowth Lundstrom EE-612 F06 15
16 SIMOX Separation by IMplantation of OXygen O + Oxygen ion implantation ion SOI layer anneal Annealing Buried oxide layer Silicon substrate Silicon substrate Deep implantation of oxygen ions into silicon Internal oxidation and damage anneal Lundstrom EE-612 F06 16
17 SIMOX comments 1) demonstrated in 1978 by Izumi et al. 2) dominant SOI technology 3) typical O + implant conditions: ~2 x cm -2 (~1000 times the S/D implant) ~ KeV ~ C anneal 4) typical numbers: BOX ~ 500 nm T Si ~ 200 nm Lundstrom EE-612 F06 17
18 BESOI Bonded and Etch-back SOI Si Wafer (future Si wafer SOI wafer) Oxide anneal polishing Polis ing/etching / etching Si Si handle Handle Wafer wafer bonding Bonding Etch-back etch-back Two flat oxidized wafers are bonded together and annealed The top wafer is thinned down by polishing and etching Lundstrom EE-612 F06 18
19 Smart Cut Oxide Initial Material Wafer A Wafer B Step 1: Hydrogen implantation into wafer A Step 2: Cleaning and bonding of wafer A and B low temp ( C) high temp (>1000C) Splitting SOI Substrate Step 3: Thermal treatment Step 4: Touch polishing Lundstrom EE-612 F06 19
20 Zone-Melting Recrystallization (ZMR) Heated graphite strip Heated graphite sus ceptor Wafer Molten zone LPCVD amorphous or polysilicon film is deposited on the oxidized silicon wafer The film is then recrystallized using e-beam, lasers, or graphite strip heater Lundstrom EE-612 F06 20
21 SEG/ELO Field oxide silicon substrate (a) create recessed wells silicon substrate (b) open seed windows SEG/ELO SOI SEG-1 SOI silicon substrate (c) SEG/ELO of silicon silicon substrate (d) CMP planarization Prof. G.W. Neudeck, Purdue University MLSOI Fabrication Process: 1st SOI Layer. Lundstrom EE-612 F06 21
22 outline 1) Basic structures and SOI advantages 2) SOI film technologies 3) Partially depleted SOI 4) Fully depleted SOI 5) Advanced SOI devices Lundstrom EE-612 F06 22
23 PDSOI Vfg 0 V Vdd FOX S Body D FOX BOX Substrate (Gb) Vbg = 0V What is V bs? Lundstrom EE-612 F06 23
24 PDSOI: floating body effects Answer: 0 < Vbs < Vdd Why does it matter? Because V T = function(vbs) Kink effect Lundstrom EE-612 F06 24
25 DC Kink effect S < 60 log 10 I DS S > 60 I DS V GS V DS Lundstrom EE-612 F06 25
26 floating body voltage: V BS What determines the DC body voltage? 0 V V DD FOX S Body D FOX BOX Substrate (Gb) S I R Body I Gi D Lundstrom EE-612 F06 26
27 floating body voltage (ii) S I R Body I Gi D I R (V BS ) = I Gi (V DS ) I R0 e qv bs / kt = (M 1) I CH thermal generation impact ionization junction tunneling GIDL (M 1) ~ e B / V DS Lundstrom EE-612 F06 27
28 explanation of Kink effect I R0 e qv bs / kt ~ I CH e B / V ds 1) Explains kink in Ids vs. Vds: I Gi Vds Vbs V T Ids 2) Explains kink in Ids vs. Vgs: Vgs Ids I Gi Vbs Ids Lundstrom EE-612 F06 28
29 floating body remedies 1) Raise the temperatures (increases I R which reduces Vbs) 2) Body ties and links 3) Implant damage to reduce lifetime 4) SiGe source to increase diode current Lundstrom EE-612 F06 29
30 ac floating body effects What determines the AC or transient body voltage? 0 V Vdd FOX S Body D FOX BOX Substrate (Gb) Answer: capacitive coupling to the bulk Lundstrom EE-612 F06 30
31 ac floating body effects voltage The equivalent circuit of the MOSFET shows capacitive coupling to the body through the: 1) gate 2) drain 3) source Lundstrom EE-612 F06 31
32 ac floating body voltage Small signal ac conditions: S g R B I Gi D C B (eq) V bs ( g + jω C (eq))= I (V ) D B Gi DS s.s. equivalent circuit is frequency dependent! Lundstrom EE-612 F06 32
33 ac floating body voltage (ii) transient conditions: S g D B I Gi D dq b /dt dq b dt = C BGf dv Gf dt + C BD dv DS dt + C BS dv BS dt Changing voltage at any terminal affects Vbs! Lundstrom EE-612 F06 33
34 ac floating body voltasge (iii) V bs (t) 1) fast component due to capacitive coupling 2) slow component due to generation/recombination 3) dynamic floating body effects can benefit circuits Lundstrom EE-612 F06 34
35 ac floating body example Vbs (i) (ii) (iv) (iii) time Vin = 0 Vin = Vdd i) gate pull-up of body ii) drain pull-down iii) gate pull-down of body iv) drain pull-up Lundstrom EE-612 F06 35
36 ac floating body summary 1) partially depleted SOI MOSFETs are bulk-like except for floating body effects 2) floating body effects can be beneficial but. 3) they need to be modeled and controlled Lundstrom EE-612 F06 36
37 outline 1) Basic structures and SOI advantages 2) SOI film technologies 3) Partially depleted SOI 4) Fully depleted SOI 5) Advanced SOI devices Lundstrom EE-612 F06 37
38 fully depleted (FD) SOI Front gate (Gf) FOX S B BOX D FOX Substrate (Gb) Fully depleted (FD) body Lundstrom EE-612 F06 38
39 FDSOI characteristics 1) FD SOI MOSFETs display small floating body effects 2) But Vtf = function (VGb) (front and back gates are coupled) 3) FD SOI MOSFETs display ideal subthreshold swing, S (60 mv / decade) as a result, V T can be lower, speed higher Lundstrom EE-612 F06 39
40 FDSOI: effect of back gate Back accumulated Vtf Back inverted Vfb(b) VGb Lundstrom EE-612 F06 40
41 FDSOI: subthreshold V S V G V D Why is S ideal? I ds e qϕ S / kt buried oxide t Si Si substrate ϕ S = V G m = V G 1 + C 2 C ox Lundstrom EE-612 F06 41
42 outline 1) Basic structures and SOI advantages 2) SOI film technologies 3) Partially depleted SOI 4) Fully depleted SOI 5) Advanced SOI devices Lundstrom EE-612 F06 42
43 single gate SOI V S V G V D buried oxide Si substrate t Si Lundstrom EE-612 F06 43
44 (b) ground plane double gate SOI (c) double gate V G V G V GB H-S Philip Wong, et al., IEDM, 1998 Ultra-thin bodies good scalability but high V t Lundstrom EE-612 F06 44
45 FinFET Sub-50 nm FINFET: PMOS, Huang et al, 1999 IEDM Lundstrom EE-612 F06 45
46 FinFET vs. trigate Si fin trigate BOX Lundstrom EE-612 F06 46
47 outline 1) Basic structures and SOI advantages 2) SOI film technologies 3) Partially depleted SOI 4) Fully depleted SOI 5) Advanced SOI devices Lundstrom EE-612 F06 47
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