Integrated Process Technology Development for the sub 7nm Era
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1 Integrated Process Technology Development for the sub 7nm Era July 12, 2017 Alex Oscilowski President TEL Technology Center, America, LLC.
2 TEL s Global R&D Operations Korea U.S. imec (Belgium) TEL Technology Center, America TEL Technology Center Korea CEA-Leti (France) Taiwan Japan Tokyo Electron Yamanashi Ltd. Tokyo Electron Kyushu Ltd. Tokyo Electron Tohoku Ltd. Tokyo Electron Miyagi Ltd. SUNY Poly/CNSE (US) TEL Technology Center, Taiwan IME (Singapore) TEL R&D base Consortium Alex Oscilowski/TTCA/July 12,
3 TEL R&D programs target key industry challenges Technology Roadmap (by Mx pitch) 64-56nm 48-40nm 38-28nm 28-20nm 20-14nm N14 N10 N7 N5 N3.5 Patterning (Logic M1 pitch) ArF immersion ArF-i/EUV/DSA SADP, LEn SADP, LEn SAQP, LEn SAQP, LEn SAOP, LEn Device FinFET FinFET FinFET FinFET, Nanowire FinFET, Nanowire Material: Channel, Contact plug, Interconnect metal Si/Si Si/Si Si/SiGe III-V/SiGe, Ge III-V/SiGe, Ge W W, Co W, Co Co Co Cu Cu Co, Cu Co, Ru Co, Ru Disruptive changes for N7/N5 Patterning methods Device architectures Material schemes are addressed through unique TTCA in Albany World class engineering talent Leading-edge process access Process/Metrology tools Competitive Benchmarking EUV Integrated flows and e-test Alex Oscilowski/TTCA/July 12,
4 TTCA R&D strategy for <7nm Develop integrated process technology modules through key R&D partnerships that deliver value to TEL and our customers Alex Oscilowski/TTCA/July 12,
5 Integrated process technology modules for <7nm Process Process technology technology Lithography/Patterning Lithography/Patterning Deposition Deposition Etch Etch Cleans Cleans Integration capability Test structures Wafer processing/access Test data (electrical/rel.) Metrology Integrated process technology modules Gate Contact Interconnect Alex Oscilowski/TTCA/July 12,
6 TTCA key R&D partnerships IBM alliance JDPs EUV patterning Transistor data Electrical/rel. data SUNY Poly/CNSE Infrastructure Technology FEOL materials EUV extension Transistor data Novel devices Supplier partners Customer focused R&D JDPs Advanced patterning Integrated modules Demos Internal R&D Module development Fast cycle feasibility Electrical/rel. data Test structures Wafer processing Competitive Benchmarking Alex Oscilowski/TTCA/July 12,
7 Advanced Patterning Examples Alex Oscilowski/TTCA/July 12,
8 SAQP using a photoresist mandrel Photoresist mandrel challenge Standard Treatment 1 Treatment 2 PR PR SiARC ODL PR PR SiARC ODL SiARC ODL SiARC ODL A-Si Oxide SiN A-Si Oxide SiN A-Si Oxide SiN A-Si Oxide SiN Oxide SiN Oxide SiN Oxide SiN Si Si Mandrel hardening Si Si Si Si Si Si Improved verticality CD ~ 16.8nm; L(S) CDU ~ 0.7 (0.9) nm LWR/LER for 4 line and 4 space features LWR LER Ave line 1.5 nm 1.2 nm Ave space 0.6 nm 1.3 nm H. Kang, SMC-2017, Seoul CDU, LER comparable to double hard mandrel SAQP Alex Oscilowski/TTCA/July 12,
9 Demonstrated Spacer-on-Spacer for SAQP cost reduction Fewer Steps for Same Results: Alex Oscilowski/TTCA/July 12, S. Thibaut et al, SPIE 2017
10 Self-Aligned Block for critical sub-40nm pitch Mx patterning A. Raley et al, SPIE 2017 Alex Oscilowski/TTCA/July 12,
11 Advanced Gate Stack Examples Alex Oscilowski/TTCA/July 12,
12 Ferroelectricity in Hafnium Oxide based Thin Films Engineered HfO 2 Anneal, etc. Doped HfO 2 Zr, Al, Gd, La, Si, Sr and Y Ferroelectricity in HfO 2 origin is assumed attributed to the non centrosymmetric phase/orthorhombic phase Currently Ferroelectric films are considered for Ferroelectric RAM (FeRAM) and as gate dielectrics for negative capacitance FETs (NCFETs) Source: J. Muller, SEMICON Europa 2012 T.S. Boscke et al. Appl. Phys. Lett Alex Oscilowski/TTCA/July 12,
13 Negative Capacitance FET (NCFET) Electrical Performance I DS -V GS Characteristics Scaling effect L G = 2 μm L G = 1 μm Steep sub-threshold slope demonstrated with ALD HZO thickness scaling Steep switching only occurs when device swept beyond coercive voltage. Dipole switching is essential for onset of NC effect. Sharma et al, VLSI-2017, Kyoto Alex Oscilowski/TTCA/July 12,
14 Advanced Contact Examples Alex Oscilowski/TTCA/July 12,
15 ALD Ti vs PVD Ti: wrap around contact NMOS Si:P R FIN R C PLOTS 4Fin-TLM resistance (Ω) 4.0k 3.0k 2.0k 1.0k 0.0 ALD Ti PVD Ti + extra HF ALD Ti + extra HF Spacing (µm) ALD Ti PVD Ti + extra HF ALD Ti + extra HF ALD Ti ALD TI + Extra HF ALD Ti wafers have lower Rc as compared to PVD Ti wafers Conformal Processes for Contact Cleans and Metals enable Wrap Around Contacts Alex Oscilowski/TTCA/July 12, IITC
16 Etch Challenges for EUV Based Contact Patterning Etch Innovation required to break these tradeoffs and to help correct incoming variability TEL DC Superposition with Q-ALE Technology enable Concurrent attainment of High Selectivity Symmetric Shrink LER smoothing & and wiggle mitigation Quasi- ALE Concept / Model A. Metz, SPIE 2017 Alex Oscilowski/TTCA/July 12,
17 Advanced Interconnect Examples Alex Oscilowski/TTCA/July 12,
18 Physical Characterization: ALD barrier testing: In-situ Ramp Anneals Barrier layers investigated using in-situ ramp anneal synchrotron XRD (Advanced Photon Source at Argonne National Lab) T c = 695ºC Integrated area under XRD peaks Al/(Al+Ta)% = 0.33 ALD TaN and TaAlN show better barrier performance than PVD TaN Alex Oscilowski/TTCA/July 12, S. Consiglio et al. ECS Trans Fall (2015)
![Resistance [kohm] [kohm] Electrical Characterization: ALD barrier / CVD-Ru liner (2nm) / Cu-fill 220 200 180 160 PVD-TaN 2nm](/docs-images/76/73626079/images/19-1.jpg "ALD-TaN 2nm ALD-TaN 1nm ALD-TaAlN 2nm ALD-TaAlN 1nm L/S=60nm/60nm 140 3.5 4.0 4.5 5.")
![0 Capacitance [pf] Cumulative probability [%] 99.](/docs-images/76/73626079/images/19-2.jpg "9 99 95 90 80 70 50 30 20 10 5 1 Via size=64nm PVD-TaN 2nm ALD-TaN 2nm ALD-TaN 1nm ALD-TaAlN 2nm ALD-TaAlN 1nm.")
![1 0 10 20 30 Via resistance [ohm] [kohm] Time to 50% failure [sec] 10 3 10 2 10 1 10 0 L/S=60nm/60nm peri.=30mm temp.](/docs-images/76/73626079/images/19-3.jpg "=125degc PVD-TaN 2nm ALD-TaN 2nm ALD-TaN 1nm ALD-TaAlN 2nm ALD-TaAlN 1nm TDDB 4 5 6 Electric field [MV/cm] Lower RC and Via")
19 Resistance [kohm] [kohm] Electrical Characterization: ALD barrier / CVD-Ru liner (2nm) / Cu-fill PVD-TaN 2nm ALD-TaN 2nm ALD-TaN 1nm ALD-TaAlN 2nm ALD-TaAlN 1nm L/S=60nm/60nm Capacitance [pf] Cumulative probability [%] Via size=64nm PVD-TaN 2nm ALD-TaN 2nm ALD-TaN 1nm ALD-TaAlN 2nm ALD-TaAlN 1nm Via resistance [ohm] [kohm] Time to 50% failure [sec] L/S=60nm/60nm peri.=30mm temp.=125degc PVD-TaN 2nm ALD-TaN 2nm ALD-TaN 1nm ALD-TaAlN 2nm ALD-TaAlN 1nm TDDB Electric field [MV/cm] Lower RC and Via Resistance plus Superior TDDB with ALD-Ta(Al)N compared to POR PVD-TaN Alex Oscilowski/TTCA/July 12, Y. Kikuchi et al., IITC/AMC 2016
20 TTCA unique capabilities Patterning capability Key R&D partnerships Rapid cycles of learning Leading edge litho ASML XT1950 ArFi- 193i ASML NXE3300B EUV DSA Film deposition, etch, and clean expertise Structures for gates, contacts, interconnects, 3DI Novel structures World class team Cross disciplinary/multi BU Breadth and depth Customer, supplier, consortia experience Joint development with all key customers, partners, suppliers on site Extensive data sharing/learning TTCA Full flow tool/process access Leading edge patterning Ge and III-V epi, BDIII, PVD, LSA/RTA Secure, TEL controlled full flow 24/7 process/tool access FEOL/MOL/BEOL/3DI All TEL/competitor tools Metrology/test Competitive Benchmarking Available to all TEL businesses Fast demo and feasibility data Local CIP/manufacturability data Hardware prototype enablement 24/7 operation TEL controlled IP protection Up and down stream integration flexibility Clustered processing, precursor delivery development Electrical/Reliability data CD variation/defectivity Vt, Vfb, Ion/Ioff, Dit, EOT, Jg, Ig, Rc, reliability for FEOL RC, Leakage, Rvia, Rline, SS, DIBL, BTI Via chain yield and reliability for BEOL Presenter / Division / Date (e.g., October 1, 2015) / Serial number 20
21 TEL and CNSE a long history of success! 12+ Years of LEADING-EDGE R&D CAPABILITY The SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering s Albany NanoTech Campus New Zero Energy Nanotechnology (ZEN) Building E C A B D TTCA* Founded A B C NanoFab South Annex 13 TEL tools in a sq ft cleanroom NanoFab South 6 TEL tools in a sq ft cleanroom First MOSCAP Data NanoFab North 40 TEL tools in a sq ft cleanroom First Full Flow Transistor Data NanoFab Central 18 TEL tools in a sq ft cleanroom D First Full Flow FinFET Data First III-V Data First DSA Data New Fab NFX 50,000 sq ft cleanroom 300/450mm compatible 3 TEL tools installed E DCS Enabled LFLFLE Solid Source Fin Doping 7nm SiN/SiO 2 ALE A WORLD-CLASS TEAM 90+ engineers 60+ service/support INTEGRATED PROCESSING TEL TOOLS Coater/Developer Tools 12 FEOL/BEOL Tools 42 Metrology/Test Tools 26 LITHOGRAPHY ACCESS ASML 1700i 1.2NA/50nm l/s ASML 1950i 1.35NA/35nm l/s ASML NXE3300B 0.33NA/18nm l/s Alex Oscilowski/TTCA/July 12,
22
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