Emerging Materials for Front End IC Process

Transcription

1 Emerging Materials for Front End IC Process Mark Thirsk Linx Consulting

2 Device Making Unit Operations % Total = 12,229, >1 Cleans CMP i-line resist Implant 248nm resist 193nm resist 193i ARCs ALD ECD Cu STI SiCOH Barrier Seed Aluminum Source: Linx Consulting 2

3 Select Device Making Unit Operations % Total = 18,923, >1 Cleans CMP i-line resist Implant ARCs ALD 248nm resist ECD Cu 193nm resist Strain 193i SiCOH STI Barrier Seed Aluminum Source: Linx Consulting 3

4 Relative Unit Operations And Growth Unit Operations CAGR 2006 to i 100 Strain 50 ALD SiCOH 193nm resist STI ECD Cu ARCs 248nm resist Aluminum CMP Implant i-line resist Cleans Average Proportion of Unit Operations Source: Linx Consulting 4

5 FEOL Processes Covered STI and CMP Gate Stack Engineering Strain Engineering Pre-Metal Dielectric High k Capacitor Dielectrics Patterning Technologies Contacts/Plugs Cleans 5

6 Shallow Trench Isolation Shallow Trench isolation is an isolation technique implemented on sub-0.18-micron technologies as an alternative to LOCOS / PECVD and is carried out one time per device at sub-180 nm to isolate transistors The flatness of the resulting wafer enables more precise pattern definition for subsequent layers With the use of SACVD for gap filling in STI, this can be extended to 32 nm and beyond Higher aspect ratios are required for memory devices 6

7 STI - Processes PARAMETERS HDP CVD HARP SPIN ON TOOL HDP CVD SA CVD (low temperature) TRACK for SOG deposition; HDP CVD on top of SOG FILM THICKNESS 3000 angstroms 3000 angstroms 3000 angstroms PRECURSORS TEOS O 3 AND TEOS POLYSILOZANE, cured in NH 3 MATERIAL COST PER DEPOSITION $0.06 $0.10 $1.5 7

8 Direct STI CMP 1000 s of operations 70,000 60,000 50,000 40,000 30,000 20,000 10,000-80% 70% 60% 50% 40% 30% 20% 10% 0% % 65 nm Ceria based HSS Slurry is the primary option for STI down to 45nm Below 65 nm Fixed Abrasive approaches with embedded Ceria are being adopted Processes often use HSS and FA Fixed Abrasive has very low sensitivity to topography and excellent selectivity for 32nm

9 Ceria - One Slurry Fits All? The concept of one slurry that can be tailored for several applications is being pursued USE DILUTION PROCESS BENEFITS STI 1:2:7 - Abrasive:Additives:DIW Dilute compared to colloidal/fumed silica slurry with stable removal rate and easy cleanability PMD 1:2 - STI Slurry:DIW Higher rate in comparison to colloidal/fumed silica slurry. Stability of removal rate and easy cleanability OXIDE 1:3 - STI Slurry:DIW Cost, high rate and easy cleanability 9

10 High-κ Gate Integration Conventional silicon dioxide gate dielectric structure compared to a proposed high-κ dielectric structures Metal Gate High k Dielectric Strained Si Substrate Gate Last Approach 1 Critical Litho level 1 Litho Level 2 CMP steps Poly Gate 1.2 nm SiON Strained Si Substrate Poly Gate Metal Gate Cap Layer High k Dielectric Strained Si Substrate Gate First Approach 1 Critical Litho level 1 Litho Level 0 CMP steps ~1.6x Capacitance ~0.01x Leakage 10

11 Gate Integration Alternatives Gate First Process High k Deposition Cap Deposition Cap Litho Metal Gate Deposition Poly Deposition Gate Litho Spacer, Strain Deposition PMD Deposition PMD CMP Dielectric Cap Layer - Lanthanum, Dysprosium for NMOS, Aluminum for PMOS Gate Last Process High k Deposition Poly Deposition Gate Litho & Etch Strain and PMD PMD CMP Poly Etch P Metal Deposition P Metal Litho & Etch N Metal Deposition Metal Fill Metal CMP 11

12 High-κ Gate Dielectric PARAMETERS 45 nm 32 nm perspectives FILM THICKNESS A A DEPOSITION TIME 8-10 sec 7-8 sec PRECURSORS TDMA Hf and TDEA Hf and HfCl 4 are the main precursors used in ALD of HfO 2 MATERIAL COST PER DEPOSITION $11.25 to $30 POST DEPOSITION TREATMENTS Thermal Thermal TEMA Hf and Hf TDMAT - Hafnium dimethylamide Hf(N(CH 3 ) 2 ) 4 and Hafnium alkoxides are also used 12

13 Metal Gate Intel announced that they have achieved 1-nm electrically-thick high-k dielectrics, dual-band-edge work function metal gates, third-generation strained silicon, using low-cost 193-nm dry patterning for critical layers FUSi approaches with Ni and Ytterbium implants is not broadly used Linx patent review on metal gates show likely materials needs are: High-κ dielectric - HfO 2, HfSiO, HfSiON NMOS - Zr, W, Ta, Hf, Ti, Al, Metal carbide, transition metal aluminides (e.g. Ti 3 Al, ZrAl) PMOS - Ru, Pa, Pt, Co, Ni, TiAlN, WCN, Metal oxide Low resistance layers - TiN, W, Ti, Al, Ta, TaN, Co, polysilicon Judging by the literature, HfSiON seems to be the consensus dielectric material, with a nominal κ of ~12, which can be also tuned by ozonization or nitridation. This is likely a single node solution. Possible low-resistance filler metals, W, Ta, TiN and TaN, and polysilicon because the CMP is already well established in HVM 13

14 Metal Gate Deposition PARAMETERS 45 nm 32 nm perspectives TOOL Process will be a hybrid PVD and ALD. PVD will be Ni-Si (FUSI) and a HfSiO. There is also a spike anneal treatment and possibly UV cure as well. FILM THICKNESS 40-50A 35-40A DEPOSITION TIME 50 sec 40 sec PRECURSORS MATERIAL COST PER DEPOSITION TaN films were deposited by ALD from commercial Tert-Butylimido- Tris(Diethylamido)Tantalum (TBTDET) and two novel mixed amido/imido/guanidinato and mixed amido/imido/hydrazido precursors $10 $8-10 POST DEPOSITION TREATMENTS Cooling Cooling TaN films were deposited by ALD from commercial (Tert- Butylimido- Tris(Diethylamido)Tantalum) TBTDET and two novel mixed amido/imido/guanidinato and mixed amido/imido/hydrazido precursors 14

15 Strain Engineering PMD dielectric layers, shallow trench isolation, and SiGe source/drain replacement can all induce useful strain on the channels of MOSFETs. these techniques can give a better trade-off of I ON for I OFF in planar designs Tensile STI Selective Epi SiGe Strained Si / SiGe Tensile SiN Compressive SiN Tensile PMD 15

16 Strain Engineering Approximately 1% induced strain results in a 10 to 20% improvement in I on Epi SiGe at S/D Strained Layers Global BiAxial Strain Buried SiGe Inducing Uniaxial Strain 16

17 Strain Engineering - Processing COMPRESSIVE TENSILE FILMS Si 3 N 4 SiGe PRECUROSRS NEXT GENERATION First generation reportedly use silane and ammonia. Common precursors also include dichlorosilane and ammonia, processed at about 700 to 800 C. The first generation of low temperature nitrides include BTBAS and HCDS, which are processed at 600 to 700 C Future products may include TSA and SAM 24 from Air Liquide and TBOS, both for ALD and CVD processes GeH 4 and silane are mostly used. SiGe needs to be deposited in pads. This means that there is an oxide or nitride mask step. HCl is used as an etchant. Precursors with Ge and Cl are being investigated 17

18 PMD Films Processes PARAMETERS HDP CVD SA CVD and PE CVD SPIN ON FILM THICKNESS 65 nm A A ~ A PRECURSORS TEOS OMCATS 3MS HSQ MATERIAL COST PER DEPOSITION 45 nm NODE FILM & PRECURSORS 32 nm NODE FILM & PRECURSORS $0.1 $0.5 to $1.0 $0.8 to $1.5 Continuation of same films materials and processes Continuation of same films materials and processes SACVD BPSG systems can extend CVD technology with a new ozonated BPSG process offering technical and operating benefits over existing systems in the pre-metal dielectric Spin-on PMDs are used to meet the requirements as current PMD technologies of HDP CVD and BPSG reflow are constrained by void formation or high thermal budget requirement 18

19 DRAM Capacitor Dielectrics Stacked capacitor-over-bit line (COB) architecture for the memory arrays Cross section taken in the plane of the bit line showing recessed channel array transistors (RCATs) used for the wordline transistors 19

20 DRAM Capacitor Dielectrics MATERIALS PRICE ($/g) GENERATION TMA & HFSiON/TMA 6 to 8 90 TEMAHf, TEMAZr HF/TMA & ZrSiO 12 to TEMAHf, TEMAZr, BST, GST, Ta-based 12 to Zr/RARE EARTHS Ru/Ta TaSiN HfSixOy For ALD of hafnium oxide and hafnium oxynitride, hafnium ethylmethylamide (TEMA Hf) Hf(N(CH 3 )(C 2 H 5 )) 4, is a good liquid precursor 2. M(OR) y in which M is a metal such as hafnium, lanthanum, zirconium, titanium, tantalum, yttrium or aluminum, R is an alkyl group (e.g., an ethyl, propyl, isopropyl, t-butyl, or neopentyl group), and y is between 3 and 5 3. Metal - cyclopentadienyls (M(C 5 H 5 )n or M(Cp) n ) are being explored for metal ALD, but not extensively for high-k ALD 20

21 DRAM Capacitor Dielectrics PARAMETERS TMA HF & laminates ZrSiO/rare earths TOOLS Jusung, Kokusai, TEL, Aixtron, Aviza, AMAT, IPS FILM THICKNESS A A A Anneal required PRECURSORS MATERIAL COST PER DEPOSITION POST DEPOSITION TREATMENTS TMA - Trimethyl aluminum Al (CH 3 ) 3 for Al 2 O 3 TDMAHF; Dicyclopentadienyldimeth yl hafnium, Hf(C 5 H 5 ) 2 (CH 3 ) 2 ; Because of its low residual carbon content and high deposition rate, TEMA Hf is currently the preferred hafnium precursor for ALD hafnium silicate films $6 to $8 $15 to $30 $18 to $32 Slow cooling Slow cooling Slow cooling TEMA Zr tetrakis(dimethylamido)zi rconium (Zr(NMe 2 ) 4 ) 21

22 Novel Precursor Markets $250 $200 millions $150 $100 $50 $ HK Capacitor Dielectric Strain HKGD Metal Gate 22

23 Patterning Trends Lithography alone may not be enough to meet the need for shrinking device features Patterning processes will become significantly more complex We have not yet met the requirement to change λ again EUV showing good progress, but some way to go yet No show-stoppers in sight, but the road is not as smooth as it has been Implementation of Double Patterning Implementation of Ultra High NA Immersion 23

24 IC Lithography Roadmap ITRS ITRS 2005 / 6 Half Pitch / nm year cycle Dry Optical Lithography Immersion Lithography Double Patterning Double Exposure EUV Imprint Direct Write *** *** *** *** *** *** *** *** E-beam *** for development and prototyping applications only Expected Solution Potential Solution Unlikely Solution 5-24

25 Double Patterning Benefits 1/2 Pitch Best Case Resolution Benefits for Double Patterning Immersion solutions H20 immersion solution Gen2 Fluid solution k1 = 0.35 k1 = 0.30 k1 = 0.25 k1 = 0.20 k1 = k1 = 0.15 Gen3 Fluid & Material solution nm NA 25

26 Complexity of the Layer Stack Increasing number of layers required for Patterning Functionality Top Coat Immersion Fluid Reflection control BARC Conditioning Filter TARC Silicon cont. BARC Image Capture Pattern Transfer Photoresist Ca Photoresist Hardmask Multiple use for Double Patterning Spin on Hardmask Under Layer Amorphous Carbon DE Materials 26

27 Total Patterning Market Growth $2,500 $ 000s $2,000 $1,500 $1,000 $500 SiBARC SOHM UL 193 TARC 284 TARC i-line TARC 193 BARC 248 BARC i-line BARC 193i Resist 193 Resist 248 Resist i-line Resist $

28 Relative Patterning Cost $ 000s $90 $80 $70 $60 $50 $40 $30 $20 $10 $0 Multilayer Material Market Size SiBARC SOHM UL Multilayer Patterning CoO CVD Precursor Spin On Material Etchant 28

29 CD Modification Roadmap Device Logic Memory Node DRAM Contacts Flow Chemical Plasma CH Shrink NAND Contacts Gate FEOL Gate Etch Trim Chemical Plasma CVD / Plasma Spacer Plasma Pattern Modification Double Patterning Logic Contacts Via 1 Chemical Freezing Chemical Plasma Chemical Plasma 29

30 Tungsten CMP Operations 250, , s of operations 120% 100% 150, ,000 50,000 80% 60% 40% 20% % 65 nm % W ALD nucleation ensures contact reliability for high AR with highly controllable and uniformly deposits. ALD nucleation ensures a wide process window for the subsequent via fill of the tungsten plug using conventional CVD 30

31 Cleaning Technology Opportunities FEOL BEOL Critical Cleans Post Implant Strip Post Etch Residue Pre- Deposition Acid Mixtures Plasma Wet Formulated Cleans Dilute HF Formulated Cleans Advanced cleans to minimize etch and physical damage Formulated Cleans or Additives to replace SPM and SC1 Improved BEOL Cleans compatible with advanced layer stacks Formulated Cleans with high selectivity of metal oxides 31

32 Improved FEOL Cleans Currently the overwhelming number of FEOL cleaning operations are inorganic based aqueous cleans in batch immersion systems. Although single wafer processes are emerging, and dilute chemistries are being employed to reduce waste, cost and improve safety, the possibility of simplified, effective processes that solve the trade-offs of aggressive chemistry and megasonic damage can succeed Damage-free cleaning that avoids Silicon loss, while minimizing the requirement for high physical energy such as megasonics Ability to measure smaller particles. Control improvements are impossible contamination cannot be measured - Smaller particles on surfaces - especially in trench structures - Smaller particles in chemicals Applied Materials AM1, distributed by Mitsubishi, combines a chelating agent in a SPM formulation reducing the requirement for an SC2 step 32

33 Relative Markets Opportunities CAGR Unit Operations - 07 to % Strain ALD 193i MultiLayer Mats SiCOH 193nm resist Front End processes generally growing more rapidly than other segments, although current market sizes are smaller STI ECD Cu ARCs Seed 248nm resist Aluminum CMP Implant i-line resist Cleans $500 Mio. Market Size % Proportion of Unit Operations BEOL FEOL & BEOL FEOL 33

34 Conclusions Memory device volume and architecture will be a key factor in the future materials demand landscape A multitude of new materials and performance requirements will emerge in the next 5 years New materials, ancillaries and processes will proliferate FEOL process will grow faster and while being concentrated in advanced manufacturers The competitive landscape throughout the value chain is changing, and may struggle to support new requirements 34

35 Supplemental Slides Double Patterning Examples 35

36 Spacer Double Patterning Sacrificial planarizing material (i.e. PETEOS) CVD Spacer (i.e. Nitride, SiON etc.) 2 nd Sacrificial material High resolution, low OLE pattern achieved with last generation lithography 36

37 Resist Freeze Double Patterning - Lines Pattern Resist Structures Coat with Freeze material Repeat resist pattern Etch Transfer High resolution Potential poor OLE Need to bias first resist pattern Potential line width differences 37

38 Resist Freeze Double Patterning - Trenches Pattern Resist Structures Coat with Shrink material and etch Repeat resist & shrink Etch transfer to hardmask Strip Etch with hard mask High resolution Potential poor OLE Trench patterns intrinsically more difficult Single hard mask requirement 38

39 Competition Status - AMAT AMAT press release on Improved APF film: APF-e film is also highly selective to polysilicon (6:1) and oxide etching (15:1) and aims to eliminate the line edge roughness associated with photoresist-only schemes to allow tighter critical dimensional control for improved device performance and yield. APF-e technology also eliminates the expensive wet cleaning steps needed by multi-layer resist processes, the company said The APF optically engineered patterning film stack combines the CVD-based amorphous carbon APF or APF-e hardmask films with Applied s dielectric anti-reflective coating (DARC) films to enable advanced lithography and etching using standard lithography tools. Applied s APF films are already being used in up to seven layers in 70nm flash memory chips, including shallow trench isolation and sub-40nm gate definition, plus other key applications. Even more layers are expected to be implemented in nextgeneration devices 39