Unique Failure Modes from use of Sn-Pb and Lead-Free (mixed metallurgies) in PCB Assembly: CASE STUDY

Transcription

1 Unique Failure Modes from use of Sn-Pb and Lead-Free (mixed metallurgies) in PCB Assembly: CASE STUDY Frank Toth, and Gary F. Shade; Intel Corporation, Hillsboro, OR, USA (503) } (503) } ABSTRACT Printed Circuit Board (PCB) assemblies are moving toward lead-free () alloys and away from the traditional Sn-Pb alloy [1]. This change is creating new and unique failure modes as the process adapts to accommodate the higher temperatures of the new process [2]. In addition, mis-processed lots are more likely due to the complexity of assembling a mix of Sn-Pb and leadfree solders, components, PCBs, solder pastes, and fluxes. This case study helps to highlight the challenge and provides an example of what can happen, how to detect it, and how the defects can cause reliability failures. Introduction PCB assemblers are gradually moving toward alloys mainly ternary Sn-Ag-Cu metallurgies. The driving forces toward assembly include regulation, environment, and global market competition. Sn-Pb solder melts at 183 o C; whereas a typical Sn-Ag-Cu alloy melts at 20 o C higher. While this is the principal difference between the Sn-Pb and PCB processes, there are other significant challenges and issues to be considered as the industry transitions to completely assemblies. Some of these issues are: 1. Procuring 100% materials (PCBs, components, connectors, pastes, etc) 2. Establishing processes that are backward compatible with Eutectic This case study examines motherboard failures from a manufacturing process with leaded parts being used on lead free boards utilizing pastes. Samples Four boards from one lot were identified with electrical failures. A common signature of overheating was identified on two of the boards in the area populated with two D-Pak FETs. One of the two boards was selected as representative and will be discussed in this case study. The two FETs on this board are identified as Q1B2 and Q3B2. Procedure The board was received and inspected both visually and using real-time x-ray. The visual inspection did not detect any anomalies; however, the X-ray inspection identified potential voiding of two FETs in D-Pak packages (Fig. 1). The void is in the heat tab area under the die. Both FETs were then cross-sectioned in the plane indicated in figures 1 and 2. X section plane Suspect voided areas i 3. Determining thermal compatibility of boards and components to new thermal profiles 4. Selecting solder paste chemistry to suit assembly process and the soldered assembly reliability and operating conditions [3] 5. Material and logistical control for simultaneous processes; leaded and Figure 1: X-ray images of FET component Q1B2 showing possible voided areas. Cross section plane is shown by the red lines.

2 Suspect voided area i Sn-Pb solder X section plane Figure 2: X-ray image of FET component Q3B2 showing possible voided area. The cross section plane is shown by the red lines. Q1B2: Optical microscope inspection of FET Q1B2 revealed that the solder had a layered structure with distinct regions with different microstructures (Fig. 3). Additional inspection using SEM with both secondary electron and backscattered detectors revealed that each layer had a grain structure indicative of Sn-Pb and solder. The separation of the regions was marked by the sharp interface seen clearly in Figure 4. EDS was used to confirm the presence of two separate regions one Sn-Pb and one. Micro-crack Eu Sn/Pb grain structure solder Figure 3: Brightfield photomicrograph of cross sectioned FET Q1B2. PCB/component interface; The grain structure clearly shows the regions where solder did not intermix with the Sn-Pb solder (see Fig. 4 for detail). The void is to the left, only partially visible in this view. Figure 4: SEM photomicrographs of cross section Q1B2. Solder of both types is clearly present; however it did not melt long enough to intermix suggesting a lower temperature Sn-Pb reflow profile was used. Clear interface is shown where /Sn-Pb solder did not coalesce.

3 see detail below Pb Sn PCB FET Figure 6: EDS line scan of Q1B2 showing the boundary between leaded and solder. Q3B2: Optical microscope inspection of FET Q3B2 revealed that the solder had a single microstructure and the presence of a large void (Fig. 5). It shows the microstructure and the presence of an intermetallic compound (IMC) at the interface of the solder to the copper pad. Using SEM with both secondary electron and backscattered detectors revealed that the solder had a microstructure typical for Sn-Pb solder. EDS was used to confirm the presence of lead and tin (Fig. 6). In the voided region, the surfaces were inspected at higher magnification with no intermetallic found. Discussion Figure 5: SEM images of FET Q3B2 showing ~ 3.5mm void between component & PCB along the cross section plane. Non-wet and voided illustrated. SEM image detail also shown at 750X and 3000X. Notice the eutectic microstructure throughout the solder bulk and the IMC evident at the PCB to solder interface. The samples evaluated exhibit partly Sn-Pb eutectic, partly Sn-Pb hypereutectic, (ie much more tin than eutectic composition) layered structure. See Fig. 7 for phase diagram. Two aspects make this microstructure very strange: (1) In part of the solder joint, the Sn-Pb eutectic is near the FET and in part of the joint, the Sn-Ag-Cu microstructure is near the FET; (2) There has been no coalescence of Sn-Pb eutectic and Sn-Ag-Cu segments. Even in backward or forward compatibility solder joints there is some amount of mixing. The PCB was intended to use a process and reflow profile with paste however the cross sections reveal a Sn-Pb structure at the PCB interface suggesting that leaded paste was printed unintended on a PCB [4].

4 The layered structure, also suggests however presence of paste as well. One hypothesis of where the Sn-Ag-Cu paste comes from is that both Sn-Pb and pastes may have been printed during possible rework on these components. Traceability to process control is very difficult to achieve and/or validate for accuracy but evidence clearly shows both Pb and pastes. If rework was not a direct cause and a reflow profile [5] such as shown in Figure 8 below was used, proper mixing has not been achieved. This is also aggravated by the large interface between the FET component/pcb surface conducting heat away rapidly, and causing the paste to only partially melt. As a consequence, the electrical performance of the overall system was affected resulting in thermal hot spots on the PCB. Although not uncommon for process voids to occur under FET components, these FET samples had extensive regions de-void of solder paste material in the heat sink region resulting in hot spots which caused the FETs to operate outside their electrical specification causing an electrical board fault. Thermal analysis and X-ray were able to isolate the failure to the FETs. Cross-section and analysis of the solder joint chemistry and microstructure were critical to identify the root cause. In this case study, the failure was caused by two separate issues; a) Improper mix of solder paste b) Insufficient localized heat at the FET components. The solder paste material did not reach a sufficient temperature to complete melting and mixing. Figure 7: Ternary phase diagram of Sn-Ag-Cu. Melting temperature of SAC solders converge around 218 C [6].

5 The increase in localized temperature and use of Sn-Ag-Cu paste exclusively has remedied the solderability problem observed on these samples. Figure 8: Reflow profile (temperature vs. time) shown for 9 thermocouples placed at various locations on the PCB board. Peak temperature ranging from C, soak temp C and TAL (time above liquidus) above 218 C shown. With profiles the peak temperatures reach approximately C compared to about C for reflow and wave respectively. As transitioning to processes occur, a significant requirement is to ensure that all materials can withstand these elevated temperatures. Conclusion Corrective actions: 1. Make sure PCB manufacturers use only Sn-Ag-Cu pastes on lead free process 2. Increase peak reflow temperature at the FET thermal plane solder joints by at least 5 C Figure 9: Board soldering compatibility References: 1. Overview of 2004 inemi Technology Roadmap, Jim McElroy (inemi), IPC Printed Circuits Expo/APEX/Designers Summit, February 22-24, 2005, Anaheim, CA. 2. Norman J. Armendariz, ASM/EDFAS Microelectronic Desk Reference, Fifth Ed., PCB SMT Solder Joint Failure Analysis p Promotional Literature: Kester Lead-Free Solutions, Kester Solder Co. 4. Private Communication; Mandy Mistkawi, October Prawin Paulraj Intel Corp. reflow profile 6. Phase Diagram Research, NIST, Metallurgy Division, Gaithersburg, MD This case study found leaded and parts within a single PCB. Installing leaded components onto a board (or vice-versa) is a scenario that is termed forward and backward compatibility respectively (Fig. 9). Many cases and varieties of this exist today and the number of cases is increasing. Mixed technology used in the transition from eutectic to solders and components presents increased risk to stress test and overall system reliability. Techniques developed for optimizing and characterizing solder joints were utilized to determine root cause for the failure. These techniques can also be used to detect improper conditions before a failure occurs thus providing better PCB reliability.