Reliability And Processability Of Sn/Ag/Cu Solder Bumped Flip Chip Components On Organic High Density Substrates

Transcription

1 Reliability And Processability Of Sn/Ag/Cu Solder Bumped Flip Chip Components On Organic High Density Substrates Minja Penttilä, Kauppi Kujala Nokia Mobile Phones, Research and Technology Access Itamerenkatu 11-13, FIN Helsinki Phone: +358-(0) , Fax: Abstract This research work faced the challenges from both miniaturization and environmental demands by focusing on the reliability and processability of lead-free flip chip components on high-density organic substrates. Ternary Sn/Ag/Cu alloy was used as the solder bump material for lead-free flip chip devices, while the reference samples had eutectic Sn/Pb solder bumps. High density PWBs (Printed Wiring Board) with RCCu (Resin Coated Copper) build-up layers and Ni/Au surface finish were used as test substrates. Combinations of two flux and two capillary-flow underfill materials were used in both conventional Sn/Pb and lead-free SMD (Surface Mount Device) processes to assemble test vehicles. Reflow was done in air. Post assembly solderability and solder joint voiding were inspected by X-ray and optical microscope. Samples were subjected to two company specific reliability tests, thermal cycling and mechanical shock test, after which samples were analyzed by cross sectioning and scanning electron microscope (SEM). Underfill voiding was determined using acoustic microscopy. Clear differences in flux material performances in conjunction with Pb-free solder bumps were noticed. Differences in solder joint reliability were further observed during thermal cycling. In addition, success of the underfilling process was noticed to have a major impact on component reliability. In the end a set of suitable materials and process parameters for lead-free flip chip SMD assembly was found. Thermal cycling performance of the best Pbfree combination turned out to be equally good with the best eutectic Sn/Pb case. Also mechanical shock resistance of lead-free components was found to be equal with the reference samples. The International Journal of Microdircuts and Electronic Packaging, Volume 24, Number 2, Second Quarter, 2001 (ISSN ) 290

2 Key words Lead-Free, Flip Chip, Flip Chip On Board, Sn/ Ag/Cu, Reliability 1.0 Introduction The continuing consumer demand for smaller and relatively lower-cost cellular handsets with ever-increasing functionality and performance place many challenges on phone engine design and manufacturing. Different electrical, thermal and density constraints of integrated circuits and substrates together with various end product reliability requirements force to look for new packaging solutions. Flip chip components offer the highest packaging density and very competitive electrical and thermal characteristics, which makes them an appealing component solution. In addition to the desire for miniaturized gadgets, environmental consciousness has emerged among consumers of portable electronics, and market demand for environmentally friendly products and production has become more noticeable. In Europe legislative dead line for the restrictions on the use of lead and some other hazardous materials will be year 2006 according to the most recent draft of the proposal for a Directive on Waste from Electrical and Electronics Equipment (WEEE) [1]. All materials and process variables used in this research work were chosen based on the experiences from various assembly trials done in house with both eutectic Sn/Pb and Sn/Ag/ Cu flip chip components. Especially there exists a deep knowledge of the eutectic Sn/ Pb flip chip process. Therefore the chosen flux and underfill materials were known to perform well in eutectic Sn/Pb assembly and to be compatible with each other. The purpose of this experiment was to manufacture samples for preliminary Pb-free FCOB (Flip Chip On Board) board-level reliability testing, and to find a set of materials that could successfully be used to assemble flip chips on organic laminates during a lead-free SMD process. 2.0 Test Vehicle Assembly Materials All test dice were daisy chain flip chips with Al/NiV/Cu under bump metallurgy. Lead-free dice had a close to eutectic solder bump alloy composition Sn/3.5Ag wt%/1.0cu wt% (there are several suggestions in the literature for the eutectic composition, two recent ones are Sn/3.5Ag/0.9Cu [2,3] and Sn/3.4Ag/0.8Cu [4]). Both one row peripheral (chip-p) and full array (chip-f) bump configurations were used. Chip-p had 88 solder bumps with 203 mm pitch and chip-f had 317 solder bumps and 254 mm pitch. Die size for both types was 4.98x4.98 mm. Reference samples were chipp type dice with eutectic Sn/37Pb solder bumps. The used test substrates were eight layer organic boards (with FR4 core, RCCu buildup layers (2+4+2 construction). The surface finish coating was electroless Ni - immersion Au. Each test vehicle contained three peripheral and one full array dice together with around 120 other SMD components mounted on the topside. Test pads for daisy chain resistance measurements were located on the backside of the substrate. Two no-clean rosin based fluxes (flux-a and flux-b) and two epoxy based capillary flow 291

3 underfill materials (underfill-a and underfill-b) were selected due to their good performance in numerous Sn/Pb flip chip experiments. It should be noticed, that no flux or underfill materials designed especially for lead-free process were available at the time this research work was started. The properties of the two used underfills are presented in Table 1. SMD Process Test vehicles were assembled in a single-side SMD process that included process steps for DCA (Direct Chip Attach): flux dipping, conventional underfill dispensing and underfill curing. A corresponding process flow diagram is shown in Figure 1. To provide useful references for mass production, neither bake-out nor other preconditioning was done for the PWB substrates. Flip chips were assembled using Universal 5681A-GSMx placement machine. No solder paste was screen printed for flip chips because of the small dimensions and risk for solder joint bridging. Lead-free solder paste was used only for the other SMD components. Reflow was performed in a forced convection oven. No special atmospheres were used, even though it has been showed that nitrogen atmosphere clearly improves the solderability results [5]. The reason for choosing reflow in air was the impracticality and cost effect of using Ni-atmospheres in very high volume cellular phone production. Figure 2 shows the used reflow profile linear-2. It had a peak temperature of 241 C (measured under component), and time above the melting temperature of the Sn/3.5Ag/1.0Cu solder, 217 C, was 46 seconds. Profiles soak-1 (peak T 226 C, time above 217 C 18,5 seconds) and linear-1 (peak T 231,5 C, time above 217 C 30,5 seconds) had been tested earlier, but they did not result in satisfactory solderability results with flux-b, as can be seen from the assembly yield results in Table 2. Therefore peak temperature and length of the profile were further increased for this experiment. The goal was to find such reflow conditions that would result in sufficient solderability for both flux materials without causing damage to the substrate or other components. Standard profile refers to the profile used with standard eutectic assembly. Solder joint formation was verified after the reflow by X-ray and measuring electrical continuities of the daisy chains. Next underfill was dispensed using an L-shape dispensing pattern. Curing times at 150 C were 5 minutes for underfill-a and 3 minutes for underfill-b. Eutectic Sn/Pb reference vehicles (flip chips plus other components) were assembled simultaneously with lead-free samples to provide reliable reference data. Used materials and the SMD process were the same as in lead-free case, only the reflow profile was changed to accommodate the Sn/ Pb solder ( standard in Figure 2). Assembly Results Table 3 shows the percentages of electrically functional dice after reflow process for each material combination. All assembly yield measurements were done manually before the underfilling process, and failure criterion was set to minimum 20% increase in daisy chain contact resistance. In the trial all other material combinations had assembly yield except Sn/Pb flux-a combination. The 292

4 Material Table1. Properties of the used underfill materials. Viscosity C, cp) Filler content (%) T g ( C) CTE (ppm/k) (T<T g ) Curing time (@150 C) Underfill-A min Underfill-B min 1. Stencil printing 2. Discrete Placement 3. Flip Chip Placement 7. Underfill curing 6. Underfill dispensing 5. Testing 4. Reflow Figure 1. SMD process steps used to assemble test devices. Table 2. Lead-free process assembly yields (percentage electrically functional dice after reflow) for soak-1 and linear-1 profiles. Reflow peak T ( C) / Time above 217 C (s) Sn/Ag/Cu + Flux-A Sn/Ag/Cu + Flux-B / 0:30,5 (linear-1) 70% 226 / 0:18,5 (soak-1) 9.5% 293

5 reason for this only failure was found out to be too substantial die misalignment. Cross sectioning was used to confirm the solderability results. Examples of typical solder joints are shown in Figure 3. Flux-A resulted in slightly better wettability with leadfree samples than flux-b, although solderability results were acceptable for both cases. With flux-b lead-free solder joints were generally somewhat higher than with flux-a, and in some cases PWB solder pads were only partly enveloped. As expected based on the previous flip chip trials, both flux-a and flux-b had very good performance in Sn/Pb assembly and all reference samples showed good solderability. When comparing the assembly yields with the results obtained from lower reflow profile assemblies (results were shown in Table 2), it can be concluded that the reflow profile with the highest peak temperature was more suitable for Sn/Ag/Cu - flux-b combination than the two lower profiles. The lower the peak temperature was, the worse the assembly yields were for this combination. Flux-A showed good lead-free process compatibility regardless of the reflow profile. During cross sectioning some voids in the Sn/ Ag/Cu bumps were noticed. These voids were also seen during an X-ray inspection right after the assembly. However, since few voids were already present in unused chips, it was hard to define the exact effect of the assembly process. When compared to the trials with lower reflow profiles, voiding incidence seemed to increase with increasing reflow peak temperature. Underfill voiding was inspected after the assembly by SAT (Scanning acoustic Transducer). Some voids were seen in underfill-b (shown in Figures 5b and 6a), but the reasons for this phenomenon were familiar from previous flip chip experiments: voiding was caused by a fiducial mask opening under the chip that prevented optimal flow of the underfill material. However, extraordinary large voids (shown in Figure 5a) and unusual fillet bubbling that cannot be explained by the fiducial mark were noticed in underfill-a. The cause for this type of voiding was not material related, since underfill-a had performed well in previous lead-free trials. Instead it was noticed afterwards, that the PWB temperature during underfill-a dispensing was set too low. This resulted in the unwanted underfill voiding. Too low temperature can cause moisture from the PWB to get trapped under the chip and also disturb the underfill material properties. 3.0 Reliability Tests Samples were subjected to environmental stress tests -thermal cycling and mechanical shock test- to compare the reliability of different material combinations. Thermal Cycling Thermal cycling was done in an air-to-air chamber using 3 minutes ramp from -40 C to +125 C, and 14 minutes hold-time at extreme temperatures (total cycle time 34 minutes). Samples were continuously monitored with an event detector to make sure failures were observed immediately when they occurred. A failure was recorded when a resistance peak over 1000 Ohms and longer than 200 nsec occurred, followed by 9 resistance peaks over 1000 Ohms. These conditions are a modification from the IPC- SM-785 standard. Minimum requirement for 294

6 Table 3. Electrically functional dice after the assembly (number of electrically functional dice / total number of dice in that combination). Flux A B Solder type total Sn/Pb (peripheral) 99% (95/96) (95/95) 99% (190/191) Sn/Ag/Cu (peripheral ) (95/95) (96/96) (191/191) Sn/Ag/Cu (full array) (32/32) (32/32) (64/64) Flux total 99,55% (222/223) (223/223) Figure 2. Linear-2 reflow profile was used in this lead-free trial. Standard Sn/Pb profile was used to assemble reference samples. Profiles soak-1 and linear- 1 had been used in earlier trials. 295

7 Solder type Flux A Flux B Eutectic Sn/Pb 95Sn/3.5Ag/1.0Cu Figure 3. Examples of typical solderability results for different material combinations. passing the test was 500 cycles. The test was stopped at 2000 cycles. Figure 4a shows two-parameter Weibull distribution graphs of the failures for Sn/Ag/ Cu and Sn/Pb cases including all the material combinations in the experiment. As can be seen from the figure, lead-free samples had a few early failures, while all eutectic reference samples passed the required 500 cycles. The low Weibull shape parameters, i.e. betavalues, indicate a presence of a mixed failure mode. Figure 4b shows the same results, but now excluding flux-b combinations due to poorer lead-free solderability, and underfill-a combinations due to very big underfill voids. These factors might have been the cause for early failures. When considering only the better material combination (flux-a & underfill- B), also all lead-free samples passed the requirements. Their performance was now equal with the reference samples. Cross sections together with SAT and SEM inspections proved, that one reason for early failures in thermal cycling test was inadequate flux performance resulting in poor solder joint quality. An even more significant reason, however, was the failed underfilling process resulting in very big underfill voids and therefore also false fillet formation. Due to the lack of adequate underfill and/or fillet reinforcement against stresses from thermal expansions, fatal cracking resulting from creep fatigue occurred earlier than in samples with smaller or no underfill voids. Figure 5 296

8 Figure 4a. Weibull graphs of thermal cycling failures including all material combinations. b(sn/ag/cu) = 1.58, b(sn/pb) = Figure 4b. Weibull graphs of thermal cycling failures including the better material combination (flux-a & underfill-b) only. b(sn/ag/cu) = 5.27, b(sn/pb) =

9 die Crack Sn/Ag/Cu bump Figure 5a. SEM figure of Sn/Ag/Cu solder joint with flux-a and underfill-a. Chip failed after 400 thermal cycles due to an almost chip size underfill void which caused solder joints to crack close to die interface. SEM figure taken after 1000 thermal cycles. Void die Crack Sn/Pb bump Pad PWB PWB Figure 5b. SEM figure of eutectic Sn/Pb solder joint with flux-b and underfill-b. Chip failed after 600 thermal cycles due to a big underfill void which caused solder joints to crack close to PWB pad. SEM figure taken after 1000 thermal cycles. 298

10 shows examples of such early failures in both Sn/Pb and Sn/Ag/Cu samples. Also the progression of underfill delamination was observed during thermal cycling using SAT. In flux-a combinations underfill delamination initiated typically around the 1000 th cycle from the corners of the die for both underfill materials. In flux-b combinations delamination was observed already around 600 th cycle, and as can be seen from Figures 6 and 7, delamination initiated also around solder joints in addition to corners. Delamination phenomenon was not noticed to correlate with solder alloy composition, underfill material or underfill void size, but only with flux material. This could mean that flux- B was in general less compatible with the used underfill materials, or that there were more flux residues left from flux-b causing delamination around solder joints. Figure 8 shows optical microscope pictures of typical Sn/Pb and Sn/Ag/Cu solder joints after 2000 thermal cycles. From the figure it can be seen, that Sn/Ag/Cu solder joints had more homogeneous microstructure than eutectic Sn/Pb reference samples. In addition, intermetallic compounds (IMC) around PWB pads did not seem to grow as much in leadfree solder joints as in eutectic Sn/Pb systems. This kind of structural behavior indicates potential better long-term reliability for leadfree solders. Mechanical Shock A board-level free fall drop tester was used to study the durability of lead-free flip chip components against mechanical shock. The testing equipment is shown in Figure 9. The test method is based on JESD22-B104-A standard, which defines the goal impact pulse, level at 1500G (+/-20%) for 1 msec (+/-30%). Test modules were fixed from four corners to the vehicle components facing down, and were then dropped from 1.5 meters 24 times. Daisy chain contact resistances were monitored in equal intervals. Since the test configuration was not optimized for flip chip components, no requirement for number of drops before failure was set. Failure criteria were set to 20% increase in daisy chain contact resistance. All together 112 dice were tested, both Sn/Pb and Sn/Ag/Cu, but no electrical failures occurred. Neither were any solder joint or die cracks found during the following cross sectioning, and SAT and SEM inspections. On the other hand, some discrete components were detached during dropping, which proves the severity of the test. 4. Conclusions The research work showed, that when compared to the eutectic Sn/Pb case, there are no major difficulties in mounting flip chip components with Sn/Ag/Cu solder balls on organic laminates. But due to the higher melting temperature of lead-free solder the assembly process window is considerably narrower than for eutectic Sn/Pb, which requires careful material and process parameter optimization. Even though all the flux and underfill materials used in this work had originally been designed for eutectic Sn/Pb process, a material combination resulting in successful assembly and adequate reliability was found. There were, however, apparent differences in the wetting abilities of the flux materials. The lower the reflow temperature was, the more significant became the fact that flux material had an optimal performance in order to achieve good solderability results. 299

11 Figure 6. An example of a typical void in underfill-b caused by fiducial under the die (a); and same die after 1000 thermal cycles (b). Other materials in this case were Sn/Pb solder and flux-b. die Solder ball underfill Figure 7. SEM picture showing underfill delamination from die passivation and solder bump interfaces (Sn/Ag/Cu solder, flux-b and underfill-b). 300

12 Figure 8. Examples of typical Sn/Pb (a) and Sn/Ag/Cu (b) solder joint structures after 2000 thermal cycles. Sample Holder Vehicle Plate 2.0 m Rubber cushion Figure 9. A simple illustration of the drop test equipment used for board level testing. 301

13 Correspondingly, increasing the reflow profile peak temperature and the time above 217 C resulted in improved solderability. Also, contrary results of the relation between solderability and increasing reflow temperature have been reported from similar experiments 5, which indicates that fluxes can have variable performances when changing into lead-free reflow temperatures. The wetting ability is of course also dependent on many other factors, like reflow atmosphere and profile shape. Higher reflow temperature was not noticed to have a clear effect on flux residues or board warpage, but it seemed to increase the tendency for solder joint voiding. However, the exact impact could not be determined within this research work, since some voids were already present in lead-free solder balls before the assembly. No problems arising from worse self-alignment properties of lead-free solder were noticed, but the difference compared to Sn/Pb solder behavior is obvious. Therefore it is necessary to have adequate placement machine accuracy, as well as controlled solder mask opening and pad tolerances. The problems for economically employing lead-free flip chip on board solutions on cellular phone motherboards do not seem to arise so much from the solder type or assembly process, but more due to other general issues related to flip chip technology. Such challenges include for example known good die, die shrinking, underfilling process and availability of low-cost high density PWBs. Acknowledgements The authors would like to thank flip chip research team members and test assembly line operators at Nokia Mobile Phones for help and contribution, P.Pasanen from Nokia Mobile Phones for providing the Weibull graphs, as well as Flip Chip Technologies for providing the test dies. The thermal cycling test showed that lead-free flip chips can have at least equal reliability compared to eutectic Sn/Pb flip chips as long as optimal assembly materials and parameters are used. In thermal cycling all failures occurring before the required 500 th cycle were in samples with exceptionally large underfill voids. These voids did not, however, appear because of the lead-free process. Reasons for subsequent thermal cycling failures were poor solderability and underfill delamination resulting in solder fatigue and solder joint cracking. In free-fall drop test underfilled flip chip components, both Sn/Pb and Sn/Ag/Cu, turned out to be very resistant against mechanical shock. 302

14 References 1. Document 501PC0316, Amended proposal for a Directive of the European Parliament and of the Council on the restriction on the use of certain hazardous substances in electrical and electronic equipment, 2. K.W. Moon, W.J. Boettinger, U.R. Kattner, F.S. Biancaniello, and C.A. Handwerker, Experimental and thermodynamic assessment of Sn/Ag/Cu solder alloys, Journal of Electronic Materials, Vol. 29, No. 10, pp , October M.E. Loomans and M.E. Fine, Tin-silvercopper eutectic temperature and composition, Metallurgical and Materials Transactions A, Vol. 31A, No. 4, pp , April About The Authors Minja Penttilä received her M.Sc. degree in Materials Science, Electronics Production Technology from Helsinki University of Technology in She is currently working as a Research Engineer at Nokia Mobile Phones, Research and Technology Access. Her main activities include novel packaging and substrate technologies. Kauppi Kujala received his M.Sc. degree in Materials Science, Electronics Production Technology from Helsinki University of Technology in He is currently working as a Project Manager and Senior Research Engineer at Nokia Mobile Phones, Research and Technology Access. 4. Wei Qun Pen, Lead-free Electronic Assembly Based on Sn-Ag-Cu Solders, Licentiate Thesis, Helsinki University of Technology, G. Baynham, D.F. Baldwin, K. Boustedt, S.Kandelid, F. Mattsson, C. Wennerholm, A. Johansson, D. Patterson, P. Elenius, and H. Balkan, Lead-Free Flip Chip Processing with Halogen-Free High Density Microvia Substrates, 26 th International Electronics Manufacturing Technology Symposium, Santa Clara, CA, October 2-3, pp ,