CMP Process Development for the Via- Middle 3D TSV Applications at 28nm Technology Node

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1 CMP Process Development for the Via- Middle 3D TSV Applications at 28nm Technology Node UMC/ ATD_AM / CMP Department T. C. Tsai, W. C. Tsao, Welch Lin, C. L. Hsu, C. L. Lin, C. M. Hsu, J. F. Lin, C. C. Huang and J. Y. Wu

2 Introduction 2

Global Foundry, Tezzaron, Ziptronix ASE, Infineon, Zycube, IZM, After Bonding Samsung, IBM, MIT LL, RTI,

3 Before (CMOS) FEOL 3D-TSV Integration Schemes Via-First Approach IBM, NEC, Elpida, OKI, Tohoku, DALSA. After FEOL (Before BEOL) (Via Middle) Before Bonding (After BEOL) Via-Last Approach UMC, TI, TSMC,IMEC, Global Foundry, Tezzaron, Ziptronix ASE, Infineon, Zycube, IZM, After Bonding Samsung, IBM, MIT LL, RTI, RPI. Source: Yole Development; P. Pangaud, U. de la Méditerranée, CMOS Emerging Technologies Workshop,

metal Stress-absorbing M2 Mechanically metal M1 strengthened dielectrics Cu/Ta-CMP

4 Via-Middle TSV Process Flow Through Silicon Via RIE Insulator Deposition PASV Barrier/Seed Deposition Via Filling Al-pad (L2) SiO2 (L1) Cu_Mn IMD Cu_M3 Bondable metal Stress-absorbing M2 Mechanically metal M1 strengthened dielectrics Cu/Ta-CMP OX/SiN CMP BEOL q Via-middle between Cont and BEOL 3D-TSV scheme has become the mainstream for IC foundry. 4

5 Experimental 5

6 Experimental q 300mm blanket wafers with Si-substrate/ inter-layer dielectric (ILD) oxide layer/ SiN layer were prepared to form via-middle TSV structure wafers. q The 70um deep TSVs with 10um diameter size were constructed with electrochemical deposition (ECD) of Cu film/ PVD Cu seed/ Ta(N) barrier/ SACVD oxide liner. q Two Cu metal layers with 28nm BEOL design rule were stacked on TSV structures to evaluate the process impacts of the intrinsic TSV Cu extrusion on BEOL layers. 6

7 Schematic of Via-middle TSV Structure Wafers post ECD Process ECD Cu SACVD Oxide Liner SIN CMP Stop Layer ILD Oxide Layer Si Ta(N) Barrier 7

8 Experimental q The TSV CMP was carried out a rotary type polisher with three polishing platens. q Three different kinds of silica based slurries were utilized to polish off 1). excess copper film on platen one; 2). Ta(N) barrier and oxide liner layers (stop on SiN layer) on platen two; 3). SiN layer (final stop on ILD oxide layer) on platen three. q Varied pre-tsv CMP anneal temperatures (350C~410C) and ECD with different electroplating chemical solutions were investigated to eliminate the formations of the Cu extrusion and voids induced by BEOL thermal budget. 8

Via-Middle TSV-CMP Potential Issues Ti Ta(N) Platen 2 OX/SiN Residue SIN ILD OX Polish Ti(Ta)/OX stop on SiN Ti Ta(N) Platen 1 Cu Residue/ Dishing SIN ILD OX Polish Cu stop on Ti(Ta)

9 Via-Middle TSV-CMP Potential Issues Ti Ta(N) Platen 2 OX/SiN Residue SIN ILD OX Polish Ti(Ta)/OX stop on SiN Ti Ta(N) Platen 1 Cu Residue/ Dishing SIN ILD OX Polish Cu stop on Ti(Ta) Platen 3 ILD range/ Cu recess / Defectivity Ti Ta(N) ILD OX Polish SiN stop on ILD q TSV recess, ILD range, T/P and defectivity are the key issues need to be fixed. 9 Ti Ta(N) Cu SIN ILD OX

10 Experimental q Cu film thickness before and after TSV CMP was detected by using a KLA RS-100 four point probe. q ILD oxide layer thickness loss and range were measured by KLA F5x thin film measurement system. q The TSV Cu recesses were characterized by using high-resolution atomic force profiler. The TSV structures post deep reactive ion etching (RIE), ECD and CMP processes were determined by using top and cross-sectional viewed SEM micrographs. 10

11 Results and Discussion 11

12 Cross-sectional TSV SEM Pictures a). b). c). 12 d). q TSV with aspect ratio (AR) ~7 structures post (a~c) deep reactive ion etch (RIE) and (d) Electrochemical Deposition (ECD) steps.

13 Cu Peeling/Residue and OX/SiN Dielectric Residue Issues post TSV-CMP Cu Peeling Cu Cu Residue OX/SiN Residue q Cu peeling/residue and OX/SiN dielectric residue found due to unsuitable ECD and TSV CMP processes. 13

14 Before and after Electrochemical Deposition (ECD) Cu THK Profiles Optimization TSV Cu Thickness (A) Before Process T uning During Proce ss T uning Final Proc ess optimizat ion W afer Diam eter from W afer C en ter (m m ) q The range of WiW Cu film thickness can be much improved from ~20000A to 1500A by ECD process optimization. 14

ILD THK Range Control Performance post TSV-CMP Platen Three Polishing Range = 65A Remaining ILD THK (A) 2150 2100 2050 2000 1950 1900 1850 #5 #6 #7 #8 #9 #10 #11 #12 #13

15 ILD THK Range Control Performance post TSV-CMP Platen Three Polishing Range = 65A Remaining ILD THK (A) #5 #6 #7 #8 #9 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 Range = 59A q WtW and WiW ILD THK mapping range control can be <100A as ILD THK loss ~100A post P3 polishing. 15 Wafer No.

16 TSV Cu Recess Level for Each Polishing Step (TSV Areas Marked by Red Cycles) a ). P re -T S V C M P b ). P o s t P 1 p o lis h R e c e s s : ~ A c ). P o s t P 2 p o lis h R e c e s s : ~ A d ). P o s t P 3 p o lis h R e c e s s : ~ A R e c e s s : ~ A q The TSV Cu recess can be continuously reduced form around 330A to 110A as polishing through platen 1 to platen 3 TSV-CMP process. 16

17 Cu Extrusion Found post TSV CMP Cap and Metal 3 Cap Layer Depositions a). ~560A Cu Cu extrusion (Pre- (350C 350C x 10x 10min. anneal) Anneal) ~60A Cu Cu extrusion (Pre- (400C 400C x 10x 10min. anneal) Anneal) Post Post Metal Metal 33 Cap Cap 95A 95A Cu Cu Extrusion q Severe Cu extrusion was easily found post TSV CMP cap and even post metal 3 cap layer deposition. 17

q Metal /ULK thinning were found due to Cu extrusion for pre anneal condition.

18 Cu Extrusion Induced Metal/ULK Thinning and BEOL Peeling with Cu Voids a). TSV Si b). M1/ V1/ M1/ ULK/ V1/ ULK/ M2 THK M2 Thinning ULK TSV TSV Cu Cu Extrusion M2 M1 M2 M1 V1 M1 M2 c). q Metal /ULK thinning were found due to Cu extrusion for pre anneal condition. - TSVCMP q Cu extrusion of TSV is indeed a potential concern to result in metal and ultra-low k (ULK) film thinning and delamination or damage of the BEOL. 18

19 Effects of pre-tsv CMP Anneal Condition on Cu Extrusion and Void Formation W/O Anneal No Anneal 350C x C x 20 (Post CMP) (Post CMP) (Post CMP) f). 350C x 10 (Post CMP) 400C x 10 (Post CMP) C x 10 (Post Cap) q Increasing pre-tsvcmp anneal temp. could reduce Cu extrusion, but induce Cu voids issue.

20 Effects of Different ECD Chemical Solutions on TSV Cu Voids (400Cx10 min. Anneal) Chemical Solution 1 Chemical Solution 2 Normalized Impurity Concentration Chemical Solution 1 Chemical Solution 2 C Cl O N S Impurities of the Cu ECD Chemical Solutions q TSV Cu voids can be eliminated by reducing the impurities of the Cu electrochemical deposition (ECD) chemical solutions.

21 Conclusions 21

22 Conclusions q Via-middle between Cont and BEOL 3D-TSV scheme has become the mainstream for IC foundry. q WiW Cu film thickness range can be much improved from ~20000A to 1500A by ECD process optimization. q WtW and WiW ILD THK mapping range control can be <100A as ILD THK loss ~100A post P3 polishing. q TSV Cu recess can be continuously reduced from around 330A to 110A as polishing through platen 1 to platen 3 TSV-CMP process. 22

23 Conclusions q Severe Cu extrusion was easily found post TSV CMP cap and even post metal 3 cap layer deposition. q Cu extrusion of TSV is indeed a potential concern to result in metal and ultra-low k (ULK) film thinning and delamination or damage of the BEOL. q Increasing pre-tsvcmp anneal temperature could reduce Cu extrusion, but induce Cu voids issue. q TSV Cu voids can be eliminated by reducing the impurities of the Cu electrochemical deposition (ECD) chemical solutions. 23

24 Thank You! 24

Overview of CMP for TSV Applications. Robert L. Rhoades, Ph.D. Presentation for AVS Joint Meeting June 2013 San Jose, CA

Overview of CMP for TSV Applications Robert L. Rhoades, Ph.D. Presentation for AVS Joint Meeting June 2013 San Jose, CA Outline TSV s and the Role of CMP TSV Pattern and Fill TSV Reveal (non-selective)