Fabrication and Layout
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1 Fabrication and Layout Kenneth Yun UC San Diego Adapted from EE271 notes, Stanford University
2 Overview Semiconductor properties How chips are made Design rules for layout Reading Fabrication: W&E 3.1, 3.2.1, Design Rules: W&E
3 What To Build Transistors nmos and pmos Wires Many levels of (real) metal wires (aluminum and copper) Need low resistance (high conductivity) Oxide insulators between metal layers Contacts (hole in the oxide) between adjacent layers
4 Silicon Semiconductor Conductivity changed by adding impurities Impurities, called dopants, create either n- type or p-type regions Oxide is stable SiO 2 (quarz or glass) Great for sealing things from impurities Can be selectively patterned Etching can remove SiO 2 without harming Si
5 Doping Adding arsenic or phosphorous to intrinsic silicon increases conductivity By adding free electrons n-type since current is carried by negatively charged particles (electrons) Adding boron to intrinsic silicon increases conductivity By adding free holes p-type since current is carried by positively charged particles
6 Diode Junction between n-type and p-type regions form a diode I n+ p+ p+ n V
7 How To Build Transistor Diffusion made by adding (diffusing) impurities into silicon n+ (p+) diffusion has lots of impurities (dopants), so higher conductivity p (n) regions lightly doped p region formed first; n+ doped over parts of p region n+ dopant added after poly is down so that poly blocks dopant poly n+ n+ p
8 Two Transistor Types CMOS requires two types of substrates for isolation of transistors n-type for pmos p-type for nmos s g d cross section n+ n+ p p+ p+ n Substrate = p Substrate = n
9 Well: Local Substrate Base wafer type may be n-type: add pwell / p-type: add nwell Some have twin well n+ p+ p n pwell process n substrate
10 Well Requirement Well must be tied to a power supply to keep isolation diode reversed biased Using well contacts (ohmic connection to the well) n+ n+ p p+ p+ n Tied to GND Tied to Vdd
11 Well Contacts Formed by placing p+ doped region in pwell (n+ region in nwell) These regions make good electrical contact to the well (ohmic, not diode) Well potential equal to the diffusion potential Need to have at least one well contact in each well
12 What s On A Chip: Review Transistors Require silicon substrate, wells, two types of diffusion, poly Wires Many levels of (real) metal wires Oxide insulator between metal layers Contacts between adjacent layers
13 Fabrication Masks Chips Wafers Processing Processed Wafer
14 Basic Fabrication Steps Transfer image of the design to wafer (photolithography) Create layers (diffusion/oxide/metal) Ion implant for diffusion; shoot impurities at silicon Deposition for oxide/metal; usually chemical vapor deposition (CVD) Grow for oxide; place silicon in oxidizing ambient
15 Basic Processing Start with wafer at current step Spin on a photoresist Pattern photoresist with mask Step specific processing etch, implant, etc... Wash off resist
16 IC Fabrication Repeat Create layer on wafer Put photo-sensitive material (resist) on top of wafer Optically project image of pattern on water Develop resist Use resist as mask to prevent etch from reaching layer below, when transferring pattern to layer Remove resist All die on wafer processed in parallel; for some chemical steps, many wafers processed in parallel
17 Photolithography To transfer pattern onto wafer, first need an image to project Glass plate (mask) with image of pattern etched in chrome generated from design database Mask = negative in photography Image optically projected onto wafer using projection aligner projection aligner = enlarger in photography Mask allows printing on large number of wafers Cost per wafer low, assuming lots of wafers
18 Making Transistors 1. Implant N-Well 2. Define thin oxide; grow field oxide 3. Etch poly
19 Making Transistors 4. Implant threshold adjust 5. Implant source and drain
20 Making Wires 1. Deposit insulator; may be polished to make it fit 2. Etch contacts to Si; fill with conductor 3. Pattern metal wires
21 Foundry Interface Designer Layout (Mask Set) Foundry Design Rules Process Parameters
22 MAGIC MOSIS SCMOS Layers 4 types of diffusion Normal (forms transistor) ndiff pdiff Diffusion for well contacts nohmic pohmic Poly Metal M1 M2
23 Physical and MAGIC Layers Physical Masks (simplified) nwell active area (thin ox) poly threshold adjust (n & p) implant select (n & p) contact metal 1 via metal 2 glass Magic Layers nwell ndiff (active & nselect & ~nwell) pdiff (active & pselect & nwell) nnd (active & nselect & nwell) ppd (active & pselect & ~nwell) poly metal1 metal2 contacts
24 Layer Example
25 MAGIC Contacts + + = ndc - ndiff to metal1 pdc - pdiff to metal1 ppc - ppd to metal1 nnc - nnd to metal1 pc - poly to metal1 via - metal1 to metal2
26 Contact Example
27 Fabrication Constraints On Layout Resolution constraints Smallest printable feature / smallest spacing that guarantees no short Depends on lithography and processing steps Resolution often depends on smoothness of surface Alignment/overlap constraints Need to align layers (like printing color picture)
28 Geometric Design Rules Resolution width and spacing of lines on one layer Alignment to make sure interacting layers overlap (or don t) contact surround poly overlap of diff well surround of diff contact spacing to unrelated geometry 3 3
29 MOSIS SCMOS Design Rules Allow you to send designs to different fabs Rules are based on λ - half the drawn gate length (poly width) All other design rules expressed in multiples of λ Poly width = 2λ, space = 3λ metal width = space = 3λ Conservative Manhattan layout (only 90 degree angles)
30 SCMOS Design Rule Highlights Resolution rules Layer Width Space poly 2 3 diff 3 3 m1 3 3 m2 3 4 nwell 10 9 cut 2 2 via 2 3 Alignment rules cut/via surround 1 poly overlap diff 2 poly space to diff 1 Notes: Cut plus surround is 4 Layout falls on 8λ grid
31 Pitch Repeat distance between objects 8λ contacted transistor pitch cut + poly width + 2 x cut-to-poly 6.5λ semi-contacted m1 pitch (contact + width)/2 + spacing 7.5λ semi-contacted m2 pitch (contact + width)/2 + spacing 7λ fully contacted m1 pitch contact + spacing 8λ fully contacted m2 pitch contact + spacing 8λ
32 Contact Rules Spacing from contacts is slightly larger than from base material Poly contact to poly spacing = 3λ Diffusion contact (ndc, pdc, nwc, pwc) to diffusion = 4λ So that the fab can make surround of contact cut slightly larger than 1λ if necessary
33 Magic Number 8 Most of the important rules for estimating the size of stick diagram can be approximated by 8λ (diff width =4) diff w/c = 8 M2 w/c = 8 8 M1 w/c = 7 poly w/dc = 8 poly w/c = 7
34 Stick Diagrams Like a layout Basic topology of the circuit Relative positions of objects roughly correct But Wires have no width Size of objects not to scale Missing wires can be squeezed in between two wires
35 Layout Issues Two types of diffusion ndiff poly crossing ndiff makes nmos transistor pdiff poly crossing pdiff makes pmos transistor Cannot directly connect ndiff and pdiff must connect ndiff to metal and metal to pdiff Cannot get ndiff too close to pdiff because of wells large spacing rule between ndiff and pdiff need to group nmos transistors together and pmos transistors together
36 Basic Layout Planning Need to route power and ground (in metal) Keep nmos devices near nmos devices and pmos devices near pmos devices nmos near ground and pmos near Vdd Run poly vertically and diffusion horizontally with m1 horizontally Keep diffusion wires as short as possible just enough to make transistors All long wires in m1 and m2
37 Typical Cell Layout Plan Parity Inverter Vdd Gnd
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