Non-charge Storage Resistive Memory: How it works

Transcription

1 Accelerating the next technology revolution Non-charge Storage Resistive Memory: How it works Gennadi Bersuker Copyright 2009 SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.

2 Acknowledgement Results obtained in collaboration with: SEMATECH: David Gilmer, Chanro Park, Dmitry Veksler, Paul Kirsch Univ. of Modena: L. Larcher group Univ. College London: A. Shluger group Univ. of Barcelona: M. Nafria group 2

3 Memory benchmarking Switching Time (read+write) [ns] Nanowire Molecular NAND PC DRAM STT RR NW-PC NOR FeRAM MRAM NEMS Density AF 2 [1] W. Y. Choi, and T.-J. King Liu IEDM p. 603 (2007). [2] A. Driskill-Smith, Y. Huai Future Fab p. 28 (2007). [3] J. E. Green Nature v. 445 p. 414 (2007). [4] B. Yu IEEE Trans on Nanotech 7, p. 496 (2008). [5] Kryder, et. al. IEEE TRANS ON MAGNETICS, 45, NO. 10, (2009) low power (fj/bit) mid power (pj/bit) mid-hi power (low nj/bit) high power (nj/bit) SRAM small A = small cell Success Criteria: MLC similar to NAND $$ similar to NAND Function, reliability = NAND Density > NAND Speed > NAND RRAM, STT interesting. BL1 BL2 BL3 1F Unit cell = 4F 2 WL1 WL2 WL3 3

4 Which space should RRAM target? Conventional space: CPU Latency gap RAM DISK TAPE Possible Space for RRAM: Latency (ns) RRAM fills large latency gap between RAM and SSD Possible apps: 1) embedded RAM for logic, 2) storage class memory (data center), 3) NAND competitor. 4

5 Which space should RRAM target? Conventional space: CPU Latency gap RAM DISK TAPE Possible Space for RRAM: CPU RAM DISK TAPE Latency (ns) RRAM fills large latency gap between RAM and SSD Possible apps: 1) embedded RAM for logic, 2) storage class memory (data center), 3) NAND competitor. 5

6 Which space should RRAM target? Conventional space: CPU Latency gap RAM DISK TAPE Possible Space for RRAM: CPU RAM SCM SSD DISK TAPE Latency (ns) RRAM fills large latency gap between RAM and SSD Possible apps: 1) embedded RAM for logic, 2) storage class memory (data center), 3) NAND competitor. 6

7 Which space should RRAM target? Conventional space: CPU Latency gap RAM DISK TAPE Possible Space for RRAM: CPU RAM RRAM SCM SSD DISK TAPE Latency (ns) RRAM fills large latency gap between RAM and SSD Possible apps: 1) embedded RAM for logic, 2) storage class memory (data center), 3) NAND competitor. 7

8 Filament-based RRAM: Bi-polar operation RESET LRS Forming SET HRS X RRAM switching involves formation and manipulation of conductive filament focus of this presentation 8

9 Why the filament-based HfO 2 RRAM Expected advantages - scaling: limited by filament dimensions - retention: high barrier for spontaneous change of chemical bonds - speed: may require only limited atomic movement - energy: changes in small dielectric volume - fab-friendly material Challenges: forming is a random process - How to control CF - How to ensure uniformity Need to understand mechanism 9

10 Outline Need to address the following questions: Dielectric morphology responsible for switching Electrically-active defects associated with morphology How Forming occurs: Role of active defects Properties of conductive filament determined by forming process Filament characteristics in high and low resistive states 10

11 Dielectric properties: Correlation between morphology and electrical characteristics HfO 2 current topography C-AFM HfO 2 SiO2 Si Breakdown spot Height (nm) Topography 0 Current E Position (nm) I (na) Height (nm) 2.1 Topography Current Position (nm) Leakage path and breakdown along/at grain boundaries I (na) 11

12 Modeling grain boundaries in HfO 2 GB structure in HfO 2 (101) O-vacancies diffuses and precipitate at GB Vacancies form conductive sub-band along GB Conductive sub-band b (101) 1nm a 12

13 Conduction via grain boundaries Statistical multi-phonon trap assisted tunneling model Defect activation: V 2+ +e V + e e e O-vacancy defect V 2+ J.L. Lyons et al. Microel.Eng J / Jfresh Simulations: TiN/6nmHfO 2 /TiN J / Jfresh T=3 00K, V g=2v T=375K,Vg=2V T=3 75K,Vg=1.6V T=3 75K,Vg=1.8V t[s] Leakage current via charged oxygen vacancies V + : T=375K,Vg=1.8V (un-interrupt) T=375K,Vg=1.8V (interrupted) t[s] V + +e V 0 V + +e 13

14 Modeling RRAM operations: Forming Forming Pre-forming current is grain boundaries driven Current Density [A/ cm 2 ] E relax =1.19eV E T = eV Fresh Forming 25 C 50 C 75 C 100 C simulations V G [V] 14

15 Forming: Power dissipation during TAT transport Phonon emission associated with electron trapping 3D temperature calculation electrode HfO 2 metal HfO 2 Heat flow Finite thermal resistor metal h h e e electrode Grain boundary Radial heat flow vanishes within 4-5 nm from GB 15

16 Simulation of Forming process Electron trapping generates phonons lead to higher T promotes generation of new defects defect generation HfO 2 e h O G( T, F) e E act bf kt E act bf ox initial F ox Dissociation coordinate Defect generation by thermo-electrical stress 16

17 Forming process: vacancy generation along GB Current during Forming process averaged multiple GB Temperature-vacancies map anode anode GB evolved into CF cathode anode cathode anode Statistics of Forming voltages cathode cathode Generation rate: Eact 1 G( T, F) e g0 bf kt g 0 E act 10 ps 4.5eV b 90eA 17

18 Reset: Filament reoxidation I (x10-4 A) Temperature along CF Tempearature (x100 o C) Anode = / o C and mixed BC at electrods = / o C = Reset Theory Ohmic Distance (nm) Cathode Vg (V) Current [A] Voltage [V] (1 at ( T )) Ohmic RESET SET dt I =- r dx (r T - x/h (r T - r B )) FORMING h 0 (1 at ( ( x ) T 0 )) V r I r dx 2 (r T - x/h (r T - r B )) 0 Reset occurs when filament temperature is sufficient for oxidation 18

19 Current [A] High resistance state RESET through barrier Lines = model Symbols = data Ohmic FORMING Voltage [V] t barr TAT SET Ohmic transport Current [A] E relax =0.77eV E T =2.4eV E rel =0.7 ev E T = ev HRS state 25 C 75 C 100 C V G [V] HRS requires ~ 0.9 nm dielectric barrier between injecting electrode and filament 19

20 SET: Field-driven barrier breakdown 10-3 RESET SET 10-4 E, MV/cm 10 5 Anode Field distribution across cell V=0.6V along filament axis Current [A] Away from filament Voltage [V] d Cathode FORMING filament Field distribution around filament anode V = 0.6V dielectric Distance, nm cathode V=0 High field leads to breakdown of dielectric barrier 20

21 SET: Temperature profile after barrier breakdown Temperature (x100 o C) CF thermal conductivity: 0.12 W/Kcm CF radius at the cathode: ~ 0.5 dnm barrier d Anode Distance (nm) Cathode HfO HfO 2 2 CF O O- - filament dielectric cathode (c) (b) O- O - barrier High temperature/field leads to oxygen dissociation metallic filament propagates to electrode 21

22 RRAM switching mechanism Reset: filament tip oxidation temperature driven In HRS: TAT via barrier traps V- O- O- V+ metal O- O- d metal d Set: barrier breakdown field-driven d In LRS: Ohmic conduction O- V+ V- metal O- metal 22

23 Summary Grain boundaries define conduction path/filament location FORMING process generates oxygen deficient filament RESET temperature-driven reoxidation of the filament narrow tip SET field-induced breakdown of oxide barrier at the filament tip Switching is controlled by 3 major filament parameters: x-section, composition, barrier thickness 23