Sub-100 nm silicon-nitride hard-mask for high aspect-ratio silicon fins

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1 Sub-100 nm silicon-nitride hard-mask for high aspect-ratio silicon fins V. Jovanović, S. Milosavljević, L.K. Nanver, T. Suligoj*, P. Biljanović* ECTM-DIMES, Delft University of Technology, P.O. BOX 5053, 2600 GB Delft, The Netherlands; Tel: +31 (0) Fax: +31 (0) *University of Zagreb, Department of Electronics, Faculty of Electrical Engineering and Computing, Unska 3, Zagreb, Croatia Abstract A method for using hard-masks to achieve sub- 100 nm patterning of silicon is described. The process flow involves anisotropic etching of the silicon with spacers forming the hard-mask. licon dioxide and silicon nitride are investigated as possible spacer materials. licon nitride is shown to have advantages due to a better etch selectivity during the removal of the sacrificial island around which the spacers are formed. It is demonstrated that nitride spacers can be used as hard-masks for the reactive-ion etching (RIE) of silicon. Vertical silicon fins, 690 nm high and processed with an aspect-ratio of 29:1 and smooth sidewalls, were achieved on <110> bulk silicon wafers when silicon wet etching with TMAH was applied. A planarized oxide trench isolation of the base of the TMAH-etched fins is demonstrated. It opens the possibility of processing FinFETs with different channel-widths. I. INTRODUCTION With the continued downscaling of integrated circuits, the patterning requirements are becoming ever more challenging [1], [2]. Optical lithography tools still remain the equipment of choice for semiconductor foundries due to their high throughput capacity. However, high-end optical wafer steppers with resolution in the sub-100 nm range are usually prohibitively expensive for smaller research groups such as university laboratories. The possibility to pattern dimensions smaller than 100 nm is offered by the electron-beam lithography, but at the cost of slow processing that severely limits the number of wafers and wafer area that can be patterned. In view of these limitations the option of achieving small lateral dimensions by the application of hard-masks processed by lowerresolution wafer-stepper lithography is becoming more attractive [3]. Hard-masks offer the ability to pattern very small dimensions without limitations on the wafer area that can be processed. The trade-offs are the added processing steps needed for the creation of hard-masks and the requirement that these extra steps can be integrated in the rest of the fabrication process. In this paper, the use of silicon-nitride hard-masks for silicon fin etching is demonstrated. Thin silicon fins are attracting great interest since the FinFET structure has become a candidate for future CMOS devices [4]. The width of silicon fins depends on the gate-length of FinFETs and is being scaled with the gate-length. In order to keep short-channel effects at an acceptable level the finwidth needs to be smaller than the channel-length and it therefore becomes the smallest dimension in FinFETs. Additionally, high anisotropy of fin etching is desired to achieve uniform fin-width, i.e., uniform transistor body thickness along the channel. Good quality of the etched silicon sidewalls is also necessary for high MOSFET performance. The process flow for the fabrication of hard-masks in the sub-100 nm range is presented in Section II of this paper. The issues related to the application of either silicon nitride or silicon dioxide as hard-masks for fin-etching are discussed, followed by a demonstration of the implementation of silicon-nitride hard-masks. These hardmasks are used for silicon fin-etching by RIE or wet crystallographic etching and results are presented in Section III. A planarized oxide trench isolation of the base of very high aspect-ratio, ideally vertical silicon fins is demonstrated in Section IV. II. SILICON-NITRIDE HARD-MASK The process flow for the spacer formation and etching of the underlying layer with spacers as a hard-mask is displayed in Fig.1. First, the layer of sacrificial material () is deposited and patterned using the available lithography system. In the present work, the i-line optical lithography tool with a minimum pattern definition of (a) (c) (e) (g) Fig. 1. Spacer hard-mask formation and etching. Material to be etched (a). The layer of the sacrificial material is deposited (b). The sacrificial layer is anisotropicaly etched (c) and the conformal spacer layer is deposited (d). The spacers are formed by anisotropic etching of (e) and the islands of sacrificial material are removed (f). The spacers are used as the hard-mask for the anisotropic etching of (g). If required, the spacers can be removed (h). (b) (d) (f) (h)

2 500 nm was used. The sacrificial layer is etched by reactive-ion etching with a high level of anisotropy to achieve highly-sloped sidewalls. Next, conformal deposition of the layer to be used as spacer material () is performed. The width of the final hard-mask is determined by the thickness of the spacer layer, allowing precise control of the hard-mask dimensions. Spacers are formed around the sacrificial island by RIE of the spacer material and the island is subsequently removed by wet chemical etching. Deviation from the 90 sacrificial island sidewall angle leads to a certain loss of spacer thickness during spacer RIE and results in a tilted spacer hard-mask. Therefore, it is an advantage to etch the profile of the sacrificial island as perpendicularly as possible. Additionally, the removal of the sacrificial island needs to be highly selective to the spacer material. With very small spacer width, any etching of the spacer hard-mask during this step can remove a significant part of the hard-mask so it is important to use a very selective etching solution. The free-standing spacers are then used for the etching of the underlying material and, if desired, they can later be removed. Experiments with silicon nitride and silicon dioxide as sacrificial/spacer materials were performed. Both materials can be conformally deposited by LPCVD and etched anisotropically by RIE as well as with high selectivity by wet chemical solutions. In addition, silicon can be etched selectively to these materials allowing their use as hardmasks. The wet chemical etching of the sacrificial islands was examined by measuring the selectivity of the etching solutions with respect to silicon dioxide and nitride. The oxide and nitride layers were deposited by LPCVD at a temperature of 700 C and 850 C, respectively. The wet etching of silicon nitride by ortho-phosphoric acid heated to 157 C gave a selectivity of roughly 1:6 to the LPCVD oxide. This value is not enough for the preservation of thin spacers during island removal. For the silicon dioxide etching, a buffered-hf (1:7) solution was used and showed almost no LPCVD nitride loss. On the basis of these results the choice was made to use LPCVD silicon oxide as sacrificial material and LPCVD silicon nitride as spacer material. The nitride-spacer height is designed to meet the requirements for etching of the underlying silicon. The Fig. 2. SEM image at 45 tilt of the silicon-nitride spacers obtained from a 30 nm thick low-stress silicon nitride layer. A part of the spacer field is shown in the inset in the top-left corner. present work is focused on the etching of silicon fins with high aspect-ratio. For this purpose, the wet etching of silicon on <110> orientated wafers with TMAH was used. Etching in TMAH is highly selective to silicon nitride and the spacer height is not important for this step. However, silicon fins are typically etched using RIE, which has less selectivity to other materials. Therefore, the investigation of nitride hard-masks included silicon RIE to obtain silicon-fin heights between 500 nm and 1 μm. In this case, the height of the hard mask needs to be adjusted to protect the covered part of the silicon during etching and it was assumed that the height of the hard-mask of 300 nm or more would be sufficient. Additionally, the loss of spacer height during nitride RIE (Fig.1.e) needs to be accounted for. Therefore, the thickness chosen for the sacrificial islands was 500 nm. The deposited thicknesses of the nitride layers were 100 nm, 50 nm and 30 nm. The anisotropic etching of silicon dioxide and nitride by RIE was done using a fluorine-based chemistry. The oxide is etched with CHF 3 and C 2 F 6 gasses (4:1 ratio) and shows a selectivity of 10:1 to silicon, resulting in a small loss of the underlying silicon during sacrificial island etching. The nitride RIE uses only C 2 F 6 and has a high physical etching component that gives low selectivity to both silicon and oxide. Therefore, a more precise etch-time control is required to prevent large loss of hard-mask height during spacer etching. However, to insure that the spacer material is completely removed from silicon and oxide surfaces, some degree of overetch had to be included in this step. The measured oxide island height showed that approximately 60 nm of oxide was removed in this step and it can be assumed that the same value of the spacerheight was also lost. The scanning-electron microscopy (SEM) images of the nitride spacers are given in Fig. 2. The measured spacer height of 436 nm corresponds well with the measured loss of oxide island thickness. The inset shows excellent control of the spacers, even for the smallest dimensions of 30 nm. A visible inward tilt of the spacers is the consequence of the slope of the spacer island profile after silicon dioxide RIE. III. SILICON ETCHING WITH HIGH ASPECT-RATIO A. licon fin etching by RIE The silicon-nitride hard-mask was used for the anisotropic etching of silicon. licon was etched in the Trikon Omega 201 inductively-coupled plasma (ICP) etcher with the combination of chlorine and hydrogenbromide gasses. The HBr/Cl 2 based RIE showed good results (Fig. 3.) with tall silicon fins of approximately 1.1 μm in height. The spacer hard-mask formed around the initial 500 nm tall oxide islands provided adequate masking for the etching. Most of the spacer-height loss is actually due to the nitride RIE used to form the spacer and not the silicon RIE. The etched silicon fins are not perfectly vertical, but have a trapezoidal shape. Moreover, the SEM of the side-view of the etched silicon sidewalls reveals some roughness, which could be detrimental to the performance of devices built on the sidewalls. The achieved aspect ratio of the RIE fins is approximately 6.3:1, which is enough for FinFET applications [5].

3 Fig. 3. SEM image at 30 tilt of the silicon fin formed by the RIE with HBr/Cl 2 plasma and a nitride hard-mask. The LPCVD low-stress silicon nitride used for spacers was 100 nm thick. The fin and the spacer heights are 1.1 μm and 410 nm, respectively. The top-view of the structure is shown in the inset. B. licon fin etching by TMAH The wet crystallographic etching was examined for the application of tetramethylammonium-hydroxide (TMAH) on wafers with a <110> orientation of the top surface. licon etching in alkaline solutions, such as TMAH, is highly anisotropic with respect to the crystal orientation of the exposed surface and shows very low etch-rates in the [111] direction. This property was used here to etch vertical silicon fins on <110> silicon wafers, where <111> planes are found perpendicular to the top surface and parallel to the primary flat. The etching anisotropy between different planes increases with concentration and temperature of the solution (Table I). A solution of 25% TMAH in DI water heated to 85 C was used in our experiments. The SEM image in Fig. 4. shows excellent quality of TMAH-etched silicon fins. The etched profile depends on the crystal orientation of the wafer with the high etching anisotropy resulting in nearly vertical silicon fins with constant width. As a result of high etch anisotropy and high selectivity to the nitride hard-mask an extremely high aspect ratio of 29:1 is achieved. Moreover, on bulk silicon wafers, the height of the silicon fins can be further increased, limited only by the silicon fin mechanical stability. The SEM images also show very smooth sidewalls, which is evidence of good surface Fig. 4. SEM image of the silicon fins etched by 25% TMAH solution at 85 C. The LPCVD low-stress silicon nitride used for the spacers was 50 nm thick. Inset on the left side shows the fin cross-section. The fin height and width are 690 nm and 22 nm, respectively. quality. With wet crystallographic etching there is no ion damage on the sidewalls and it is expected that the resulting surfaces have significantly better quality than the ones etched by RIE. Tall silicon fins with high aspect ratio offer the possibility of FinFETs with much wider transistor channels than typically achieved today [8], [9]. IV. SILICON FIN ISOLATION By using bulk silicon wafers for fin fabrication instead of SOI wafers the process cost is significantly reduced. In addition, there is more freedom in choosing the fin height with the possibility of achieving very tall fins. However, the etched fins remain electrically connected through the substrate and an isolation layer needs to be placed between O 2 N X Photoresist O 2 N X TABLE I TMAH ETCHING RATES (a) (b) TMAH, 20%, 79.8 C [6] Etching rate ( μm/min) Etching-rate ratio TMAH, 25%, 70 C [7] Etching rate ( μm/min) Etching-rate ratio TMAH, 25%, 85 C Etching rate ( μm/min) Etching-rate ratio O 2 (c) N X O 2 (d) N X Fig. 5. The isolation of the silicon fins on bulk silicon wafer. The fins are covered with thick conformal oxide layer (a) and coated with photoresist (b). A RIE process with the same etch-rate for photoresist and the deposited oxide is performed (c). The active part of the fin is exposed by the wet chemical etching of oxide (d).

4 performance BiCMOS with the Horizontal Current Bipolar Transistor (HCBT), as proposed in [11]. V. CONCLUSION Fig. 6. SEM image of the silicon fin isolated with the LPCVD oxide. The oxide planarization was done using the photoresist and the RIE of the photoresist and the oxide. The visible step at the base of the fin comes from the short TMAH step before nitride deposition. the top section of the fin and the substrate. The isolation is typically achieved by a combination of shallow-trench isolation and subsequent oxide etch-back [10]. Here, the etched silicon fins are first covered by a thick, conformally deposited oxide layer, which is then planarized, followed by the oxide etch-back (Fig. 5.). The isolation procedure was investigated for the tall fins etched in TMAH. An additional short etching step in TMAH was performed after the oxide sacrificial-island formation to produce a vertical sidewall before the silicon nitride deposition. This was done in order to form vertically aligned nitride spacers, albeit only at the bottom part, rather than the tilted spacers resulting from the nitride alignment to the oxide island. The isolation process starts with the deposition of 1.5 μm thick LPCVD oxide that was densified at 1050 C for one hour. The surface was then planarized by coating of a 2 μm thick photoresist, followed by RIE of the photoresist and the oxide in the same step. The plasma used etches both the photoresist and the oxide with roughly the same etch-rate, resulting in a planarized surface. Finally, oxide etch-back was carried out by using buffered- HF solution to expose the top part of the silicon fin/nitride hard mask structure. The SEM image in Fig. 6. shows the TMAH-etched silicon fin isolated by the deposited oxide. The height of the active part of the fin, which corresponds to the transistor width is determined by the oxide etch-back and can be different for different devices if an additional lithography step is used for device selection. This removes the limitation that a single-fin FinFET can only have one channel width and that larger devices must have a channel width that is an integer multiple of single-fin device channel-width. Depending on the number of lithography steps applied, several single-fin channel widths can be achieved on tall, TMAH-etched silicon fins. Moreover, the bulk silicon FinFET can be integrated into high The processing of the silicon-nitride spacers with dimensions down to 30 nm has been demonstrated. An excellent control of the spacer dimensions can be achieved with the proper choice of processing materials and dimensions. When used as the hard-mask for anisotropic etching of silicon, nitride spacers have been shown to effectively mask the underlying silicon. In the case of silicon RIE, the spacer-height was adjusted to etch 1 μm tall silicon fins and the aspect-ratio of 6.3:1 was achieved with sloped sidewalls. The application of wet crystallographic etching with TMAH resulted in vertical silicon fins with an extremely high aspect-ratio of 29:1. Moreover, the SEM images show very smooth silicon sidewalls and it is assumed that the observed sidewall quality is sufficient for the processing of FinFETs. Trench isolation of the TMAH-etched tall silicon fins on <110> bulk silicon wafers is demonstrated. An advantage of the very tall silicon fins, is that it is possible to process singlefin FinFETs with different channel widths. Additionally, integration with advanced devices, such as HCBT, can be achieved. Compared to the use of SOI wafers to achieve fin isolation, our tall FinFET technique is thus much cheaper and more versatile. ACKNOWLEDGEMENTS The authors would like to thank the staff of the DIMES IC-processing group for their assistance during the fabrication of the experimental material. REFERENCES [1] Yuan Taur and Tak H. Ning,, Fundamentals of modern VLSI devices, Cambridge University Press, 1998, ch. 3,4,5 [2] James D. Plummer, Michael D. Deal, and Peter B. Griffin, licon VLSI technology, Prentice Hall, 2000, ch. 2, 5, 9 [3] Yang-Kyu Choi, Tsu-Jae King, and Chenming Hu, A spacer patterning technology for nanoscale CMOS, IEEE Trans. Electron Devices, vol. 49, no. 3, pp , March [4] Digh Hisamoto, Wen-Chin Lee, Jakub Kedzierski, Hideki Takeuchi, Kazuya Asano, Charles Kuo, Erik Anderson, Tsu- Jae King, Jeffrey Bokor, and Chenming Hu, FinFET-a selfaligned double-gate MOSFET scalable to 20 nm, IEEE Trans. Electron Devices, vol. 47, no. 12, pp , December [5] Jakub Kedzierski, Meikei Ieong, Edward Nowak, Thomas S. Kanarsky, Ying Zhang, Ronnen Roy, Diane Boyd, David Fried, and H.-S. Philip Wong, Extension and source/drain design for high-performance FinFET devices, IEEE Trans. Electron Devices, vol. 50, no. 4, pp , April 2003 [6] Mitsuhiro Shikida, Kazuo Sato, Kenji Takoro, and Daisuke Uchikawa, Comparison of anisotropic etching properties between KOH and TMAH solutions, Proc. MEMS 1999 Twelfth IEEE Intl. Conference on Micro Electro Mechanical Systems, Jan , 1999, pp [7] K. Sato, M. Shikida, T. Yamashiro, K. Asaumi, Y. Iriye, and M. Yamamoto, Anisotropic etching rates of single-crystal

5 silicon for TMAH water solution as a function of crystallographic orientation, Proc. MEMS 1998 The Eleventh Annual Intl. Workshop on Micro Electro Mechanical Systems, Jan , 1998, pp [8] Y. X. Liu, K. Ishii, T. Tsutsumi, M. Masahara, H. Takashima, and E.Suzuki, Ultra-narrow rectangular crosssection -fin channel double-gate MOSFETs fabricated by using orientation-dependent wet etching, Proc. Device Research Conference, June 23-25, 2003, pp [9] Yongxun Liu, Meishoku Masahara, Kenichi Ishii, Toshihiro Sekigawa, Hidenori Takashima, Hiromi Yamauchi, and Eichii Suzuki, A highly threshold voltage-controllable 4T FinFET with an 8.5-nm-thick -fin channel, IEEE Electron Device Letters, vol. 25, no. 7, pp , July [10] T. Suligoj, and K.L. Wang, A Novel Isolation of Pillar-like Structures by the Chemical-Mechanical Polishing and Etch- Back Process, Electrochemical and Solid-State Letters, Vol. 8, No. 5, pp , May [11] T. Suligoj, J.K.O. n, and K.L. Wang, Horizontal Current Bipolar Transistor (HCBT) Process Variations for Future RF BiCMOS Applications, IEEE Trans. On Electron Devices, Vol. 52, No. 7, pp , July 2005.

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