Research Activities on Defect Improvement of CMP Process in 1x nm Foundry Device
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1 Research Activities on Defect Improvement of CMP Process in 1x nm Foundry Device 1JI CHUL YANG, 2Hong Jin Kim, 2Venu. Govindarajulu,1Dinesh Koli and 2Jason Mazzotti 1 CMP, Advanced Technology Development (ATD), 2 CMP, Advanced Module Enginnering (AME)
2 Confronting Reality in semiconductor field. Scaling Challenges Device Structure Flow Complexity Critical Insights Needed to Manage Dynamics New Material Introduction Complex Interdependencies 2
3 Number of Step (A.U) CMP is becoming COMPLEX! 16 TSV Cu Cu 14 TSV Cu W-CA/CB Cu SIOC 12 W-CA/CB TI ILD 11 RM GP MOL MOL 10 W-TS MO 9 W-Gate SiN Cap 8 TSV Cu POC W-Gate Cu ILD2 ILD2 6 W-CA/CB ILD1 ILD1 5 MOL W-TS FEOL GP TI ILD Cu Al Gate MO FEOL GP 3 W ILD2 RB MO BEOL 2 Oxide ILD1 STI2 Nit Buff MOL FEOL 1 STI STI STI1 STI FEOL 28nm 20nm 14nm 10nm CMP steps doubled from 28nm to 10nm node in order to enable new integration schemes such as replacement metal gate or self-aligned contact. Higher increased in 10nm CMP steps at MOL due to the complexity of contact module from gate and contact engineering. 3
4 CMP process challenges Selectivity Materials FEOL: SiN, Ox MOL: SiN, Ox, W, TiN, Al BEOL: Cu, Ta, TaN, TiN FEOL: Si, SiN, Ox, a-si MOL: W, SiN, Ox, poly Si, New Materials BEOL: Cu, Ta, TaN, TiN FEOL: Si, SiN, Ox, low k MOL: W, SiN, Ox, poly, New materials BEOL: Cu, Ta, TaN. Lower Resistivity material. Dishing/ Erosion Higher PD < 100 (A.U) Higher PD <83 (A.U) Higher PD < 66 (A.U) Uniformity (100x100um) 3sigma < 100 (A.U) 3sigma < 66 (A.U) 3sigma < 46 (A.U) 20nm 14nm 10nm More new materials are expected in the future nodes in order to meet stringent process requirement in CMP 4
5 Increasing challenge in 3 D s ICPT 2015 keynote Speaking material, Mark Doherty, GF Within-die uniformity Within-wafer uniformity Silicon Wafer Within-macro uniformity Must deliver minimal & stable non-uniformity
6 ICPT 2015 keynote Speaking material, Mark Doherty, GF Increasing challenge defect translation FEOL CMP BEOL CMP Increased # layers = increased defect translation GLOBALFOUNDRIES Confidential 6
7 Unforgettable and endless problem in CMP Micro and Nano Scratches GLOBALFOUNDRIES Confidential 7
8 Improvement activities for Micro Scratches GLOBALFOUNDRIES Confidential 8
9 Nanoparticle Abrasive Conventional Abrasive Micro/nano scratch density (relative) Nanoparticle-Ceria: CMP Performance Venu. at el. CMPUGM AVS Jul. 11, 2016, Austin USA Case I: Poly CMP Case II: Inter-layer Dielectric (ILD) Macro to Macro Variation Nanoparticle-ceria abrasive Slurry Nanoparticleceria abrasive Slurry Nano-sized cerium hydroxide slurry buffing Lot IDs Macro 1 Macro 2 Macro 3 Nano-ceria based slurry showed microscratch reduction in multiple process steps with different integration scheme, however most processes are limited to buffing CMP only so far Planarity and selectivity control is the key challenges (i.e., proper slurry chemistry) with nano-scale abrasive application for CMP slurry (removal rate is tunable with easy and comparable to conventional ceria based slurry) 9
10 Soft Pad Effect on Microscratch Venu. at el. CMPUGM AVS Jul. 11, 2016, Austin USA Microscratch Trend Post CMP Pad Thickness: Planarity Soft pad Soft pad Removal Rate: ~10% drop Soft pad Microscratch reduction can be achieved by soft pad implement, however, planarity and removal rate degraded either (this is reported many times in different conferences, publications, and business reports). For the soft pad application, proper pad conditioning is necessary to maintain polishing performances. 10
11 Venu. at el. CMPUGM AVS Jul. 11, 2016, Austin USA Process Scheme for Microscratch Reduction CMP: Scratch generating process and scratch removal process as well! Non-selective buffing CMP help to scratch reduction selectivity and uniformity control is challenge for this application 11
12 JI Chul Yang, 60 th KCMPUGM, Suwon, South Korea, 2015 Conditioner Design Change to improve scratches Advantages of CVD Tip Formation Guaranteed Quality No Design Limitation : tip to tip distance, Tip height distribution, etc. Can control pad surface roughness and polishing Debris Tip Height Control A C B C A 3D Patterning H1 H2 H1(H A -H B ), H2(H B -H C ) controlling GLOBALFOUNDRIES Confidential 12 Working with SHINHAN Diamond & 3M GLOBALFOUNDRIES Confidential 12
13 Strategies for Scratch Mitigation Soft Pad w/ Proper Conditioning Ultrafine Abrasive Particle Recipe Optimize (Low Down Force, Slurry Flow) Cleaner Brush Treatment CMP Friendly Process Scratch SOLELY can be minimized? 13
14 In-Wafer Uniformity (iapc) GLOBALFOUNDRIES Confidential 14
15 Challenges of CMP Process Incoming height variation: variation in multiple upstream processes add up Removal rate drop as pad life (removal rate stability) CMP loading effect on removal rate - Polishing rate is not constant - Sinusoidal removal behavior observed - Early stage of polishing (< 10s) is not predictable
16 iapc: Integrated Advanced Process Control /types-of-metrology-equipments/ Implement of on-board metrology CMP In-situ Metrology
17 Hong Jin Kim, at el. TechConnect June Washington, DC, USA iapc Algorithm and Process Sequence Rework time adjusted Main CMP On board Metro On target Rework CMP Out of target RW removal rate set RW time cal. RW time adjusted Post thickness - target RW removal rate reset Feedback to the next rework Polishing time set by self-learning process: Empirical
18 Gate Height Control with iapc Hong Jin Kim, at el. TechConnect June Washington, DC, USA Without iapc With iapc Incoming process variability CMP needs to accommodate and compensate it and tight gate height control in-situ (or real time) process control improve wafer to wafer variation
19 Contact W CMP with iapc Hong Jin Kim, at el. TechConnect June Washington, DC, USA >50% Reduction in raw level delta to target (contact height) Contact CMP Contact height
20 Cu CMP with IAPC [Invited Talk] Ji Chul Yang, 60 th anniversary Korean CMP User Group Meeting, Defect Reduction of CMP process in Logic Device Suwon, Korea, Nov Example of Rs control by iapc Cu CMP With integrated APC With integrated APC Without integrated APC WTW Rs control demonstrated and in use Need further WID/WIW/WTW enhancement Endpoint improvements (On-platen / In-situ?) GLOBALFOUNDRIES Confidential 20
21 Ji Chul Yang, at el. ICPT2015, Sep. 30 Oct. 2, Arizona, USA In-situ Cu height control with Barrier EPD and Dielectric removal amount control In-situ monitoring flow 1. Cu CMP 2. Barrier CMP Start 2-1. Barrier Clear 2-2. Dielectric Removal Amount Control 1. Cu CMP - > Cu clear + O.P. 2. Dielectric removal amount control with in-situ optical sensor
22 Cleaner Defect GLOBALFOUNDRIES Confidential 22
23 Cu CMP Defect lots of cleaner defect type Ring Scratches Brush Particle Organic Residue Cu Flake GLOBALFOUNDRIES Confidential 23
24 Recipe Test - Recipe is major driven solution for CMP defect GLOBALFOUNDRIES Confidential 24
25 Brush Surface Modification No Treatment With Treatment Working with Rippey GLOBALFOUNDRIES Confidential 25
26 Changing profile by different Process condition Cu Protrusion GLOBALFOUNDRIES Confidential 26
27 Removal Efficiency Tool Configuration for effective cleaning [Invited Talk] Ji Chul Yang, 60 th anniversary Korean CMP User Group Meeting, Defect Reduction of CMP process in Logic Device Suwon, Korea, Nov Target 100 % Performance Two Fluld Jet Typical Brush Mag Tank & IPA Dryer Pencil Brush Particle Size GLOBALFOUNDRIES Confidential 27
28 In Conclusion, Fundamental Studies Structures & Materials Defect-Preventive Process Design Selectable Selectivity Advanced Diagnostics (FDC, SPC sensor) Manufacturing-Friendly Equipment Design Defect Management The Next Silver Bullet 28
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