EE 560 FABRICATION OF MOS CIRCUITS. Kenneth R. Laker, University of Pennsylvania

Transcription

1 1 EE 560 FABRICATION OF MOS CIRCUITS

2 2 CMOS CHIP MANUFACTRING STEPS Substrate Wafer Wafer Fabrication (diffusion, oxidation, photomasking, ion implantation, thin film deposition, etc.) Finished Wafer Wafer Probe Tests Finished Integrated Circuits Final Tests Packaging (encapsulation) Visual Inspection Chip Separation

3 CMOS PROCESSING TECHNOLOGY 3 DIFFUSION PROCESS Boron atoms deposited on surface n High Temp Treatment (> 800 o C) p n Impurity Concent - atoms/cm Impurity Concent - atoms/cm 3 N P N SUB Depth x - µm N SUB Depth x - µm -> Boron typically used for p-type doping -> Arsenic and Phosphorus are typically used for n-type doping.

4 4 PHOTOLITHOGRAPHY SiO 2 UV Mask Light n n > > > > n n n p-type Impurities p n Photoresist Window Methods for inserting impurity atoms into Si substrate Diffusion (high temperature) Epitaxial growth followed by diffusion Ion implantation (high velocity)

5 Local Oxidation of Silicon (LOCOS) 5 -> Fabricate thin SiO 2 layer adjacent to THICK SiO 2 layers. -> Transition from THICK to thin SiO 2 layers fabricated WITHOUT creating sharp vertical transitions. (a) SiO 2 (b) SiN SiO 2 (c) smooth transition SiO 2 Si Si Si SiN acts as barrier to oxygen atoms, stops further oxidation at SiN-SiO 2 interface.

6 6 A FABRICATED n-mos TRANSISTOR source metalization polysilicon gate drain metalization field oxide n+ gate oxide n+ source diffusion drain diffusion p -substrate field oxide

7 Create n-well regions & channel stop regions. 7 Simplified process sequence for the fabrication of an n-well CMOS IC with a single polysilicon layer Grow field oxide (thick oxide) & gate oxide (thin oxide). Deposit & pattern polysilicon layer. Implant source & drain regions, substrate contacts. Create contact windows, deposit & pattern metal layer.

8 Fabrication Steps in Si-Gate NMOS Process 8 Patterning SiO 2 Layer SiO 2 Thin Oxide Gate Oxidation 100A - 300A Polysilicon Patterning Polysilicon 0.5 µm - 2 µm Source, Drain Inplants or Diffusions (self aligned) n + n + implant of impurities 1 µm deep Contact Cuts Patterning Al Layer n + n + SiO 2 by deposition n + n + Aluminum contacts

9 9 Parasitc MOS Transistor or Field Device

10 Typical N-Well CMOS Process Physical Structure Mask Top View 10 nitride oxide p-channel stop thick field oxide n-well n-well photoresist n-well n-well n-well active channel stop n-well polysilicon n + n + p n-well + n + mask

11 11 n + n + p n-well + n + mask n + n + n-well mask p n + n + + n-well contact mask p n + n + + n-well metal mask

12 CMOS INVERTER LAYOUT IN AN N-WELL CMOS PROCESS 12 V in V SS G G S B D D B S V out COLOR LEGEND n-well V DD V in n + Polysilicon Gate Oxide Field Oxide Metal 1 Metal 2 Metal 3 Contact/via V out V DD V SS V DD V out V SS n + n + n + n-well

13 13 CMOS INVERTER IN TWIN-WELL CMOS PROCESS V in COLOR LEGEND n-well p-well n + Polysilicon Gate Oxide Field Oxide Metal 1 Metal 2 Metal 3 Contact/via V out V DD V SS V DD V out V SS n + n + n + n-well p-well epitaxial layer n + -substrate

14 14 CMOS PROCESS ENHANCEMENTS 1. INTERCONNECT A. Metal Interconnect (two, three, four or more levels) B. Polysilicon (two or more levels, also for high quality capacitors) C. Polysilicon/Refractory Metal Inteconnect D. Local Inteconnect 2. CIRCUIT ELEMENTS A. Resistors B. Capacitors C. Electrically Alterable ROM (EAROM - EEROM - EEPROM) D. Bipolar Transistors

15 COLOR LEGEND via hole field oxide substrate Metal 2 Metal 1 field oxide contact cut 15 n-well n + Polysilicon via spearation usually required contact LOCAL INTERCONNECT Gate Oxide Field Oxide Metal 1 Metal 2 Metal 3 Contact/via contact local interconnect (direct connect between poly and diffusion) V DD stacked via/contact

16 (A) Polysilicon/Refractory Metal or Silicide Gate/Interconnect Structures V DD Silicide V out V SS 16 n + n-well Silicide Gate (e.g. silicon and tantalum) Doped Polysilicon: R sheet = 20 to 40 Ω/Square Silicide: R sheet = 1 to 5 Ω/Square n + n + (B) Polysilicon V DD Silicide V out V SS n + n + n + n-well Polysilicon/Silicide (Polycide) Gate

17 17 (C) Polysilicon V DD Silicide V out V SS n + n + n + n-well Self-Aligned Polysilicon/Silicide (Salicide) (i) Polysilicon/silicide gate, (ii) Silicide source/drain(s) n +

18 CMOS DOUBLE POLY CAPACITORS 18 Poly 2 B T B T Poly 1 p n Capacitor SiO 2 layer ( A) C B T C = C oxc WL C oxc = ε ox t oxc

19 RESISTORS 19 W L R = ρ L t W = ρ = resistivity t = thickness L = conductor length W = conductor width R s = sheet resistance Ω/sq k = R L s W Ω R c = k L W Ω 1 µc ox (V gs V T ) L W Typical Sheet Resistance for Conductors (R s - Ω/sq) Material Min Typ Max Metal - Meal Metal Polysilicon Silicide n +, Diffusion n-well 1K 2K 5K MOS Resistor

20 20 EEPROM TECHNOLOGY field oxide inter poly oxide tunnel oxide n + n + control gate floating gate I FN = C 1 WLE 2 ox e E o /E ox where E ox = V gs t ox electric field across tunnel oxide E 0 and C 1 are process dependent constants

21 21 BIPOLAR TRANSISTORS IN STANDARD CMOS Substrate pnp Bipolar Transistor E B C D S V SS n + n + n + n-well

22 LAYOUT DESIGN RULES 22 PHYSICAL LAYER: prescription for preparing photomasks used in fabrication of ICs. Specify to the designer geometric constraints on the layout artwork so that patterns on the processed wafer will preserve the intended topology and geometry of the design. PURPOSE: realize fabricated circuits optimum yield in smallest area possible without compromising the reliability of the circuit. DESIGN RULE WAIVER: any significant and/or frequent departure from design rules. TWO TYPES OF DESIGN RULES: a. line widths and separations b. interlayer registration DESIGN RULE SPECS: a. 'micron' rules - minimum feature sizes and spacings in µm units (normal spec in industry) b. 'lambda (λ)' rules - minimum feature sizes and spacings speced in terms of a single parameter λ (popularized by Mead and Conway and permits first order scaling)

23 LAYOUT DESIGN RULES 23 The Design Process can be Abstracted to Manageable Number of Layout Levels that Represent the Physical Features on the Processed Silicon Wafer, i.e. -> Two different substrates (i.e. original substrate + well or twin wells) -> Doped regions p- and n- transistor forming materials (e.g. sources and drains) -> Transistor gate electrodes -> Interconnect paths -> Interlayer contacts

24 COLOR LEGEND n-well p-well n + Polysilicon CMOS N-WELL DESIGN RULES A1 = 10λ wells at same potential A2 = 6λ wells at different potential A2 = 8λ 24 Gate Oxide Field Oxide Metal 1 Metal 2 Metal 3 B1 = 3λ B2 = 3λ B5 = 5λ B4 = 3λ B3 = 5λ B6 = 3λ Contact/via B1 = TEXT - R1 B2 = TEXT - R2 C1 = TEXT - R3 C2 = TEXT - R4 C3 = TEXT - R6 C4 = TEXT - R5 C5 = TEXT - R7 C1 = 2λ C2 = 2λ C3 = 1λ C5 = 3λ C4 = 2λ Kenneth R. Laker, University of Pennsylvani

25 COLOR LEGEND n-well p-well n + E1 = 2λ E5 = 1λ E3 = 2λ F2 = 3λ F1 = 3λ 25 Polysilicon Gate Oxide Field Oxide Metal 1 Metal 2 Metal 3 Contact/via E1 = TEXT - R10 E2 = TEXT - R11 E5 = TEXT - R12 E6 = TEXT - R13 E3 = TEXT - R16 E4 = TEXT - R17 E7 = TEXT - R18 E8 = TEXT - R14 E9 = TEXT - R20 E10 = TEXT - R19 F1 = TEXT - R8 F2 = TEXT - R9 E2 = 2λ E6 = 1λ E7 = 1λ E4 = 1λ E8 = 3λ E9 = 6λ E10 = 3λ J3 = 2λ I2 = 3λ G1 = 2λ J1 = 8λ G3 = 1λ I1 = 2λ H1 = 3λ J2 = 2λ J2 = 5λ G4 = 1λ G2 = 3λ H2 = 4λ

26 EFFECT OF INSUFFICENT GATE EXTENSION 26 over-etched poly shrinks drawn region diffusion bloats processed region drawn poly region source, drain short processed poly region gate extension (C4)

27 27 EFFECT OF INSUFFICENT SOURCE-DRAIN EXTENSION source diffusion mask is poly mask is shifted left shifted right drawn region gate processed region drain drawn poly region mask misalignment changes width of device and sometimes completely eleminates it. processed poly region contact

28 28 TECHNOLOGY RELATED CAD ISSUES TWO BASIC CHECKS MUST BE COMPLETED TO ENSURE THE MASK DATBASE DEVELOPED IN LAYOUT CAN BE TURNED INTO A WORKING CHIP: a. To verify specified Design Rules have been obeyed (DESIGN RULE CHECK or DRC) b. To verify masks produce correct interconnected set of circuit elements (MASK CIRCUIT-EXTRACTION)

29 TYPICAL DESIGN FLOW FOR THE PRODUCTION OF AN IC MASK SET Functionality & performance specs Circuit topology or schematic Initial sizing of transistors Estimate parasitic capacitances Stick diagram layout Mask layout design Design Rule Check (DRC) Resize & Modify Improve Performance Circuit & parasitic extraction Circuit simulation OK Layout Complete