Workfunction Tuning for Single-Metal Dual-Gate With Mo and NiSi Electrodes

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1 tivation Workfunction Tuning for ngle-metal Dual-Gate With and i Electrodes poly- Gate Gate depletion effect -Effective oxide thickness increase Metal Gate o gate depletion effect K.Sano, M.Hino, and K.Shibahara Research Center for anodevices and System Hiroshima University Issue Dual Metal CMOSFET Complicated fabrication process Solution Dual-workfunction gates with single metal 3.. W Properties of Metal Materials Ta Required Properties High melting point (>000 o C) Low resistivity Suitability for the conventional processes i Hf Zr Ti Ir Resistivity [ cm] 3.. Al valence band Ir Melting Point [ o C] Hf conduction band Zr Ti Ta i W and i match the requirement Possibility of Workfunction Tuning? Workfunction Tuning Techniques Gate - + Implantation T.Amada et al., Mat.Res.Soc Q.Lu et al., Symp. on VLSI 200 K.Shibahara, 2003 COE Workshop -Solid phase diffusion from Ti Film R.J.P. Lander et al., Mat.Res.Soc M.Hino et al., SSDM 2003 i Gate -Impurity pileup by snowplow effect W.P.Maszara et al., IEDM 2002 J.Kedzierski et al., IEDM 2002 & 2003 Targets : Integration into MOSFET fabrication i : Optimization of silicidation condition for pileup formation

2 Solid-Phase Diffusion from Ti Film Workfunction shift Diode MOSFET Gate -0.6eV 0eV RTA : Solid-phase diffusion Temperature : 800 o C Time : min itrogen out-diffusion from gate? This Work itrogen Profile in MOS structure FET fabrication with modified process steps [K.Shibahara, 2003 COE Workshop] itrogen Profiles in MOS structure (back-side SIMS) dified Gate MOSFET Fabrication Process TIM//O2/ RTA : Solid Phase Diffusion Ti Removal Gate Formation itrogen Concentration [cm -3 ] Diode Process FET Process o RTA RTA for S/D Activation itrogen reduction by S/D activation at /O2 interface in bulk itrogen out-diffusion by S/D Activation Countermeasure Deposition O 2 before S/D Activation Ti/ Diode Proc. FET Proc. O Depth[nm] P- (00) Isolation and Ti sputter Solid-phase diffusion 800 o C min Ti removal Gate, patterning and S/D formation Interlayer O 2 CVD RTA : 900 o C min O2 CVD@previous Al wiring Al S/D Cover to prevent nitrogen out diffusion

3 MOSFET I D -V G Characteristics Workfunction adjustment methods for CMOSFET I D [A] Vth : 0.V 0 - Vth : 0.6V Ti/ Expected Vd : 0.0 V Lg : m W : 0 m Tox :.7nm V G [V] Speculation Pileup formation at upper /O 2 interface Decrease in nitrogen concentration at lower interface Fabricated MOSFET V th : -0.V (< Diode V FB : -0.6V) Improved,but still smaller V th O2 n+ O2 n+ O2 n+ O2 n+ Selective Out Diffusion itrogen pileup formation Cover deposition and patterning Annealing for out diffusion Selective Diffusion Deposition and pattering of nitrogen diffusion source Annealing for diffusion, pileup formation and S/D activation itrogen out diffusion Pileup free cover film tub n-mos p-mos Solid Phase Diffusion Source tub n-mos p-mos Comparison of silicide materials Ti 2 Original salicide material Replaced by Co 2 because of severe narrow line effect i Gate Co 2 Currently most popular for salicided CMOS Superior thermal stability than i i Small consumption Lower contact resistance Poor thermal stability Suitable for sub-90nm CMOS with low temperature BEOL and Candidate for workfunction tunable gate metal silicide O2 Source/Drain poly- -sub

4 Impurity pileup by snowplow effect in Full-i Gate i Gate MOS diodes Fabrication Process Introduction of impurities in poly- full-silicidation Pileup at i/o 2 i O 2 -sub impurity poly- P- (00) Gate oxidation poly- deposition Impurity implantation (Sb +, B +, P +, etc.) Workfunction shift Snowplow effect Drive away impurities in downward when full-silicidation i deposition i full-silicidation 00 o C 32min, 0 o C 2min 00 o C min Unreacted i removal Post metallization annealing i LOCOS i Gate MOS Diode C-V Characteristics undoped o C 0 o C o C 0. V FB : 0.3V Gate Volta ge [V] licidation temperature 00,0 o C 00 o C V FB 0.3V ~0V V FB increase by lower silicidation temperature Sb depth profiles in i MOS structure i O 2 -Sub Depth [nm] Closeup around the MOS interface Depth [nm] Lower silicidation temperature Lower silicidation rate Key parameter to snowplow effect Enhancement of snowplow effect by slowing down silicidation

5 Conclusions itrogen solid-phase diffusion into gate from Ti itrogen pileup and workfunction shift were reversible process. Additional thermal treatment gave rise to nitrogen redistribution. MOSFET fabrication : Procedure must be constructed to avoid the pileup deformation. Impurity pileup by snowplow effect in i gate Snowplow effect was enhanced by lower temperature at silicidation. Acknowledgements This work is partially supported by STARC(Semiconductor Technology Academic Research Center)

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