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1 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Manufacturing Process July 30,
2 CMOS Process 2
3 A Modern CMOS Process gate-oxide TiSi 2 AlCu Tungsten SiO 2 n+ p-well p-epi poly n-well p+ SiO 2 p+ Dual-Well Trench-Isolated CMOS Process 3
4 Circuit Under Design V DD V DD M2 M4 V in V out V out2 M1 M3 4
5 Its Layout View 5
6 The Manufacturing Process For a great tour through the IC manufacturing process and its different steps, check 6
7 Photo-Lithographic Process oxidation optical mask photoresist removal (ashing) photoresist coating stepper exposure process step Typical operations in a single photolithographic cycle (from [Fullman]). spin, rinse, dry acid etch photoresist development 7
8 Patterning of SiO2 Si-substrate (a) Silicon base material Si-substrate (b) After oxidation and deposition of negative photoresist Si-substrate (c) Stepper exposure Photoresist SiO 2 UV-light Patterned optical mask Exposed resist Si-substrate Si-substrate Si-substrate Hardened resist SiO 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 (e) After etching Chemical or plasma etch Hardened resist SiO 2 SiO 2 (f) Final result after removal of resist 8
9 CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers 9
10 CMOS Process Walk-Through p-epi p+ (a) Base material: p+ substrate with p-epilayer p-epi p+ SiN 3 4 SiO 2 (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer) p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask 10
11 CMOS Process Walk-Through SiO 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride n (e) After n-well and V Tp adjust implants p (f) After p-well and V Tn adjust implants 11
12 CMOS Process Walk-Through poly(silicon) (g) After polysilicon deposition and etch n+ p+ (h) After n+ source/drain and p+source/drain implants. These steps also dope the polysilicon. SiO 2 (i) After deposition of SiO 2 insulator and contact hole etch. 12
13 CMOS Process Walk-Through Al (j) After deposition and patterning of first Al layer. Al SiO 2 (k) After deposition of SiO 2 insulator, etching of via s, deposition and patterning of second layer of Al. 13
14 Advanced Metallization 14
15 Advanced Metallization 15
16 Design Rules 16
17 3D Perspective Polysilicon Aluminum 17
18 Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules) 18
19 CMOS Process Layers Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red Blue Magenta Black Black Black Representation 19
20 Layers in 0.25 mm m CMOS process 20
21 Intra-Layer Design Rules Same Potential Different Potential Well 10 0 or 6 9 Polysilicon 2 2 Active Select Contact or Via Hole 2 2 Metal1 Metal
22 Transistor Layout Transistor
23 Vias and Contacts 2 1 Via Metal to Active Contact 1 Metal to Poly Contact
24 Select Layer Select Substrate Well 24
25 CMOS Inverter Layout GND In V DD A A Out (a) Layout A A p-substrate n Field Oxide n + (b) Cross-Section along A-A p + 25
26 Layout Editor 26
27 Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um. 27
28 Sticks Diagram V DD 3 In 1 Out Dimensionless layout entities Only topology is important Final layout generated by compaction program GND Stick diagram of inverter 28
29 Packaging 29
30 Packaging Requirements Electrical: Low parasitics Mechanical: Reliable and robust Thermal: Efficient heat removal Economical: Cheap 30
31 Bonding Techniques Wire Bonding Substrate Die Pad Lead Frame 31
32 Tape-Automated Bonding (TAB) Sprocket hole Film + Pattern Solder Bump Test pads Lead frame Polymer film Die Substrate (b) Die attachment using solder bumps. (a) Polymer Tape with imprinted wiring pattern. 32
33 Flip-Chip Bonding Die Solder bumps Interconnect layers Substrate 33
34 Package-to to-board Interconnect (a) Through-Hole Mounting (b) Surface Mount 34
35 Package Types EE141 Integrated Digital Circuits 2nd 35 Manufacturing
36 Package Parameters 36
37 Multi-Chip Modules 37
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