MOS Gate Dielectrics. Outline

Transcription

1 MOS Gate Dielectrics Outline Scaling issues Technology Reliability of SiO 2 Nitrided SiO 2 High k dielectrics 42 Incorporation of N or F at the Si/SiO 2 Interface Incorporating nitrogen or fluorine instead of hydrogen strengthens the Si/SiO 2 interface and increases the gate dielectric lifetime because Si-F and Si-N bonds are stronger than Si-H bonds. Oxide Poly-Si Gate N or F Nitroxides Nitridation of SiO 2 by NH 3, N 2 O, NO Growth in N 2 O Improvement in reliability Barrier to dopant penetration from poly-si gate Marginal increase in K Used extensively Si substrate Fluorination Fluorination of SiO 2 by F ion implantation Improvement in reliability Increases B penetration from P + poly-si gate Reduces K Not used intentionally Can occur during processing (WF 6, BF 2 ) 43 1

2 Nitridation of SiO 2 in NH 3 H Oxidation in O 2 to grow SiO 2. RTP anneal in NH 3 maximize N at the interface and minimize bulk incorporation. Reoxidation in O 2 remove excess nitrogen from the outer surface Anneal in Ar remove excess hydrogen from the bulk Process too complex 44 Nitridation in N 2 O or NO Profile of N in SiO 2 Stress-time dependence of g m degradation of a NMOS SiO 2 Ref. Bhat et.al IEEE IEDM 1994 (Ref: Ahn, et.al., IEEE Electron Dev. Lett. Feb. 1992) The problem of H can be circumvented by replacing NH 3 by N 2 O or NO 45 2

3 Oxidation of Si in N 2 O N 2 O N 2 + O N 2 O + O 2NO Ref: Okada, et.al., Appl. Phys. Lett. 63(2), 1993 RTP oxidation shows N accumulation near the Si/SiO 2 interface Furnace oxidation shows almost uniform N profile lower Q bd 46 Dopant Penetration From Poly-Si Gate Thick gate oxide P + Poly-Si Gate B Thin gate oxide B Thin nitrided gate oxide B B in SiO 2 Si Si Si SiO X N Y Incorporation of nitrogen at the interface suppresses dopant diffusion from gate poly-si into the channel which can can cause V T shift. The problem is more serious for P + poly-si as boron diffuses more readily in SiO 2. It is desirable to use P + gate for PMOS transistors, for scaled CMOS technology to minimize short channel effects 47 3

4 MOS Gate Dielectrics Outline Scaling issues Technology Reliability of SiO 2 Nitrided SiO 2 High k dielectrics 48 High-k MOS Gate Dielectrics I channel charge x source injection velocity (gate oxide cap x gate overdrive) v inj C ox (V GS - V T ) E source µ inj Historically C ox has been increased by decreasing gate oxide thickness. It can also be increased by using a higher K dielectric I D "C ox " K thickness 20 Å SiO 2 K 4 40 Å Si 3 N 4 K 8 Si Higher thickness -> reduced gate leakage J DT "e #t ox 49 4

5 Benefits of High-κ Gate Dielectrics κ = 4 source V DD Gate 15 Å SiO 2e - e - drain channel Si substrate High leakage V DD Low leakage J DT " e! t ox source e - V DD Gate 60 Å High-κ e - drain channel Si substrate κ = 16 V DD Higher-κ film thicker gate dielectric lower leakage and power dissipation with the same capacitance!" A ') $ high( ) C t % " ox = 0 high( ) =! t SiO2 tox & ) SiO2 # Historically C ox has been increased by decreasing gate oxide thickness. It can also be increased by using a higher K dielectric 50 Alternatives to SiO 2 : Silicon Nitride (Ref: Guo & Ma, IEEE Electron Dev. Lett. June. 1998) A factor of 2 increase in K Reduction in bandgap increased gate leakage 51 5

6 Thermal Nitridation of Si in NH 3 Nitridation of Silicon I d - V g of 1.5 µm Si 3 N 4 gate NMOS Drain Current (ma) 25 Å Si 3 N 4 Vg = 2V 1.5V 1V 0.5V Drain Voltage (V) (Ref: Moslehi & S, EEE Trans. Electron Dev. Feb. 1985) Si reacts with NH 3 to grow Si 3 N 4 Excellent gate dielectric properties Reaction needs very high temperatures Si reacts with atomic nitrogen Reaction temperature could be reduced using nitrogen plasma More research needed Several deposition methods under investigations, e.g., rapid thermal CVD, jet vapor deposition (JVD) 52 Nitride / Nitroxide Sandwich Gate MOS 1.2 nm EOT Gate dielectric I d I g Ref: Q. Xiang, et.al., (AMD), IEDM nm EOT Ref: M. Bohr, (Intel), IEDM nm EOT (Equivalent oxide thickness) gate dielectric can be formed by - thermally growing ultrathin oxinitride - CVD of Si 3 N 4 Low gate leakage 40 nm channel length CMOS demonstrated 53 6

7 Requirements for the MOS gate dielectrics High dielectric constant higher charge induced in the channel Wide band gap higher barriers lower leakage Ability to grow high purity films on Si with a clean interface. High resistivity and breakdown voltage. Low bulk and interfacial trap densities. Compatibility with the substrate and top electrode. minimal interdiffusion and reaction minimal silicon reoxidation during growth and device processing - even a thin SiO 2 layer would deteriorate the C gate significantly. Thermal stresses most oxides have larger thermal expansion coefficients than Si. Good Si fabrication processing compatibility. Stability at higher processing temperatures and environments Ability to be cleaned, etched, etc. 54 Candidates for High K Gate Dielectrics Dielectric Permittivity Band Gap!E C to Si (ev) SiO Si 3 N Al 2 O TiO Ta 2 O Y 2 O La 2 O HfO ZrO ZrSiO HfSiO Ref: Robertson, J., Appl. Surf. Sci. (2002) 190 (1-4), 2 Higher K materials have lower bandgap There are many performance, reliability and process integration issues yet to be solved More research is needed to make these materials manufacturable 55 7

8 Thermodynamic Stability of High-K Dielectric Oxides 75 Å K Å K Å Si 3 N 4 Unstable oxides (e.g. TiO 2, Ta 2 O 5, BST) React with Si to form SiO 2 and silicides upon thermal annealing Barrier (e.g. Si 3 N 4 ) is required to prevent such a reaction Dielectric stack: poly-si/nitride/unstable oxide/nitride/si substrate A monolayer of nitride on both sides of gate dielectric already contributes 5 Å to the physical oxide thickness Stable oxides (e.g. HfO 2, ZrO 2, Al 2 O 3 ) and their silicates (e.g. ZrSi x O y ) and aluminates (e.g. ZrAl x O y ) Do not react with Si upon thermal annealing (up to 1000 C) May not require a barrier layer between Si and the metal oxide simple structure: poly-si/stable oxide/si substrate 56 Stability of Metal Oxides with Si After Beyers,J. Appl. Phys. 56, 157, 1984 And Wang and Meyer J. Appl. Phys. 64, 4711,

9 Capacitance and Leakage for High-k Gate Dielectric Films Grown Using ALCVD 10 0 Silicon Germanium Gate Leakage (A/cm 2 ) ALCVD ZrO 2 SiO nm 4 nm /C ' ox (µm2 /ff) Gate Current@ V FB+1V (A/cm 2 ) Equivalent SiO 2 Thickness (nm) Perkins, S and McIntyre, Stanford Univ Chui, Kim, S and McIntyre, Stanford Univ Atomic Layer CVD of Hi-κ Dielectric Pump Rotary Pump Turbo Pump H 2 O MFC HfCl4 MFC MFC ZrCl4 MFC Carrier Gas (N2) Loadlock Main Chamber Throttle Valve Turbo Pump Scrubber Rotary Pump 59 McIntyre, S, Stanford 9

10 Atomic Layer Deposition ZrCl 4 /HfCl 4 (g) Substrate Reactant A (ZrCl 4 /HfCl 4 ) ON OFF 1/4 cycle : Injection of reactant A (ZrCl 4 /HfCl 4 ) Reactant B (H 2 O) 1 cycle Time (sec) 60 Atomic Layer Deposition * Zr " OH + ZrCl4 # Zr " O " ZrCl3 + HCl! Saturated adsorption Substrate Reactant A (ZrCl 4 /HfCl 4 ) ON OFF 2/4 cycle : Purging (N 2 ) Reactant B (H 2 O) 1 cycle Time (sec) 61 10

11 Atomic Layer Deposition HCl (g) H 2 O (g) Substrate Reactant A (ZrCl 4 /HfCl 4 ) ON OFF 3/4 cycle : Injection of reactant B (H 2 O) Reactant B (H 2 O) 1 cycle Time (sec) 62 Atomic Layer Deposition * * Zr " Cl + H O # Zr " OH + HCl! 2 ZrO 2 /HfO 2 (s) Substrate Reactant A (ZrCl 4 /HfCl 4 ) ON OFF 4/4 cycle : Purging (N 2 ) Reactant B (H 2 O) 1 cycle Time (sec) 63 11

12 Atomic Layer Deposition ZrCl 4 /HfCl 4 (g) Saturated adsorption Substrate Substrate HCl (g) H 2 O (g) ZrO 2 /HfO 2 (s) Substrate Substrate - Surface saturation controlled process - Layer-by-layer deposition process - Excellent film quality and step coverage 64 Microstructure of ALD HfO 2 and HfO 2 ZrO 2 =29Å ZrO 2 =43Å ZrO 2 =82Å As-deposited ALD- ZrO 2 is polycrystalline. ZrO 2 Chemical oxide Si HfO 2 =28Å HfO 2 =45Å HfO 2 =62Å HfO 2 Chemical oxide As-deposited ALD-HfO 2 is amorphous. It crystallizes upon high temperature annealing Si There is always a thin layer of chemical SiO 2 present at the interface There are charges and trap states at various interfaces and grain boundaries 65 12

13 HfO 2 GeO x N y Ge High-k Gate Dielectric Can Also be Applied to Other Semiconductors HR-XTEM 4 nm Effective Mobility (cm 2 /V-s) Si Universal Mobility Si hi-! pfet 25 µm Ge hi-! pfet 30 µm Ge hi-! pfet 100 µm Ge hi-! pfet Effective Field (MV/cm) Passivation of Ge with GeO x N y, ZrO 2 and HfO 2 1 st demo of Ge MOSFETs with hi-κ p-mosfet with 3 mobility vs. Hi-k Si Passivation of many other materials being experimented, e.g., carbon nanotubes, GaAs, etc. Chui, et. al., IEDM Issues With High k Dielectrics How good is the interface with Si? mobility Contamination of Si by metal atoms Compatibility with gate electrode metal gate Device reliability and lifetime Minimum EOT achievable Technology integration More research is needed to make these materials manufacturable and reliable 67 13

14 Reduced Mobility in High- K Gate Stacks µ Coulombic Phonon Surface Roughness 1 µ = eff µ C µ ph µ sr E eff Electron Hole S. Saito, et al., IEEE IEDM, Possible Sources for Reduced Mobility in High- K Gate Stacks S. Saito, et al., IEEE IEDM, Washington, DC, Dec., Extensive research is needed to understand these mechanisms and how to minimize their impact on device performance 69 14

15 Effect of Interface states on CV curves Small density of states Large density of slow states Severe distortion, hysteresis and frequency dependence in C-V can be observed if large number of slow states are present This causes degradation in device properties, such as, V t, mobility, etc. 70 Effect of Slow D it states on CV Curves Responding to DC (Ideal) C Up-sweep Responding to DC (Actual) Downsweep Effect of C it Decreasing frequency Responding to DC (Actual) Acceptor -ve V t shift Measurement is like a regular C-V setup with a DC sweep from +ve to ve followed by a DC sweep from ve to +ve. Hysteresis in C-V is due to the VERY slow states that do not empty out fast enough and cannot even respond to the slow DC sweep. 71 V 15

16 Effect of Interface States on Mobility in High- K Gate Stacks E eff = 0.1 MV/cm µ eff, for HfO 2 and SiO 2 gate MOSFETs, along with their three components, including the components limited by Coulomb scattering, µ coul, surface roughness scattering, µ sr, and the phonon scattering, µ ph. Effect of interface traps on mobility. Coulombic scattering reduces the mobility Ref: T. P. Ma, IEEE TED, Jan High-K/Poly-Si Gate Transistors High-K/poly-Si gate transistors suffer from high V T, degraded channel mobility and poor drive performance Phonon scattering limits channel mobility in high-k/poly-si gate MOSFETs R. Chau, Intel, ICSICT

17 Metal Gate Screens Surface Phonon Scattering and Improves Mobility in High-K Transistors R. Chau, Intel, ICSICT µ = 1 i " µi 74 Annealing Crystallization of ALD-HfO 2 In-situ anneal at 520 C using 30Å HfO 2 on 25Å thermal SiO 2. As-dep 10 min 20 min 50 min 60 min 70 min Upon annealing the amorphous films cryatsllize Grain boundaries cause statistical variation in the properties By adding other elements (e.g. N, Al, Si) to HfO 2 crystallization can be impeded 75 17

18 Crystallization and Phase Separation 20% SiO2 3.1 MX 55% (21-12) 55% SiO2 HfO2 SiO2 Si SiO2 5 nm SiO2 5 nm 65% SiO2 75 % (21-18) 75% SiO2 65% SiO2 (21-15) Non-uniformity of k-value leads to mobility degradation This can occure in the case of silicates. G.B. et al., MRS nm 5 nm B.Foran et al., ALD conference, Luigi Colombo, et al.,(t.i.) IWGI Nov 2003 Tokyo, Japan 77 18

19 Mobility: N Incorporation in HfSiO Hole Electron Luigi Colombo, et al.,(t.i.) IWGI Nov 2003 Tokyo, Japan 78 Summary Scaling issues Technology Reliability of SiO 2 Nitrided SiO 2 High k dielectrics 79 19