EECS130 Integrated Circuit Devices

Transcription

1 EECS130 Integrated Circuit Devices Professor Ali Javey 9/13/2007 Fabrication Technology Lecture 1

2 Silicon Device Fabrication Technology Over transistors (or 100,000 for every person in the world) are manufactured every year. Variations of this versatile technology are used for flat-panel displays, micro-electro-mechanical systems (MEMS), and even DNA chips for DNA screening...

3 Terminology SSI (Small Scale Integration) few transistors MSI (Medium Scale Integration) hundreds LSI (Large Scale Integration) - thousands VLSI (Very Large Scale Integration) - millions ULSI (Ultra Large Scale Integration)

4 Foundry (Fab) Foundry (also called a fab for fabrication plant) is used to refer to a factory where devices like integrated circuits are manufactured. The central part of a fab is a cleanroom. Note the difference between a fab and a lab.

5 Cleanroom Standards Federal Standard Class Limits CLASS MEASURED PARTICLE SIZE (MICROMETERS) NA NA 100 NA NA 1,000 NA NA NA 1, ,000 NA NA NA 10, ,000 NA NA NA 100, Why do we need cleanrooms?

6 Introduction to Device Fabrication Oxidation Lithography & Etching Ion Implantation Annealing & Diffusion Thin Film Deposition

7 Dry Oxidation : Wet Oxidation : Oxidation of Silicon Si + O 2 SiO 2 Si +2H 2 O SiO 2 + 2H 2 Thin oxide Thick oxide

8 Oxidation of Silicon Quartz tube Si Wafers Flow controller O 2 N 2 H 2 O or TCE(trichloroethylene) Resistance-heated furnace

9 EXAMPLE : Sequential Oxidation (a) How long does it take to grow 0.1μm of dry oxide at 1000 o C? (b) After step (a), how long will it take to grow an additional 0.2μm of oxide at 900 o C in a wet ambient? Solution: Oxidation of Silicon (a) From the 1000 o C dry curve in Slide 3-3, it takes 2.5 hr to grow 0.1μm of oxide. (b) Use the 900 o C wet curve only. It would have taken 0.7hr to grow the 0.1 μm oxide and 2.4hr to grow 0.3 μm oxide from bare silicon. The answer is 2.4hr 0.7hr = 1.7hr.

10 Lithography Resist Coating Photoresist Positive resist Development Negative resist Optical Lens system Si Oxide (a) Deep Ultraviolet Light Photomask with opaque and clear patterns Si (c) Si Exposure (b) Si (d) Si Etching and Resist Strip

11 Lithography Photolithography Resolution Limit, R R kλ due to optical diffraction Wavelength λ needs to be minimized. (248 nm, 193 nm, 157 nm?) k ( 0.5) can be reduced by Large aperture, high quality lens Small field, step-and-repeat using stepper Phase-shift mask Optical proximity correction Lithography is difficult and expensive. There are ~20 lithography steps in an IC process.

12 Other Advanced Lithography Methods EUV Photolithography E-beam Lithography Dip-pen lithography

13 Dip-pen Lithography, Chad Mirkin, NWU

14 Richard Feynman

15 Pattern Transfer Etching wet etch Isotropic etching dry etch Anisotropic etching photoresist photoresist SiO 2 SiO 2 (1) photoresist (1) photoresist SiO 2 SiO 2 (2) (2) SiO 2 SiO 2 (3) (3)

16 Pattern Transfer Etching Dry Etching (also known as Plasma Etching, or Reactive-Ion Etching) is anisotropic. Silicon and its compounds can be etched by plasmas containing F. Aluminum can be etched by Cl. Some concerns : - Selectivity and End-Point Detection - Plasma Process-Induced Damage or Wafer Charging Damage and Antenna Effect

17 Scanning electron microscope view of a plasma-etched (dry-etched) 0.16 μm pattern in polycrystalline silicon film.

18 Doping Ion Implantation Ions Si Masking material for example resist or SiO 2 The dominant doping method Excellent control of dose (cm -2 ) Good control of implant depth with energy (KeV to MeV) Repairing crystal damage and dopant activation requires annealing, which can cause dopant diffusion and loss of depth control.

19 Ion implantation Phosphorous Density Profile after Implantation

20 Doping Other Doping Methods Gas-Phase Doping : Used to dope Si with P using POCl 3. Solid-Source Doping : Dopant diffuses from a doped solid film (SiGe or oxide) into Si. In-Situ Doping : Used to dope deposited films during film deposition.

21 Dopant Diffusion Junction depth, x j SiO 2 N( x, t) N = π n-type diffusion layer o Dt e x 2 / 4Dt p-type Si N : N d or N a (cm -3 ) N o : dopant atoms per cm 2 t : diffusion time D : diffusivity, Dt is the approximate distance of dopant diffusion

22 Dopant Diffusion D increases with increasing temperature. Some applications need very deep junctions (high T, long t). Others need very shallow junctions (low T, short t).

23 Dopant Diffusion Shallow Junction and Rapid Thermal Annealing After ion implantation, thermal annealing is required. Furnace annealing causes too much diffusion of dopant for some applications. In rapid thermal annealing (RTA), the wafer is heated to high temperature in seconds by a bank of heat lamps. Also RTO (oxidation), RTCVD (chemical vapor deposition), RTP (processing).

24 Crystalline Thin-Film Deposition Three Kinds of Solid Polycrystalline Amorphous Silicon wafer Thin film of Si or metal. Thin film of SiO 2 or Si 3 N 4.

25 Thin-Film Deposition Metal layers for device interconnect Inter-metal dielectric Poly-Si for transistor gate Barrier against interdiffusion Encapsulation

26 Sputtering Schematic Illustration of Sputtering Process Sputtering target Ion (Ar + ) Atoms sputtered out of the target Target material deposited on wafer Si Wafer

27 Chemical Vapor Deposition (CVD) Chemical reaction Molecules of deposited layer Gas 1 Gas 2 Si Wafer Thin film is formed from gas phase components.

28 Chemical Vapor Deposition (CVD) Pressure sensor Resistance-heated furnace Quartz tube Si Wafers Trap To exhaust Pump Gas control system Source gases LPCVD Systems

29 Interconnection The Back-end Process Al-Cu SiO 2 Si Dopant diffusion region (a) Encapsulation Dielectric Dielectric Dielectric Metal 3 Metal 2 Metal 1 via or plug Si CoSi 2 diffusion region (b)

30 Interconnection The Back-end Process Multi-Level Metallization Sun Microsystems Ultra Sparc Microprocessor

31 Interconnection The Back-end Process Copper Interconnect Al interconnect develops voids from electromigration. Cu has excellent electromigration reliability and 40% lower resistance than Al.

32 Start (0) (1) Oxidation (2) Lithography (3) Chapter Summary A Device Fabrication Example P-Si SiO 2 P-Si SiO2 UV Mask Positive resist SiO 2 P-Si SiO 2 SiO 2 P-Si Oxide Etching (4) (5) (6) (7) Arsenic implantation SiO 2 SiO 2 SiO 2 SiO 2 N + P Al SiO 2 SiO 2 N + P P-Si Res is t Al Al SiO 2 SiO 2 N + P UV Mask Lithography Annealing & Diffusion Al Sputtering

33 Chapter Summary A Device Fabrication Example Metal etching (8) (9) CVD nitride deposition (10) Lithography and bonding window etching (11) Back Side milling SiO2 SiO2 Si 3 N 4 N + P SiO 2 SiO 2 Si 3 N 4 N + P SiO 2 SiO 2 N + P Photoresist Si 3 N 4 SiO 2 SiO 2 N + P Al Al Al Al (12) (13) SiO 2 SiO 2 Si 3 N 4 N + P SiO 2 SiO 2 Au Si 3 N 4 Au N + P Al Plastic package metal leads Al Dicing, wire bonding, and packaging Au deposition on the back side wire