Lecture 200 BiCMOS Technology (12/12/01) Page 200-1
|
|
|
- Pierce Sanders
- 6 years ago
- Views:
Transcription
1 Lecture 200 BiCMOS Technology (12/12/01) Page LECTURE 200 BICMOS TECHNOLOGY (READING: Text-Sec. 2.11) INTRODUCTION Objective Illustrate BiCMOS technology Outline Introduction Physical process illustration Summary Lecture 200 BiCMOS Technology (12/12/01) Page Typical BiCMOS Technology The following pages describe a 0. BiCMOS process. Masking Sequence: 1. Buried n+ 13. PMOS lightly doped drain 2. Buried p+ 14. n+ source/drain 3. Collector tub 15. p+ source/drain 4. Active area 16. Silicide protection 5. Collector sinker 17. Contacts Metal Via 1 8. Emitter window 20. Metal 2 9. Base oxide/implant 21. Via Emitter implant 22. Metal Poly Nitride passivation 12. NMOS lightly doped drain Notation: BSPG = Boron and Phosphorus doped Silicate Glass (oxide) Kooi Nitride = A thin of silicon nitride on the silicon surface as a result of the reaction of silicon with the HN3 generated, during the field oxidation. TEOS = Tetro-Ethyl-Ortho-Silicate. A chemical compound used to deposit conformal oxide films.
2 Lecture 200 BiCMOS Technology (12/12/01) Page n + and p + Buried Layers Starting Substrate: BiCMOS-01 n + and p + Buried Layers: BiCMOS-02 Lecture 200 BiCMOS Technology (12/12/01) Page Growth n+ buried p+ buried BiCMOS-03 Comment: As the epi grows vertically, it assumes the doping level of the substrate beneath it. In addition, the high temperature of the epitaxial process causes the buried s to diffuse upward and downward.
3 Lecture 200 BiCMOS Technology (12/12/01) Page Original Area of CollectorTub Implant BiCMOS-04 Comment: The collector area is developed by an initial implant followed by a drive-in diffusion to form the collector tub. Lecture 200 BiCMOS Technology (12/12/01) Page Active Area Definition Nitride α- BiCMOS-05 Comment: The silicon nitride is use to impede the growth of the thick oxide which allows contact to the substrate α-silicon is used for stress relief and to minimize the bird s beak encroachment
4 Lecture 200 BiCMOS Technology (12/12/01) Page BiCMOS-06 The field oxide is used to isolate surface structures (i.e. metal) from the substrate Lecture 200 BiCMOS Technology (12/12/01) Page Collector Sink and n-well and p-well Definitions Collector Sink Anti-Punch Through Threshold Adjust Anti-Punch Through Threshold Adjust BiCMOS-07
5 Lecture 200 BiCMOS Technology (12/12/01) Page Base Definition BiCMOS-08 Lecture 200 BiCMOS Technology (12/12/01) Page Definition of the Emitter Window and Sub-Collector Implant Sacrifical Oxide Sub-Collector BiCMOS-09
6 Lecture 200 BiCMOS Technology (12/12/01) Page Emitter Implant Emitter Implant Sub-Collector BiCMOS-10 The polysilicon above the base is implanted with n-type carriers Lecture 200 BiCMOS Technology (12/12/01) Page Emitter Diffusion Emitter BiCMOS-11 The polysilicon not over the emitter window is removed and the n-type carriers diffuse into the base forming the emitter
7 Lecture 200 BiCMOS Technology (12/12/01) Page Formation of the MOS Gates and LD Drains/Sources BiCMOS-12 The surface of the region where the MOSFETs are to be built is cleared and a thin gate oxide is deposited with a polysilicon on top of the thin oxide The polysilicon is removed over the source and drain areas A light source/drain diffusion is done for the NMOS and PMOS (separately) Lecture 200 BiCMOS Technology (12/12/01) Page Heavily Doped Source/Drain BiCMOS-13 The sidewall spacers prevent the heavy source/drain doping from being near the channel of the MOSFET
8 Lecture 200 BiCMOS Technology (12/12/01) Page Siliciding Silicide TiSi 2 Silicide TiSi 2 Silicide TiSi2 BiCMOS-14 Siliciding is used to reduce the resistance of the polysilicon and to provide ohmic contacts to the base, emitter, collector, sources and drains Lecture 200 BiCMOS Technology (12/12/01) Page Contacts Tungsten Plugs Tungsten Plugs Tungsten Plugs BiCMOS-15 A dielectric is deposited over the entire wafer One of the purposes of the dielectric is to smooth out the surface Tungsten plugs are used to make electrical contact between the transistors and metal1
9 Lecture 200 BiCMOS Technology (12/12/01) Page Metal1 Metal1 Metal1 Metal1 BiCMOS-16 Lecture 200 BiCMOS Technology (12/12/01) Page Metal1-Metal2 Vias Tungsten Plugs Oxide/ SOG/ Oxide BiCMOS-17
10 Lecture 200 BiCMOS Technology (12/12/01) Page Metal2 Metal 2 Oxide/ SOG/ Oxide BiCMOS-18 Lecture 200 BiCMOS Technology (12/12/01) Page Metal2-Metal3 Vias TEOS/ BPSG/ SOG Oxide/ SOG/ Oxide BiCMOS-19 The metal2-metal3 vias will be filled with metal3 as opposed to tungsten plugs
11 Lecture 200 BiCMOS Technology (12/12/01) Page Completed Wafer Nitride (Hermetically seals the wafer) Oxide/SOG/Oxide Metal3 Metal3 Vias TEOS/ BPSG/ SOG Oxide/ SOG/ Oxide BiCMOS-20 Lecture 200 BiCMOS Technology (12/12/01) Page SUMMARY This section has illustrated the major process steps for a 0.5micron BiCMOS technology. The performance of the active devices are: npn bipolar junction transistor: f T = 12GHz, β F = BV CEO = 7V n-channel FET: K = 127µA/V2 V T = 0.64V λ N p-channel FET: K = 34µA/V2 V T = -0.63V λ P Although today s state of the art is 0.2 or 0.18µm BiCMOS, the processing steps illustrated above approximate that which is done in a smaller geometry.
Lecture 030 Integrated Circuit Technology - I (5/8/03) Page 030-1
Lecture 030 Integrated Circuit Technology - I (5/8/03) Page 030-1 LECTURE 030 INTEGRATED CIRCUIT TECHNOLOGY - I (References [7,8]) Objective The objective of this presentation is: 1.) Illustrate integrated
EE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects
EE 330 Lecture 9 IC Fabrication Technology Part II -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects Review from Last Time Etching Dry etch (anisotropic) SiO
VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras
VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras Lecture - 33 Problems in LOCOS + Trench Isolation and Selective Epitaxy So, we are discussing
National Semiconductor LM2672 Simple Switcher Voltage Regulator
Construction Analysis National Semiconductor LM2672 Simple Switcher Voltage Regulator Report Number: SCA 9712-570 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale,
EE 434 Lecture 9. IC Fabrication Technology
EE 434 Lecture 9 IC Fabrication Technology Quiz 7 The layout of a film resistor with electrodes A and B is shown. If the sheet resistance of the film is 40 /, determine the resistance between nodes A and
FABRICATION of MOSFETs
FABRICATION of MOSFETs CMOS fabrication sequence -p-type silicon substrate wafer -creation of n-well regions for pmos transistors, -impurity implantation into the substrate. -thick oxide is grown in the
HOMEWORK 4 and 5. March 15, Homework is due on Monday March 30, 2009 in Class. Answer the following questions from the Course Textbook:
HOMEWORK 4 and 5 March 15, 2009 Homework is due on Monday March 30, 2009 in Class. Chapter 7 Answer the following questions from the Course Textbook: 7.2, 7.3, 7.4, 7.5, 7.6*, 7.7, 7.9*, 7.10*, 7.16, 7.17*,
Process Integration. NMOS Generic NMOS Process Flow. CMOS - The MOSIS Process Flow
Process Integration Self-aligned Techniques LOCOS- self-aligned channel stop Self-aligned Source/Drain Lightly Doped Drain (LDD) Self-aligned silicide (SALICIDE) Self-aligned oxide gap MEMS Release Techniques
Isolation Technology. Dr. Lynn Fuller
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Isolation Technology Dr. Lynn Fuller Motorola Professor 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Fax (585) 475-5041
EE 560 FABRICATION OF MOS CIRCUITS. Kenneth R. Laker, University of Pennsylvania
1 EE 560 FABRICATION OF MOS CIRCUITS 2 CMOS CHIP MANUFACTRING STEPS Substrate Wafer Wafer Fabrication (diffusion, oxidation, photomasking, ion implantation, thin film deposition, etc.) Finished Wafer Wafer
Motorola PC603R Microprocessor
Construction Analysis Motorola PC603R Microprocessor Report Number: SCA 9709-551 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax:
VLSI Systems and Computer Architecture Lab
ΚΥΚΛΩΜΑΤΑ VLSI Πανεπιστήμιο Ιωαννίνων CMOS Technology Τμήμα Μηχανικών Η/Υ και Πληροφορικής 1 From the book: An Introduction ti to VLSI Process By: W. Maly ΚΥΚΛΩΜΑΤΑ VLSI Διάρθρωση 1. N well CMOS 2. Active
VLSI INTRODUCTION P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
VLSI INTRODUCTION P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents UNIT I INTRODUCTION: Introduction to IC Technology MOS, PMOS, NMOS, CMOS & BiCMOS technologies. BASIC ELECTRICAL PROPERTIES : Basic Electrical
CHAPTER 2 - CMOS TECHNOLOGY
CMOS Analog Circuit Design Page 2.0-1 CHAPTER 2 - CMOS TECHNOLOGY Chapter Outline 2.1 Basic MOS Semiconductor Fabrication Processes 2.2 CMOS Technology 2.3 PN Junction 2.4 MOS Transistor 2.5 Passive Components
Lattice isplsi1032e CPLD
Construction Analysis Lattice isplsi1032e CPLD Report Number: SCA 9612-522 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780 Fax: 602-948-1925
Intel Pentium Processor W/MMX
Construction Analysis Intel Pentium Processor W/MMX Report Number: SCA 9706-540 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780 Fax:
Semiconductor Manufacturing Technology. IC Fabrication Process Overview
Semiconductor Manufacturing Technology Michael Quirk & Julian Serda October 00 by Prentice Hall Chapter 9 IC Fabrication Process Overview /4 Objectives After studying the material in this chapter, you
Figure 2.3 (cont., p. 60) (e) Block diagram of Pentium 4 processor with 42 million transistors (2000). [Courtesy Intel Corporation.
Figure 2.1 (p. 58) Basic fabrication steps in the silicon planar process: (a) oxide formation, (b) selective oxide removal, (c) deposition of dopant atoms on wafer, (d) diffusion of dopant atoms into exposed
CMOS Manufacturing Process
CMOS Manufacturing Process CMOS Process A Modern CMOS Process gate-oxide TiSi 2 AlCu Tungsten SiO 2 n+ p-well p-epi poly n-well p+ SiO 2 p+ Dual-Well Trench-Isolated CMOS Process Circuit Under Design V
Dallas Semicoductor DS80C320 Microcontroller
Construction Analysis Dallas Semicoductor DS80C320 Microcontroller Report Number: SCA 9702-525 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone:
Silicon Wafer Processing PAKAGING AND TEST
Silicon Wafer Processing PAKAGING AND TEST Parametrical test using test structures regularly distributed in the wafer Wafer die test marking defective dies dies separation die fixing (not marked as defective)
SGS-Thomson M17C1001 1Mb UVEPROM
Construction Analysis SGS-Thomson M17C1001 1Mb UVEPROM Report Number: SCA 9612-518 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780
CMOS FABRICATION. n WELL PROCESS
CMOS FABRICATION n WELL PROCESS Step 1: Si Substrate Start with p- type substrate p substrate Step 2: Oxidation Exposing to high-purity oxygen and hydrogen at approx. 1000 o C in oxidation furnace SiO
Rockwell R RF to IF Down Converter
Construction Analysis Rockwell R6732-13 RF to IF Down Converter Report Number: SCA 9709-552 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780
3.155J / 6.152J Micro/Nano Processing Technology TAKE-HOME QUIZ FALL TERM 2005
3.155J / 6.152J Micro/Nano Processing Technology TAKE-HOME QUIZ FALL TERM 2005 1) This is an open book, take-home quiz. You are not to consult with other class members or anyone else. You may discuss the
EE 330 Fall Ruden Michael. Al Kaabi Humaid. Archer Tyler. Hafeez Mustafa. Mullen Taylor. Thedens Peter. Cao Khoi.
1 2 5 6 3 4 8 7 1 2 3 4 5 6 ROW EE 330 Fall 2017 9 10 Al Kaabi Humaid Alegria Francisco Allison Trenton Alva Caroline Archer Tyler Bahashwan Abdullah Betke Jarrett Chun Junho Davidson Caleb Faronbi Matthew
Fabrication and Layout
Fabrication and Layout Kenneth Yun UC San Diego Adapted from EE271 notes, Stanford University Overview Semiconductor properties How chips are made Design rules for layout Reading Fabrication: W&E 3.1,
Lecture 22: Integrated circuit fabrication
Lecture 22: Integrated circuit fabrication Contents 1 Introduction 1 2 Layering 4 3 Patterning 7 4 Doping 8 4.1 Thermal diffusion......................... 10 4.2 Ion implantation.........................
1 Thin-film applications to microelectronic technology
1 Thin-film applications to microelectronic technology 1.1 Introduction Layered thin-film structures are used in microelectronic, opto-electronic, flat panel display, and electronic packaging technologies.
Historical Development. Babbage s second computer. Before the digital age
Historical Development To fully appreciate the computers of today, it is helpful to understand how things got the way they are The evolution of computing machinery has taken place over several centuries
Hitachi A 64Mbit (8Mb x 8) Dynamic RAM
Construction Analysis Hitachi 5165805A 64Mbit (8Mb x 8) Dynamic RAM Report Number: SCA 9712-565 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone:
ELEC 3908, Physical Electronics, Lecture 4. Basic Integrated Circuit Processing
ELEC 3908, Physical Electronics, Lecture 4 Basic Integrated Circuit Processing Lecture Outline Details of the physical structure of devices will be very important in developing models for electrical behavior
FABRICATION ENGINEERING MICRO- NANOSCALE ATTHE AND. Fourth Edition STEPHEN A. CAMPBELL. of Minnesota. University OXFORD UNIVERSITY PRESS
AND FABRICATION ENGINEERING ATTHE MICRO- NANOSCALE Fourth Edition STEPHEN A. CAMPBELL University of Minnesota New York Oxford OXFORD UNIVERSITY PRESS CONTENTS Preface xiii prrt i OVERVIEW AND MATERIALS
Layout-related stress effects on TID-induced leakage current
Layout-related stress effects on TID-induced leakage current Nadia Rezzak, R. D. Schrimpf, M. L. Alles, En Xia Zhang, Daniel M. Fleetwood, Yanfeng Albert Li Radiation Effects Group Vanderbilt University,
Modeling of Local Oxidation Processes
Introduction Isolation Processes in the VLSI Technology Main Aspects of LOCOS simulation Athena Oxidation Models Several Examples of LOCOS structures Calibration of LOCOS effects using VWF Field Oxide
Manufacturing Process
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Manufacturing Process July 30, 2002 1 CMOS Process 2 A Modern CMOS Process gate-oxide TiSi 2 AlCu Tungsten
Cost of Integrated Circuits
Cost of IC Design 1 Cost of Integrated Circuits NRE (Non-Recurrent Engineering) costs fixed design time and effort, mask generation independent of sales volume / number of products one-time cost factor
Fabrication and Layout
ECEN454 Digital Integrated Circuit Design Fabrication and Layout ECEN 454 3.1 A Glimpse at MOS Device Polysilicon Aluminum ECEN 475 4.2 1 Material Classification Insulators Glass, diamond, silicon oxide
EE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009
Suggested Reading EE40 Lec 22 IC Fabrication Technology Prof. Nathan Cheung 11/19/2009 300mm Fab Tour http://www-03.ibm.com/technology/manufacturing/technology_tour_300mm_foundry.html Overview of IC Technology
Is Now Part of To learn more about ON Semiconductor, please visit our website at
Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC
(12) Patent Application Publication (10) Pub. No.: US 2006/ A1
(19) United States US 20060228850A1 (12) Patent Application Publication (10) Pub. No.: US 2006/0228850 A1 Tsai et al. (43) Pub. Date: Oct. 12, 2006 (54) PATTERN LOADING EFFECT REDUCTION FOR SELECTIVE EPTAXAL
Lecture 19 Microfabrication 4/1/03 Prof. Andy Neureuther
EECS 40 Spring 2003 Lecture 19 Microfabrication 4/1/03 Prof. ndy Neureuther How are Integrated Circuits made? Silicon wafers Oxide formation by growth or deposition Other films Pattern transfer by lithography
Technology. Semiconductor Manufacturing. Hong Xiao INTRODUCTION TO SECOND EDITION SPIE PRESS
INTRODUCTION TO Semiconductor Manufacturing Technology SECOND EDITION Hong Xiao TECHNISCHE INFORMATIONSBiBUOTHEK UNIVERSITATSBIBLIOTHEK HANNOVER SPIE PRESS Bellingham,Washington USA Contents Preface to
Lecture 2. Fabrication and Layout
Lecture 2 Fabrication and Layout Mark Horowitz Modified by Azita Emami Computer Systems Laboratory Stanford University azita@stanford.edu 1 Overview Reading W&E 3.1(scan), 3.2.1, 3.3.1 - Fabrication W&E
Lezioni di Tecnologie e Materiali per l Elettronica
Lezioni di Tecnologie e Materiali er l Elettronica Danilo Manstretta danilo.manstretta@univ.it microlab.univ.it Outline Passive comonents Resistors Caacitors Inductors Printed circuits technologies Materials
Semiconductor Technology
Semiconductor Technology von A bis Z Metallization www.halbleiter.org Contents Contents List of Figures List of Tables II III 1 Metallization 1 1.1 Requirements on metallization........................
Ion Implantation Most modern devices doped using ion implanters Ionize gas sources (single +, 2+ or 3+ ionization) Accelerate dopant ions to very
Ion Implantation Most modern devices doped using ion implanters Ionize gas sources (single +, 2+ or 3+ ionization) Accelerate dopant ions to very high voltages (10-600 KeV) Use analyzer to selection charge/mass
VLSI Technology. By: Ajay Kumar Gautam
By: Ajay Kumar Gautam Introduction to VLSI Technology, Crystal Growth, Oxidation, Epitaxial Process, Diffusion Process, Ion Implantation, Lithography, Etching, Metallization, VLSI Process Integration,
EEC 118 Lecture #5: MOS Fabrication. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #5: MOS Fabrication Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 3 this week, report due next week HW 3 due this Friday at 4
Ajay Kumar Gautam [VLSI TECHNOLOGY] VLSI Technology for 3RD Year ECE/EEE Uttarakhand Technical University
![Ajay Kumar Gautam [VLSI TECHNOLOGY] VLSI Technology for 3RD Year ECE/EEE Uttarakhand Technical University](/thumbs/75/72824557.jpg "Ajay Kumar Gautam [VLSI TECHNOLOGY] VLSI Technology for 3RD Year ECE/EEE Uttarakhand Technical University")
2014 Ajay Kumar Gautam [VLSI TECHNOLOGY] VLSI Technology for 3RD Year ECE/EEE Uttarakhand Technical University Page1 Syllabus UNIT 1 Introduction to VLSI Technology: Classification of ICs, Scale of integration,
Ion Implantation Most modern devices doped using ion implanters Implant dopants by accelerating individual atoms (ions) Ionize gas sources (single +,
Ion Implantation Most modern devices doped using ion implanters Implant dopants by accelerating individual atoms (ions) Ionize gas sources (single +, 2+ or 3+ ionization) Use analyzer to selection charge/mass
Interconnects OUTLINE
Interconnects 1 Interconnects OUTLINE 1. Overview of Metallization 2. Introduction to Deposition Methods 3. Interconnect Technology 4. Contact Technology 5. Refractory Metals and their Silicides Reading:
Radiation Tolerant Isolation Technology
Radiation Tolerant Isolation Technology Background The following contains a brief description of isolation technologies used for radiation hardened integrated circuits. The technologies mentioned are junction
Semiconductor Technology
Semiconductor Technology from A to Z Oxidation www.halbleiter.org Contents Contents List of Figures List of Tables II III 1 Oxidation 1 1.1 Overview..................................... 1 1.1.1 Application...............................
Design and Optimization of 22nm NMOS Transistor
Australian Journal of Basic and Applied Sciences, 6(7): 1-8, 01 ISSN 1991-8178 Design and Optimization of nm NMOS Transistor 1 Afifah Maheran A.H., 1 Menon, P.S., I. Ahmad, 1 S. Shaari, 1 H.A. Elgomati,
Lecture 7 CMOS MEMS. CMOS MEMS Processes. CMOS MEMS Processes. Why CMOS-MEMS? Agenda: CMOS MEMS: Fabrication. MEMS structures can be made
EEL6935 Advanced MEMS (Spring 2005) Instructor: Dr. Huikai Xie CMOS MEMS Agenda: Lecture 7 CMOS MEMS: Fabrication Pre-CMOS Intra-CMOS Post-CMOS Deposition Etching Why CMOS-MEMS? Smart on-chip CMOS circuitry
Semiconductor Physics Course Final Presentation CMOS Fabrication by Özgür Çobanoğlu (Turin, 2006)
Semiconductor Physics Course Final Presentation CMOS Fabrication by Özgür Çobanoğlu (Turin, 2006) 1 Outline Sections and Contents of the Presentation What is MOS? How does MOS behave in low level? A useful
Chapter 2. Density 2.65 g/cm 3 Melting point Young s modulus Tensile strength Thermal conductivity Dielectric constant 3.
Chapter 2 Thin Film Materials Thin films of Silicon dioxide, Silicon nitride and Polysilicon have been utilized in the fabrication of absolute micro pressure sensor. These materials are studied and discussed
Solutions Manual to Accompany
Solutions Manual to Accompany FUNDAMETALS OF SEMICONDUCTOR FABRICATION G. S. May Motorola Foundation Professor School of Electrical & Computer Engineering Georgia Institute of Technology Atlanta, GA, USA
Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 6: New Materials, Processes, and Equipment
Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 6: New Materials, Processes, and Equipment Editors: E. P. Gusev Qualcomm MEMS Technologies San Jose, California, USA D-L. Kwong
Semiconductor Manufacturing Technology. Semiconductor Manufacturing Technology
Semiconductor Manufacturing Technology Michael Quirk & Julian Serda October 2001 by Prentice Hall Chapter 11 Deposition Film Layers for an MSI Era NMOS Transistor Topside Nitride Pre-metal oxide Sidewall
Development of a Deep-Submicron CMOS Process for Fabrication of High Performance 0.25 mm Transistors
Development of a Deep-Submicron CMOS Process for Fabrication of High Performance 0.25 mm Transistors Michael Aquilino M.S. Thesis Defense Department May 19, 2006 Motivation o Enable the department to continue
EECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 9/13/2007 Fabrication Technology Lecture 1 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world)
SEMATECH Symposium Korea 2012 Practical Analysis Techniques of Nanostructured Semiconductors by Electron Microscopy
SEMATECH Symposium Korea 2012 Practical Analysis Techniques of Nanostructured Semiconductors by Electron Microscopy Jun-Mo Yang, Ph.D. Measurement & Analysis Team National NanoFab Center, Korea Introduction
CMOS VLSI Design M.Tech. First semester VTU Anil V. Nandi, ECE department, BVBCET, Hubli
CMOS VLSI Design M.Tech. First semester VTU Anil V. Nandi, ECE department, BVBCET, Hubli-580031. Contents: Semiconductor Technology overview Silicon Growth/Processing,Oxidation, Diffusion, Epitaxy, deposition,
Chapter 3 Silicon Device Fabrication Technology
Chapter 3 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world) are manufactured every year. VLSI (Very Large Scale Integration) ULSI (Ultra Large Scale
Process Flow in Cross Sections
Process Flow in Cross Sections Process (simplified) 0. Clean wafer in nasty acids (HF, HNO 3, H 2 SO 4,...) --> wear gloves! 1. Grow 500 nm of SiO 2 (by putting the wafer in a furnace with O 2 2. Coat
Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering
Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering Jack Kavalieros, Brian Doyle, Suman Datta, Gilbert Dewey, Mark Doczy, Ben Jin, Dan Lionberger, Matthew
R Sensor resistance (Ω) ρ Specific resistivity of bulk Silicon (Ω cm) d Diameter of measuring point (cm)
4 Silicon Temperature Sensors 4.1 Introduction The KTY temperature sensor developed by Infineon Technologies is based on the principle of the Spreading Resistance. The expression Spreading Resistance derives
Etching Etching Definitions Isotropic Etching: same in all direction Anisotropic Etching: direction sensitive Selectivity: etch rate difference
Etching Etching Definitions Isotropic Etching: same in all direction Anisotropic Etching: direction sensitive Selectivity: etch rate difference between 2 materials Need strong selectivity from masking
Fabrication Technology
Fabrication Technology By B.G.Balagangadhar Department of Electronics and Communication Ghousia College of Engineering, Ramanagaram 1 OUTLINE Introduction Why Silicon The purity of Silicon Czochralski
Metallization. Typical current density ~105 A/cm2 Wires introduce parasitic resistance and capacitance
Metallization Interconnects Typical current density ~105 A/cm2 Wires introduce parasitic resistance and capacitance RC time delay Inter-Metal Dielectric -Prefer low dielectric constant to reduce capacitance
New Materials as an enabler for Advanced Chip Manufacturing
New Materials as an enabler for Advanced Chip Manufacturing Drive Innovation, Deliver Excellence ASM International Analyst and Investor Technology Seminar Semicon West July 10 2013 Outline New Materials:
6.777J/2.732J Design and Fabrication of Microelectromechanical Devices Spring Term Solution to Problem Set 2 (16 pts)
6.777J/2.732J Design and Fabrication of Microelectromechanical Devices Spring Term 2007 By Brian Taff (Adapted from work by Feras Eid) Solution to Problem Set 2 (16 pts) Issued: Lecture 4 Due: Lecture
Atomic Layer Deposition(ALD)
Atomic Layer Deposition(ALD) AlO x for diffusion barriers OLED displays http://en.wikipedia.org/wiki/atomic_layer_deposition#/media/file:ald_schematics.jpg Lam s market-leading ALTUS systems combine CVD
Making III-V contact with silicon substrates
106Technology focus: III-Vs on silicon Making III-V contact with silicon substrates High-speed logic, high-frequency/high-power transistors and photonics systems could benefit from marrying with silicon
Surface micromachining and Process flow part 1
Surface micromachining and Process flow part 1 Identify the basic steps of a generic surface micromachining process Identify the critical requirements needed to create a MEMS using surface micromachining
Introduction to Microeletromechanical Systems (MEMS) Lecture 5 Topics. JDS Uniphase MUMPs
Introduction to Microeletromechanical Systems (MEMS) Lecture 5 Topics JDS Uniphase MUMPS Foundry Process and Devices Foundry Process Sequence Design Rules and Process Interactions Examples CMOS for MEMS
CMOS Manufacturing process. Circuit designer. Design rule set. Process engineer. Set of optical masks. Fabrication process.
CMOS Manufacturing process Circuit design Set of optical masks Fabrication process Circuit designer Design rule set Process engineer All material: Chap. 2 of J. Rabaey, A. Chandrakasan, B. Nikolic, Digital
Nonplanar Metallization. Planar Metallization. Professor N Cheung, U.C. Berkeley
Nonplanar Metallization Planar Metallization Passivation Metal 5 (copper) Metal 3 (copper) Interlevel dielectric (ILD) Via (tungsten) Metal 1 (copper) Tungsten Plug to Si Silicon Caps and Plugs oxide oxide
200mm Next Generation MEMS Technology update. Florent Ducrot
200mm Next Generation MEMS Technology update Florent Ducrot The Most Exciting Industries on Earth Semiconductor Display Solar 20,000,000x reduction in COST PER TRANSISTOR in 30 years 1 20x reduction in
PROCESSING OF INTEGRATED CIRCUITS
PROCESSING OF INTEGRATED CIRCUITS Overview of IC Processing (Part I) Silicon Processing Lithography Layer Processes Use in IC Fabrication (Part II) Integrating the Fabrication Steps IC Packaging (Part
Metallization. Typical current density ~10 5 A/cm 2 Wires introduce parasitic resistance and capacitance
Metallization Interconnects Typical current density ~10 5 A/cm 2 Wires introduce parasitic resistance and capacitance RC time delay Inter-Metal Dielectric -Prefer low dielectric constant to reduce capacitance
Isolation of elements
1 In an IC, devices on the same substrate must be isolated from one another so that there is no current conduction between them. Isolation uses either the junction or dielectric technique or a combination
Issue 51 September 2013
Laser Decapsulation By Christopher Henderson Historically, failure analysts used either mechanical or chemical means to decapsulate integrated circuits. They used primarily mechanical means on hermetically-sealed
Schottky-Barrier-Height Modulation of Ni Silicide/Si Contacts by Insertion of Thin Er or Pt Layers
Schottky-Barrier-Height Modulation of Ni Silicide/Si Contacts by Insertion of Thin Er or Pt Layers Yoshihisa Ohishi 1, Kohei Noguchi 1, Kuniyuki Kakushima 2, Parhat Ahmet 1, Kazuo Tsutsui 2, Nobuyuki Sugii
ME 141B: The MEMS Class Introduction to MEMS and MEMS Design. Sumita Pennathur UCSB
ME 141B: The MEMS Class Introduction to MEMS and MEMS Design Sumita Pennathur UCSB Outline today Introduction to thin films Oxidation Deal-grove model CVD Epitaxy Electrodeposition 10/6/10 2/45 Creating
Laser Spike Annealing for sub-20nm Logic Devices
Laser Spike Annealing for sub-20nm Logic Devices Jeff Hebb, Ph.D. July 10, 2014 1 NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014 Outline Introduction Pattern Loading Effects LSA Applications
Advancing RIT to Submicron Technology: Design and Fabrication of O.5~j,m N-channel MOS Transistors
Advancing RIT to Submicron Technology: Design and Fabrication of O.5~j,m N-channel MOS Transistors Ivlichael Aquilino, Student Member, IEEE Absh act The design and fabrication of N-channel MOS transistors
Memory Devices. Ki-Nam Kim, President, Institut of Technology Samsung Electronics, 2010 IEDM, San Francisco.
Memory Devices In Korea now, Samsung : 2010, 30nm 2Gb DDRS DRAM/DDR3 SRAM 2011, Invest US $12 bil. for 20nm & SysLSI. Hynix : 2010, 26nm MLC- NAND Flash 2011, 30nm 4Gb DRAM At 2020, the demands of computing
Rapid Thermal Processing (RTP) Dr. Lynn Fuller
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Rapid Thermal Processing (RTP) Dr. Lynn Fuller Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585)
Lecture 8. Deposition of dielectrics and metal gate stacks (CVD, ALD)
Lecture 8 Deposition of dielectrics and metal gate stacks (CVD, ALD) Thin Film Deposition Requirements Many films, made of many different materials are deposited during a standard CMS process. Gate Electrodes
A Novel Body-tied Silicon-On-Insulator(SOI) n-channel metal-oxide-semiconductor. Field-Effect Transistor with Grounded Body Electrode
ETRI Journal, volume 17, number 4, January 1996 1 A Novel Body-tied Silicon-On-Insulator(SOI) n-channel Metal-Oxide-Semiconductor Field-Effect Transistor with Grounded Body Electrode Won-Gu Kang, Jong-Son
Manufacturer Part Number. Module 2: CMOS FEOL Analysis
Manufacturer Part Number description Module 2: CMOS FEOL Analysis Manufacturer Device # 2 Some of the information is this report may be covered by patents, mask and/or copyright protection. This report
Copyright by. Puneet Kohli
Copyright by Puneet Kohli 2003 The Dissertation Committee for Puneet Kohli Certifies that this is the approved version of the following dissertation: Fundamental Understanding of the Physics and Modeling
Thin Films: Sputtering Systems (Jaeger Ch 6 & Ruska Ch 7,) Can deposit any material on any substrate (in principal) Start with pumping down to high
Thin Films: Sputtering Systems (Jaeger Ch 6 & Ruska Ch 7,) Can deposit any material on any substrate (in principal) Start with pumping down to high vacuum ~10-7 torr Removes residual gases eg oxygen from
Lecture 10: MultiUser MEMS Process (MUMPS)
MEMS: Fabrication Lecture 10: MultiUser MEMS Process (MUMPS) Prasanna S. Gandhi Assistant Professor, Department of Mechanical Engineering, Indian Institute of Technology, Bombay, 1 Recap Various VLSI based
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 55, NO. 4, AUGUST
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 55, NO. 4, AUGUST 2008 1833 Radiation Effects in MOS Oxides James R. Schwank, Fellow, IEEE, Marty R. Shaneyfelt, Fellow, IEEE, Daniel M. Fleetwood, Fellow, IEEE,
Microstructures using RF sputtered PSG film as a sacrificial layer in surface micromachining
Sādhanā Vol. 34, Part 4, August 2009, pp. 557 562. Printed in India Microstructures using RF sputtered PSG film as a sacrificial layer in surface micromachining VIVEKANAND BHATT 1,, SUDHIR CHANDRA 1 and
Lecture 12. Physical Vapor Deposition: Evaporation and Sputtering Reading: Chapter 12. ECE Dr. Alan Doolittle
Lecture 12 Physical Vapor Deposition: Evaporation and Sputtering Reading: Chapter 12 Evaporation and Sputtering (Metalization) Evaporation For all devices, there is a need to go from semiconductor to metal.