MOS Front-End. Field effect transistor

Transcription

1 MOS Front-End Back-end Transistor Contact Front-end p-well STI n-well Front-end-of-line includes substrate, isolation, wells, transistor, silicide Field effect transistor MOSFET: Metal-Oxide-Semiconductor Field Effect Transistor Invented: Lilienfeld First made: Kahng, Attala 1960 Properties of a MOSFET: Small area Low power Simple technology Lower switching speed than bipolar device CMOS: Complementary MOS: NMOS + PMOS 1

2 NMOS and PMOS transistors NMOS Free electron Free hole PMOS Conducts at +V G Conducts at -V G NMOS + PMOS = CMOS: why? CMOS - inverter layout V dd V in PMOS B = nwell V ss V out V dd V in V out n-well NMOS B = pwell p-substrate Circuit schematic Silicon cross section 2

3 From NMOS to CMOS V dd High Low Low High Capacitive load High Low Low High GND NMOS inverter CMOS inverter NMOS logic: high power during low output. NMOS inverter slowly switches to high output. (Same effects in PMOS logic.) Present CMOS 0.18 µm CMOS is now produced by all major manufacturers. This process features: µm gate length, µm pitch nm gate oxide (regular SiO 2 ) 5-6 levels of metal interconnect About 10 7 transistors on a 1 cm 2 chip 1.2 GHz on-chip clock frequency 3

4 10 5 Gordon Moore 1965 (Prediction) Moore s Law 10 8 INTEL microprocessors Source: Intel website Pentium 4 Number of components per chip Transistors per chip Year Year Brews Law L t ox x j W s L min = 0.4 [ x j t ox (W s + W d ) 2 ] 1/3 L min : minimum gate length without short channel effects x j : junction depth (µm) t ox : oxide thickness (Å) W s, W d : depletion widths of source and drain junctions (µm) Moore s law implies gate length scaling Brews law implies: many other dimensions scale with it 4

5 ITRS roadblocks in CMOS front-end ITRS 2000 topics with no known solution : 90 nm node: Shallow junctions with x j nm, R s Ω/ 60 nm node: Gate dielectric thickness < 1.2 nm Gate tunnel current < 20 A/cm 2 Gate doping > 4x10 20 cm -3 In other words: the MOS transistor requires several research breakthroughs to continue scaling beyond the 100 nm node! Outline Introduction to CMOS (why CMOS?) CMOS process flow CMOS process modules (step by step) 5

6 STI (Shallow Trench Insolation) formation (field isolation) Sacrificial oxide (warstwa protekcyjna) on top of silicon: To avoid contamination Retrograde (wsteczne) n-well formation n-well 6

7 Retrograde p-well formation p-well n-well Gate oxide growth + poly deposition poly 7

8 After polysilicon deposition Photo: Philips Research After gate etch - S/D formation 8

9 PMOS S/D extension implant (and NMOS extension implant) Spacer formation thin oxide + nitride 9

10 NMOS - S/D implant Simultaneous source, drain and gate doping, and well contact doping PMOS - S/D implant 10

11 After S/D implants Silicidation TiSi 2 or CoSi 2 (sub-0.18 µm technologies) 11

12 TEM cross-section after silicidation TiSi 2 Spacer Poly gate TiSi 2 Photo: Intel Contact formation 12

13 CMOS inverter after first metal input input 0.25 µm CMOS after Metal 6 13

14 Outline Introduction to CMOS (why CMOS?) CMOS process flow CMOS process modules (step by step) CMOS process modules Field isolation Wells Gate dielectric Gate conductor Shallow junctions Pocket implants Spacers Source, drain and gate doping (Silicide) 14

15 Field isolation Purpose: to electrically isolate adjacent MOSFETs Traditional in bipolar and MOS: LOCOS isolation sub-0.35 µm CMOS: always Shallow Trench Isolation LOCOS field isolation Si 3 N 4 SiO 2 Si Stack deposition Stack etch LOCal Oxidation of Silicon Stack removal 15

16 Shallow trench isolation (STI) Stack deposition Oxidation Trench fill Stack removal Trench etch (deposition & CMP) Transistor well formation Purpose of the well: opposite-type to S/D: to give isolation between S/D and wafer (reverse-biased diodes) inversion gives channel conductivity Issues: Doping level determines V T and short channel effects Diode leakage, capacitance, parasites Deep doping (~ 1 µm) Vertical and lateral grading super steep retrograde well pockets 16

17 Conventional well Concentration As implanted After 6h 1150ºC in N 2 n-well Depth 1D depth profiles P-substrate 2D cross section Standard Technology in > 0.5 µm CMOS generations + Low cost - standard equipment - Large temperature budget: long time - high T - Large lateral diffusion - Highest doping concentration at surface Retrograde well As implanted Concentration n-well Depth n-well P-substrate Standard in (sub) 0.25 µm CMOS technologies + Buried peak doping concentration (channel stop, latch up,...) + Low temperature budget - Dedicated high energy ion implanter needed for n-well - Higher junction capacitance 17

18 Super steep retrograde well SSR peak Concentration Depth Well Ideal Realistic Source Gate SSR Well Drain < 0.25 µm CMOS: high channel doping to control short channel effects low V T necessary SSR well: low surface doping (giving low V T and high mobility) high doping at nm depth (reduces short channel effects) Gate oxide + gate polysilicon 18

19 Gate oxide formation Remove the existing SiO 2 that screens the silicon Clean the wafer Oxidize the wafer at high temperature Post-anneal (N 2, N 2 O, NO ) Immediately deposit polysilicon gate on top Thin oxide growth Furnace Wet (diluted H 2 O) - low temperature ( ºC) Dry (diluted) O 2 ( + nitridation N 2 O, NO) Temperature: ºC + Standard method, excellent uniformity, batch process - Run takes several hours. Very difficult for t ox < 2.5 nm Rapid Thermal Oxidation: Dry O 2 ( + nitridation N 2 O, NO) + Growth at higher temperature more nitrogen incorporation + Only a few minutes per wafer - Uniformity, reproducibility 19

20 TEM cross section thin oxide G. Timp et al., IEDM 1999 ITRS roadmap: oxide thickness (Equivalent) Oxide Thickness (nm) CMOS generation (µm) Leakage current through SiO 2 increases exponentially 20

21 Tunnel current n-gate (band diagrams at negative gate voltage) 3.1 ev n-gate qv G SiO 2 p-substrate SiO 2 p-substrate Thick oxide (> 4 nm): triangular tunnel barrier Fowler-Nordheim tunneling Thin oxide (< 4 nm): Trapezoidal barrier Direct tunneling Tunnel current - very thin oxide J G (A/cm 2 ) 1.E+02 1.E+01 1.E+00 1.E-01 1.E-02 1.E-03 1.E-04 1.E-05 Measurement Model t ox = 1.4nm t ox = 1.7nm t ox = 2.2nm Van Langevelde, IEDM 2001 V GS (V) Leakage current exceeds 1A/cm 2 (!) at 100 nm CMOS generation 21

22 ITRS: gate dielectric will change 2.5 SiO 2 High k EOT (nm) CMOS generation (µm) But: no high-k dielectric yet fulfills all requirements! Candidate high-k gate dielectrics vacuum SiO 2 TiO Al 2 O 2 3 Si 3 N HfO 2 4 Ta 2 O 5 ZrO 2 BST K:

23 Gate electrode formation Dual-flavor gate technology in CMOS n + and p + doping of polysilicon Gate depletion Boron penetration Dual-flavor polysilicon gates n + poly for the NMOS transistor, p + poly for the PMOS Symmetric: given same oxide thickness and doping levels, V T NMOS = -V T PMOS Excellent work functions Convenient processing: self-aligned source, gate, drain and well contact implant; all activated together. Issues: how to achieve high gate doping connection between n + poly and p + poly (inter-diffusion of impurities between n + and p + poly) 23

24 Doping of polysilicon n + gate doping with S/D implant Phosphorus gives the best gate doping: very high solubility, high diffusion, high activation but: too high diffusion for source/drain implant Arsenic more complicated: lower diffusion constant, lower activation getters at the Si/SiO 2 interface; evaporates de-activates in ºC thermal treatments Antimony: too low solubility (4x10 19 cm -3 at 1000ºC) 24

25 p + gate doping with S/D implant Indium: Too low solubility (< cm -3 ) Diffuses through gate oxide ( indium penetration ) Boron: The only option (either with B or BF 2 implant) Risk of boron penetration (since 0.25 µm CMOS) Clustering above solubility limit: problematic de-activates in ºC thermal treatments Gate depletion V G = V FB V G > V FB V G >> V FB V G >>> V FB channel n + gate Ionized (activated) As atom Free electron n + poly gate for NMOS: gate depletion is inevitable Lower capacitance less current 25

26 Boron penetration Gate oxide [B] (cm -3 ) polysilicon monosilicon as-implanted proper activation boron penetration depth Gate doping > cm -3 Channel doping << cm -3 Slight boron penetration dramatic V T shift Solutions: reduce thermal steps, replace gate oxide... PMOS S/D extension implant 26

27 Extensions: purpose and requirements Suppress short channel effects Add series resistance (good for µm technology, LDDs) Brews Law: L min [ x j t ox (W s + W d ) 2 ] 1/3 Criteria for shallow junctions: Junction depth Treated in the following slides Sheet resistance Good diode operation Junction profile steepness Uniformity, reproducibility Low defect density (residual crystal damage) CMOS compatible (materials, thermal budget) ITRS scaling of shallow junctions Junction depth (nm) Sheet resistance (Ω/) PMOS NMOS CMOS generation (µm) CMOS generation (µm) 27

28 Sheet resistance Impurity concentration Depth profile x j Source/drain Channel Depth Sheet resistance R s depends on the concentration of free carriers C(x) and on the mobility of these carriers µ(c): x=x j R s = 1 / q C(x) µ(c) dx x=0 (approximation for not-too-steep profiles) Aim for high concentration; junction depth is imposed by generation. Steep tail at fixed x j lower resistivity! Junction depth Definition: junction depth (x j ) = metallurgical junction: the depth where the n-type concentration equals the p-type concentration. Determination of junction depth: SIMS (or SRP). Impurity concentration Source/drain Channel Steepness is important; but also the proper activation of the peak (should be below the solubility limit at the anneal temperature) x j Depth 28

29 B and As diffusion - example Data: Philips Research B concentration (cm -3 ) As concentration (cm -3 ) Depth (nm) Depth (nm) High T pushes junction - much stronger effect for Boron Shallow junction annealing Furnace anneals: typically 2 + -hour runs, slow ramp up and down too much TED too much diffusion Rapid thermal anneals Spike RTA anneals Laser anneals > 0.25 µm < 0.13 µm µm Photo: Sematech 29

30 Rapid thermal anneal cycle temperature Anneal (0-60 seconds) Ramp-up (50ºC/s) Ramp-down (25ºC/s) First ramp-up Stabilisation C time Pockets Large Angle Tilt Punch Through Stopper Also called: HALO latips well Pocket Punch through stopper implanted under tilt angle after gate formation Reduces depletion regions of source and drain Angle, dose and energy are critical parameters + low channel doping, low V T possible (low voltage technology) - Process control, more expensive implanter 30

31 Spacer formation Standard: TEOS or Si 3 N 4 deposition Plasma etch Spacer process flows Two-layer deposition (e.g. SiO 2 + Si 3 N 4 ) Plasma etch of top layer Optional etch of layer 2 31

32 PMOS - S/D implant Source/drain implant Purpose: S/D implant adds impurities to the shallow junctions: lower sheet resistance deeper junction (convenient for salicidation) Gate doping Doping of the well contacts Optimization: Low sheet resistance of junctions and poly Low gate depletion - no boron penetration Good diodes; suppression of junction spiking Low salicide contact resistance 32

33 Activation anneal Last step of the MOS front-end fabrication Activation of: gate, source and drain implants High temperature required for good activation Short time required for suppression of diffusion Therefore: again, Rapid Thermal Anneal Optimization of this step is truly process integration Fabrication after this anneal can influence activation: de-activation further diffusion (dr. R.A.M. Wolters ) MOS front-end Further reading S. Wolf - The submicron MOSFET F. Pierret - Field effect devices A. S. Grove: Physics and technology of semiconductor devices, John Wiley & sons The Technology roadmap for semiconductors: A dictionary of semiconductors: Nice 3D view of transistor fabrication and operation: Many interesting links at 33

34 Closing remarks MOS technology changed a lot over the years CMOS front-end-of-line technology gets complex many new materials tight process windows incredible pace of innovation Scaling down to 30 nm feasible Many challenges for research! 34