1 Construction Analysis Analog Devices ADSP KS-160 SHARC Digital Signal Processor Report Number: SCA Global Semiconductor Industry the Serving Since N. Hartford Drive Scottsdale, AZ Phone: Fax: Internet:
2 INDEX TO TEXT TITLE PAGE INTRODUCTION 1 MAJOR FINDINGS 1 TECHNOLOGY DESCRIPTION Assembly 2 Die Process 2-3 ANALYSIS RESULTS I Assembly 4 ANALYSIS RESULTS II Die Process and Design 5-7 ANALYSIS PROCEDURE 8 TABLES Overall Evaluation 9 Package Markings 10 Wirebond Strength 10 Die Material Analysis 10 Horizontal Dimensions 11 Vertical Dimensions 12 - i -
3 INTRODUCTION This report describes a construction analysis of the Analog Devices ADSP KS-160 SHARC Digital Signal Processor. Two devices which were packaged in 240-pin Plastic Quad Flat Packages (PQFP) were received for the analysis. The devices were date coded 9641 and The majority of the analysis was performed on the device date coded MAJOR FINDINGS Questionable Items: 1 none. Special Features: Sub-micron gate lengths (0.5 micron). Tungsten plugs. 1 These items present possible quality or reliability concerns. They should be discussed with the manufacturer to determine their possible impact on the intended application
4 TECHNOLOGY DESCRIPTION Assembly: The devices were packaged in 240-pin Plastic Quad Flat Packages (PQFP). A copper heat slug (heatsink) was employed on the top of the package (cavity down orientation). It was internally connected to ground. Wirebonding method: A thermosonic ball bond technique employing 1.2 mil O.D. gold wire was used. Dicing: Sawn (full depth) dicing. Die attach: A silver epoxy compound. Die Process Fabrication process: Selective oxidation CMOS process employing twin-wells in an N substrate. Die coat: No die coat was used on the devices. Final passivation: A layer of nitride over a layer of silicon-dioxide. Metallization: Two levels of metal defined by standard dry-etch techniques. Metal 2 consisted of aluminum with a titanium-nitride cap and barrier. Metal 1 consisted of aluminum, a titanium nitride cap and barrier, and a titanium adhesion layer. Tungsten plugs were used as the vertical interconnect under both metal layers. They were lined with titanium-nitride. Interlevel dielectric: Interlevel dielectric consisted of four layers of silicon-dioxide with a planarizing spin-on-glass (SOG) between the third and fourth layer. Pre-metal dielectric: This dielectric consisted of a layer of reflow glass over densified oxides
5 TECHNOLOGY DESCRIPTION (continued) Polysilicon: Two layers of polysilicon were used on the die. Poly 1 (polysilicon and tungsten silicide) was used to form redundancy fuses, all gates on the die, and word lines in the array. Poly 2 was used to form pull-up resistors in the cell array, and formed resistors in fuse blocks which were connected to one end of the poly 1 fuses. Both poly layers were defined by a dry-etch of good quality. Diffusions: Implanted N+ and P+ diffusions formed the sources/drains of transistors. No silicide was present on diffusions. An LDD process was used with the oxide sidewall spacers left in place. N+ diffusions were pushed down at tungsten contacts. Wells: Planar (no step in LOCOS) twin-well process in the N substrate. No epi layer. Redundancy: Fuses consisting of poly 1 were present on the die. Passivation and interlevel dielectric cutouts were made over the fuses. One end of the fuse structure was connected to metal 1, while the other end was connected to a poly 2 resistor. Some laser blown fuses were noted. Memory cells: The die employed a 2 Mbit SRAM array. The memory cells used a 4T CMOS SRAM cell design. Metal 2 distributed GND and Vdd (via Metal 1), and formed the bit lines using metal 1 links. Metal 1 was used as piggy-back word lines. Poly 1 formed the word lines, select, and storage gates. Poly 2 formed pullup resistors and distributed Vdd. Both metals 1 and 2 were used in the bond pads
6 ANALYSIS RESULTS I Assembly: Figures 1-2 Questionable Items: 1 None. Special Features: None. General Items: Overall package: The device was packaged in a 240-pin PQFP. A large copper heat slug (heatsink) was employed on the top of the package (cavity down orientation). It was internally connected to GND. Wirebonding method: A thermosonic ball bond technique employing 1.2 mil gold wire was used. All bonds were well formed and placed. Bond strengths were normal as determined by wire pull tests. Dicing: Sawn (full depth). No large chips or cracks were noted. Die attach: A silver epoxy compound of normal quality. 1 These items present possible quality or reliability concerns. They should be discussed with the manufacturer to determine their possible impact on the intended application
7 ANALYSIS RESULTS II Die Process and Design: Figures 3-39 Questionable Items: 1 None. Special Features: Sub-micron gate lengths (0.5 micron). General Items: Fabrication process: Selective oxidation CMOS process employing twin-wells in an N substrate. Process implementation: Die layout was clean and efficient. Alignment was good at all levels. Die surface defects: None. No contamination, toolmarks or processing defects were noted. Passivation: A layer of nitride over a layer of silicon-dioxide. Passivation coverage and edge seal were good. Integrity test indicated defect free passivation. Metallization: Two levels of metallization were used. Metal 2 consisted of aluminum with a titanium-nitride cap and barrier. Metal 1 consisted of aluminum, titanium-nitride cap and barrier, and a titanium adhesion layer. Tungsten plugs were employed under both metal layers. The plugs were lined with titanium-nitride. Metal patterning: All metal layers were defined by a dry etch of good quality. 1 These items present possible quality concerns. They should be discussed with the manufacturer to determine their possible impact on the intended application
8 ANALYSIS RESULTS II (continued) Metal defects: None. No voiding, notching or cracking of the metal layers was found. Silicon nodules were found following removal of metal 1. Metal step coverage: Virtually no metal thinning was noted due to the use of tungsten plugs. The tungsten plugs were nearly level with the oxide surface, so no large steps were present for the metal to cover. Vias and contacts: Vias and contacts were defined by a dry-etch. No significant over-etching was noted. Interlevel dielectric: Interlevel dielectric consisted of four layers of silicon-dioxide with a spin-on-glass (SOG) between the third and fourth layers to aid in planarization. No problems were noted. Pre-metal dielectric: This dielectric consisted of a layer of reflow glass (BPSG) over densified oxide. No problems were found.. Polysilicon: Two layers of polysilicon were employed. Poly 1 (polysilicon and tungsten silicide) formed the redundancy fuses, all gates on the die, and word lines in the array. Poly 2 was used to form resistors in the cell array and outside the fuse blocks. Definition was by a dry etch of good quality. No problems were found. Isolation: LOCOS (local oxide isolation). No problems were noted at birdsbeak or elsewhere and no step was present at the well boundaries. Diffusions: Implanted N+ and P+ diffusions were used for sources and drains. Oxide sidewall spacers were present to provide LDD spacing. Deep (pushed down) N+ diffusions were noted under contacts in N regions. Diffusions were not silicided. No problems were found. Wells: Twin-wells were employed in an N substrate. No step was present at the well boundaries. No problems were noted
9 ANALYSIS RESULTS II (continued) Buried contacts: Direct poly-to-diffusion (buried) contacts were only used in the SRAM array. No problems were found in these areas. Redundancy: Poly 1 fuses were present along the row and column decode logic outside the SRAM array. Passivation and interlevel dielectric cutouts were made over the fuses. Laser blown fuses were noted. Memory cells: The die employed a 2 Mbit SRAM array. The memory cells used a 4T CMOS SRAM cell design. Metal 2 distributed GND and Vdd, and formed the bit lines using metal 1 links. Metal 1 was used as the piggy-back word lines. Poly 1 formed the word lines, select, and storage gates. Poly 2 formed pull-up resistors and distributed Vdd. Cell size was 3.3 x 5.7 microns (19 microns 2 )
10 PROCEDURE The devices were subjected to the following analysis procedures: External inspection X-ray Decap SEM of passivation Passivation integrity test (chemical) Wirepull test Passivation removal SEM inspection of metal 2 Aluminum 2 removal and inspect Delayer to metal 1 and inspect Aluminum 1 removal and inspect barrier Delayer to polycide/substrate and inspect Die sectioning (90 for SEM) * Measure horizontal dimensions Measure vertical dimensions Die material analysis * Delineation of cross-sections is by silicon etch unless otherwise indicated
11 OVERALL QUALITY EVALUATION: Overall Rating: Good DETAIL OF EVALUATION Package integrity: Die placement: Die attach quality: Wire spacing: Wirebond placement: Wirebond quality: Dicing quality: Wirebond method Die attach method Dicing G G G N N G G Thermosonic ball bonds using 1.2 mil gold wire. Silver-epoxy Sawn (full depth) Die surface integrity: Toolmarks (absence) Particles (absence) Contamination (absence) Process defects (absence) General workmanship Passivation integrity Metal definition Metal integrity Metal registration Contact coverage Contact registration G G G G G G G G G G G G = Good, P = Poor, N = Normal, NP = Normal/Poor - 9 -
12 PACKAGE MARKINGS TOP Sample 1 Sample 2 (LOGO) ANALOG DEVICES (LOGO) ANALOG DEVICES ADSP ADSP KS KS-160 ED/C (SHARC LOGO) ED/C (SHARC LOGO) BOTTOM WAFER H HONG KONG WAFER H HONG KONG WIREPULL TEST Sample 2 # of wires tested: 25 Bond lifts: 0 Force to break - high: 9g - low: 5.25g - avg.: 7.45g - std. dev.: 1.0 DIE MATERIAL IDENTIFICATION Overlay passivation: Metallization 2: Interlevel dielectric: Metallization 1: Plugs: Pre-metal glass: Silicide (Poly 1): Nitride over silicon-dioxide. Aluminum with a titanium-nitride cap and barrier. Multiple layers of silicon-dioxide including SOG. Aluminum with a titanium-nitride cap and barrier, on a titanium adhesion layer. Tungsten, lined with titanium-nitride. BPSG reflow glass on densified oxide. Tungsten
13 HORIZONTAL DIMENSIONS Die size: 11.9 x 14.9 mm (468 x 586 mils) Die area: 177 mm 2 (274,248 mils 2 ) Min pad size: Min pad window: Min pad space: Min metal 2 width: Min metal 2 space: Min metal 2 pitch: Min metal 1 width: Min metal 1 space: Min metal 1 pitch: Min via: Min contact: Min polycide width: Min polycide space: Min gate length * - (N-channel): 0.11 x 0.11 mm (4.4 x 4.4 mils) 0.09 x 0.09 mm (3.7 x 3.7 mils) 40 microns 0.8 micron 1.0 micron 1.8 micron (uncontacted) 0.6 micron 0.7 micron 1.3 micron (uncontacted) 0.45 micron 0.5 micron 0.5 micron 0.7 micron 0.5 micron - (P-channel): 0.5 micron Min LOCOS: 0.8 micron SRAM cell size: 19.0 microns 2 SRAM cell pitch: 3.3 x 5.7 microns * Physical gate length
15 INDEX TO FIGURES ASSEMBLY Figures 1-2 DIE LAYOUT AND IDENTIFICATION Figures 3-6 PHYSICAL DIE STRUCTURES Figures 7-39 REDUNDANCY FUSES Figures COLOR DRAWING OF DIE STRUCTURE Figure 26 SRAM MEMORY CELL STRUCTURES Figures CIRCUIT LAYOUT AND I/O Figure ii -
16 Figure 1. Package photographs of the Analog Devices ADSP KS-160 SHARC Digital Signal Processor. Mag. 2.5x.
17 PIN 1 top Figure 2. X-ray view of the package. Mag. 3x.
18 Figure 3. Portion of the Analog Devices ADSP KS-160 die. Mag. 26x.
19 Figure 3a. Portion of the Analog Devices ADSP KS-160 die. Mag. 26x.
20 Figure 3b. Portion of the Analog Devices ADSP KS-160 die. Mag. 26x.
21 Figure 3c. Remaining portion of the Analog Devices ADSP KS-160 die. Mag. 26x.
22 Figure 4. Optical views of die markings. Mag. 500x.
23 Figure 5. Optical views of die corners. Mag. 80x.
24 METAL 2 SLOT Figure 6. Optical views illustrating a slotted bus line and mask revision numbers. Mag. 400x.
25 EDGE OF PASSIVATION SUBSTRATE Mag. 1200x EDGE OF PASSIVATION METAL 2 METAL 1 N+ Mag. 6400x Figure 7. SEM section views of the die edge seal.
26 PASSIVATION 1 PASSIVATION 2 METAL 2 METAL 1 W PLUG LOCOS POLY 1 GATE N+ S/D PASSIVATION 1 PASSIVATION 2 SOG METAL 2 METAL 1 W PLUG LOCOS N+ S/D POLY 1 GATE Figure 8. SEM section views illustrating general structure. Mag. 13,000x.
27 Mag. 4800x Mag. 9600x Figure 9. SEM views illustrating final passivation. 60.
28 PASSIVATION 2 PASSIVATION 1 METAL 2 INTERLEVEL DIELECTRIC METAL 1 Mag. 26,000x TIN CAP ALUMINUM 2 TiN BARRIER Mag. 52,000x Figure 10. SEM section views illustrating metal 2 line profiles.
29 Mag. 3250x METAL 2 Mag. 6500x VIAS Mag. 6500x METAL 2 Figure 11. Topological SEM views of metal 2 patterning. 0.
30 METAL 2 Mag. 12,400x TiN CAP ALUMINUM 2 Mag. 26,000x TiN BARRIER TiN BARRIER W PLUG Mag. 40,000x Figure 12. Perspective SEM views of metal 2 step coverage, barrier, and plug. 60.
31 PASSIVATION 2 SOG METAL 2 W PLUG Mag. 13,000x METAL 1 LOCOS POLY 1 METAL 2 INTERLEVEL DIELECTRIC W PLUG Mag. 26,000x METAL 1 METAL 2 W PLUG INTERLEVEL DIELECTRIC Mag. 26,000x SOG METAL 1 Figure 13. SEM section views of typical vias.
32 METAL 2 INTERLEVEL DIELECTRIC METAL 1 Mag. 26,000x TiN CAP ALUMINUM 1 TiN BARRIER Mag. 52,000x Figure 14. SEM section views of metal 1 line profiles.
33 CONTACT METAL 1 POLY METAL 1 VIA METAL 1 Figure 15. Topological SEM views of metal 1 patterning. Mag. 6500x, 0.
34 METAL 1 Mag. 6500x Mag. 10,000x TiN CAP ALUMINUM 1 Mag. 30,000x TiN BARRIER Figure 16. Perspective SEM views of metal 1 step coverage. 60.
35 TiN BARRIER Mag. 10,000x Si TiN BARRIER W PLUG Mag. 40,000x Figure 17. Perspective SEM views of metal 1 barrier and plugs. 60.
36 METAL 1 W PLUG POLY 1 LOCOS METAL 1 W PLUG Ti ADHESION LAYER LOCOS N+ METAL 1 W PLUG LOCOS P+ Figure 18. SEM section views illustrating typical metal 1 contacts. Mag. 26,000x.
37 Mag. 3200x Mag. 3200x POLY N+ P+ Mag. 6500x Figure 19. Topological SEM views of poly 1 patterning. 0.
40 DENSIFIED OXIDE POLY 1 LOCOS GATE OXIDE Figure 22. SEM section view of typical birdsbeak. Mag. 52,000x. Mag. 800x P-WELL N- SUBSTRATE METAL 1 Mag. 6500x LOCOS P+ N+ P-WELL N- SUBSTRATE Figure 23. Section views illustrating well structure.
41 Mag. 800x BLOWN FUSE Mag. 800x INTACT FUSE LASER BLOWN FUSE Mag. 1600x Figure 24. Optical and SEM views of typical fuses.
42 PASSIVATION Mag. 4800x, 60 CUTOUT CUTOUT Mag. 6500x POLY 1 FUSE PASSIVATION METAL 2 POLY 2 METAL 1 Mag. 13,000x LOCOS POLY 1 FUSE Figure 25. Perspective and cross-section SEM views of typical fuses.
43 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, METAL 1 W PLUG NITRIDE PASSIVATION METAL 2 INTERLEVEL DIELECTRIC PRE-METAL GLASS GATE OXIDE N+ S/D P-WELL N SUBSTRATE GLASS PASSIVATION W SILICIDE POLY 1 SOG LOCAL OXIDE Orange = Nitride, Blue = Metal, Yellow = Oxide, Green = Poly, Red = Diffusion, and Gray = Substrate,,,,,,, P+ S/D Figure 26. Color cross section drawing illustrating device structure. DENSIFIED OXIDE N-WELL,,,,,,,,,,,, Analog Devices ADSP KS-160
44 metal 2 metal 1 poly Figure 27. Perspective SEM views of the SRAM cell array. Mag. 5000x, 60.
45 GND BIT BIT metal 2 PIGGYBACK WORD LINE GND metal 1 WORD GND BIT BIT poly Figure 28. Perspective SEM views of the SRAM cell array. Mag. 10,000x, 60.
46 POLY 2 RESISTOR INTERLEVEL CONTACT POLY 1 POLY 1 WORD LINE SELECT GATE POLY 2 POLY 1 Figure 29. Detailed SEM views of the SRAM cell structures (delayered). Mag. 42,000x, 60.
47 GND metal 2 BIT BIT PIGGYBACK WORD LINE GND metal 1 WORD LINE poly Figure 30. Topological SEM views of the SRAM cell array. Mag. 3200x, 0.
48 GND BIT BIT metal 2 PIGGYBACK WORD LINE GND BIT BIT metal 1 Figure 31. Detailed topological SEM views of an SRAM cell. Mag. 13,000x, 0.
49 4 GND V DD BIT 1 R1 3 BIT 2 R2 GND unlayered WORD R1 R2 BIT 1 2 BIT 3 4 Figure 32. Detailed topological SEM view and schematic of an SRAM cell. Mag. 13,000x, 0.
50 METAL 2 BIT LINE Mag. 13,000x METAL 1 LINK POLY 1 STORAGE GATE N+ S/D METAL 2 BIT LINE W PLUG METAL 1 LINK Mag. 20,000x POLY 2 W PLUG METAL 1 LINK POLY 1 SELECT GATE W PLUG Mag. 26,000x N+ S/D Figure 33. SEM section views of an SRAM cell (parallel to bit line).
52 METAL 2 BIT LINE BIT LINE CONTACT POLY 1 WORD / SELECT LINE Mag. 13,000x POLY 1 WORD / SELECT LINE LOCOS GATE OXIDE Mag. 26,000x Figure 35. SEM section views of the SRAM cell array (perpendicular to bit line).
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