Analog Devices ADSP KS-160 SHARC Digital Signal Processor

Size: px
Start display at page:

Download "Analog Devices ADSP KS-160 SHARC Digital Signal Processor"

Transcription

1 Construction Analysis Analog Devices ADSP KS-160 SHARC Digital Signal Processor Report Number: SCA Global Semiconductor Industry the Serving Since N. Hartford Drive Scottsdale, AZ Phone: Fax: Internet:

2 INDEX TO TEXT TITLE PAGE INTRODUCTION 1 MAJOR FINDINGS 1 TECHNOLOGY DESCRIPTION Assembly 2 Die Process 2-3 ANALYSIS RESULTS I Assembly 4 ANALYSIS RESULTS II Die Process and Design 5-7 ANALYSIS PROCEDURE 8 TABLES Overall Evaluation 9 Package Markings 10 Wirebond Strength 10 Die Material Analysis 10 Horizontal Dimensions 11 Vertical Dimensions 12 - i -

3 INTRODUCTION This report describes a construction analysis of the Analog Devices ADSP KS-160 SHARC Digital Signal Processor. Two devices which were packaged in 240-pin Plastic Quad Flat Packages (PQFP) were received for the analysis. The devices were date coded 9641 and The majority of the analysis was performed on the device date coded MAJOR FINDINGS Questionable Items: 1 none. Special Features: Sub-micron gate lengths (0.5 micron). Tungsten plugs. 1 These items present possible quality or reliability concerns. They should be discussed with the manufacturer to determine their possible impact on the intended application

4 TECHNOLOGY DESCRIPTION Assembly: The devices were packaged in 240-pin Plastic Quad Flat Packages (PQFP). A copper heat slug (heatsink) was employed on the top of the package (cavity down orientation). It was internally connected to ground. Wirebonding method: A thermosonic ball bond technique employing 1.2 mil O.D. gold wire was used. Dicing: Sawn (full depth) dicing. Die attach: A silver epoxy compound. Die Process Fabrication process: Selective oxidation CMOS process employing twin-wells in an N substrate. Die coat: No die coat was used on the devices. Final passivation: A layer of nitride over a layer of silicon-dioxide. Metallization: Two levels of metal defined by standard dry-etch techniques. Metal 2 consisted of aluminum with a titanium-nitride cap and barrier. Metal 1 consisted of aluminum, a titanium nitride cap and barrier, and a titanium adhesion layer. Tungsten plugs were used as the vertical interconnect under both metal layers. They were lined with titanium-nitride. Interlevel dielectric: Interlevel dielectric consisted of four layers of silicon-dioxide with a planarizing spin-on-glass (SOG) between the third and fourth layer. Pre-metal dielectric: This dielectric consisted of a layer of reflow glass over densified oxides

5 TECHNOLOGY DESCRIPTION (continued) Polysilicon: Two layers of polysilicon were used on the die. Poly 1 (polysilicon and tungsten silicide) was used to form redundancy fuses, all gates on the die, and word lines in the array. Poly 2 was used to form pull-up resistors in the cell array, and formed resistors in fuse blocks which were connected to one end of the poly 1 fuses. Both poly layers were defined by a dry-etch of good quality. Diffusions: Implanted N+ and P+ diffusions formed the sources/drains of transistors. No silicide was present on diffusions. An LDD process was used with the oxide sidewall spacers left in place. N+ diffusions were pushed down at tungsten contacts. Wells: Planar (no step in LOCOS) twin-well process in the N substrate. No epi layer. Redundancy: Fuses consisting of poly 1 were present on the die. Passivation and interlevel dielectric cutouts were made over the fuses. One end of the fuse structure was connected to metal 1, while the other end was connected to a poly 2 resistor. Some laser blown fuses were noted. Memory cells: The die employed a 2 Mbit SRAM array. The memory cells used a 4T CMOS SRAM cell design. Metal 2 distributed GND and Vdd (via Metal 1), and formed the bit lines using metal 1 links. Metal 1 was used as piggy-back word lines. Poly 1 formed the word lines, select, and storage gates. Poly 2 formed pullup resistors and distributed Vdd. Both metals 1 and 2 were used in the bond pads

6 ANALYSIS RESULTS I Assembly: Figures 1-2 Questionable Items: 1 None. Special Features: None. General Items: Overall package: The device was packaged in a 240-pin PQFP. A large copper heat slug (heatsink) was employed on the top of the package (cavity down orientation). It was internally connected to GND. Wirebonding method: A thermosonic ball bond technique employing 1.2 mil gold wire was used. All bonds were well formed and placed. Bond strengths were normal as determined by wire pull tests. Dicing: Sawn (full depth). No large chips or cracks were noted. Die attach: A silver epoxy compound of normal quality. 1 These items present possible quality or reliability concerns. They should be discussed with the manufacturer to determine their possible impact on the intended application

7 ANALYSIS RESULTS II Die Process and Design: Figures 3-39 Questionable Items: 1 None. Special Features: Sub-micron gate lengths (0.5 micron). General Items: Fabrication process: Selective oxidation CMOS process employing twin-wells in an N substrate. Process implementation: Die layout was clean and efficient. Alignment was good at all levels. Die surface defects: None. No contamination, toolmarks or processing defects were noted. Passivation: A layer of nitride over a layer of silicon-dioxide. Passivation coverage and edge seal were good. Integrity test indicated defect free passivation. Metallization: Two levels of metallization were used. Metal 2 consisted of aluminum with a titanium-nitride cap and barrier. Metal 1 consisted of aluminum, titanium-nitride cap and barrier, and a titanium adhesion layer. Tungsten plugs were employed under both metal layers. The plugs were lined with titanium-nitride. Metal patterning: All metal layers were defined by a dry etch of good quality. 1 These items present possible quality concerns. They should be discussed with the manufacturer to determine their possible impact on the intended application

8 ANALYSIS RESULTS II (continued) Metal defects: None. No voiding, notching or cracking of the metal layers was found. Silicon nodules were found following removal of metal 1. Metal step coverage: Virtually no metal thinning was noted due to the use of tungsten plugs. The tungsten plugs were nearly level with the oxide surface, so no large steps were present for the metal to cover. Vias and contacts: Vias and contacts were defined by a dry-etch. No significant over-etching was noted. Interlevel dielectric: Interlevel dielectric consisted of four layers of silicon-dioxide with a spin-on-glass (SOG) between the third and fourth layers to aid in planarization. No problems were noted. Pre-metal dielectric: This dielectric consisted of a layer of reflow glass (BPSG) over densified oxide. No problems were found.. Polysilicon: Two layers of polysilicon were employed. Poly 1 (polysilicon and tungsten silicide) formed the redundancy fuses, all gates on the die, and word lines in the array. Poly 2 was used to form resistors in the cell array and outside the fuse blocks. Definition was by a dry etch of good quality. No problems were found. Isolation: LOCOS (local oxide isolation). No problems were noted at birdsbeak or elsewhere and no step was present at the well boundaries. Diffusions: Implanted N+ and P+ diffusions were used for sources and drains. Oxide sidewall spacers were present to provide LDD spacing. Deep (pushed down) N+ diffusions were noted under contacts in N regions. Diffusions were not silicided. No problems were found. Wells: Twin-wells were employed in an N substrate. No step was present at the well boundaries. No problems were noted

9 ANALYSIS RESULTS II (continued) Buried contacts: Direct poly-to-diffusion (buried) contacts were only used in the SRAM array. No problems were found in these areas. Redundancy: Poly 1 fuses were present along the row and column decode logic outside the SRAM array. Passivation and interlevel dielectric cutouts were made over the fuses. Laser blown fuses were noted. Memory cells: The die employed a 2 Mbit SRAM array. The memory cells used a 4T CMOS SRAM cell design. Metal 2 distributed GND and Vdd, and formed the bit lines using metal 1 links. Metal 1 was used as the piggy-back word lines. Poly 1 formed the word lines, select, and storage gates. Poly 2 formed pull-up resistors and distributed Vdd. Cell size was 3.3 x 5.7 microns (19 microns 2 )

10 PROCEDURE The devices were subjected to the following analysis procedures: External inspection X-ray Decap SEM of passivation Passivation integrity test (chemical) Wirepull test Passivation removal SEM inspection of metal 2 Aluminum 2 removal and inspect Delayer to metal 1 and inspect Aluminum 1 removal and inspect barrier Delayer to polycide/substrate and inspect Die sectioning (90 for SEM) * Measure horizontal dimensions Measure vertical dimensions Die material analysis * Delineation of cross-sections is by silicon etch unless otherwise indicated

11 OVERALL QUALITY EVALUATION: Overall Rating: Good DETAIL OF EVALUATION Package integrity: Die placement: Die attach quality: Wire spacing: Wirebond placement: Wirebond quality: Dicing quality: Wirebond method Die attach method Dicing G G G N N G G Thermosonic ball bonds using 1.2 mil gold wire. Silver-epoxy Sawn (full depth) Die surface integrity: Toolmarks (absence) Particles (absence) Contamination (absence) Process defects (absence) General workmanship Passivation integrity Metal definition Metal integrity Metal registration Contact coverage Contact registration G G G G G G G G G G G G = Good, P = Poor, N = Normal, NP = Normal/Poor - 9 -

12 PACKAGE MARKINGS TOP Sample 1 Sample 2 (LOGO) ANALOG DEVICES (LOGO) ANALOG DEVICES ADSP ADSP KS KS-160 ED/C (SHARC LOGO) ED/C (SHARC LOGO) BOTTOM WAFER H HONG KONG WAFER H HONG KONG WIREPULL TEST Sample 2 # of wires tested: 25 Bond lifts: 0 Force to break - high: 9g - low: 5.25g - avg.: 7.45g - std. dev.: 1.0 DIE MATERIAL IDENTIFICATION Overlay passivation: Metallization 2: Interlevel dielectric: Metallization 1: Plugs: Pre-metal glass: Silicide (Poly 1): Nitride over silicon-dioxide. Aluminum with a titanium-nitride cap and barrier. Multiple layers of silicon-dioxide including SOG. Aluminum with a titanium-nitride cap and barrier, on a titanium adhesion layer. Tungsten, lined with titanium-nitride. BPSG reflow glass on densified oxide. Tungsten

13 HORIZONTAL DIMENSIONS Die size: 11.9 x 14.9 mm (468 x 586 mils) Die area: 177 mm 2 (274,248 mils 2 ) Min pad size: Min pad window: Min pad space: Min metal 2 width: Min metal 2 space: Min metal 2 pitch: Min metal 1 width: Min metal 1 space: Min metal 1 pitch: Min via: Min contact: Min polycide width: Min polycide space: Min gate length * - (N-channel): 0.11 x 0.11 mm (4.4 x 4.4 mils) 0.09 x 0.09 mm (3.7 x 3.7 mils) 40 microns 0.8 micron 1.0 micron 1.8 micron (uncontacted) 0.6 micron 0.7 micron 1.3 micron (uncontacted) 0.45 micron 0.5 micron 0.5 micron 0.7 micron 0.5 micron - (P-channel): 0.5 micron Min LOCOS: 0.8 micron SRAM cell size: 19.0 microns 2 SRAM cell pitch: 3.3 x 5.7 microns * Physical gate length

14 VERTICAL DIMENSIONS Die thickness: 0.45 mm (18 mils) Layers Passivation 2: Passivation 1: Metal 2 - cap: 0.6 micron 0.15 micron 0.04 micron (approx.) - aluminum: 0.7 micron - barrier: 0.09 micron - plugs: micron Interlevel dielectric - glass 4: 0.5 micron (average) - glass 3: 0.15 micron (average) - glass 2: micron - glass 1: 0.15 micron (average) Metal 1 - cap: 0.15 micron (approx.) - aluminum: 0.5 micron - barrier: 0.1 micron - plugs: micron Pre-metal glass: Polycide - silicide: 0.65 micron 0.1 micron - poly: 0.13 micron Local oxide: 0.4 micron N+ S/D diffusion: 0.2 micron P+ S/D diffusion: 0.2 micron N-well: P-well: 2.5 microns (approx.) 2.0 microns (approx.)

15 INDEX TO FIGURES ASSEMBLY Figures 1-2 DIE LAYOUT AND IDENTIFICATION Figures 3-6 PHYSICAL DIE STRUCTURES Figures 7-39 REDUNDANCY FUSES Figures COLOR DRAWING OF DIE STRUCTURE Figure 26 SRAM MEMORY CELL STRUCTURES Figures CIRCUIT LAYOUT AND I/O Figure ii -

16 Figure 1. Package photographs of the Analog Devices ADSP KS-160 SHARC Digital Signal Processor. Mag. 2.5x.

17 PIN 1 top Figure 2. X-ray view of the package. Mag. 3x.

18 Figure 3. Portion of the Analog Devices ADSP KS-160 die. Mag. 26x.

19 Figure 3a. Portion of the Analog Devices ADSP KS-160 die. Mag. 26x.

20 Figure 3b. Portion of the Analog Devices ADSP KS-160 die. Mag. 26x.

21 Figure 3c. Remaining portion of the Analog Devices ADSP KS-160 die. Mag. 26x.

22 Figure 4. Optical views of die markings. Mag. 500x.

23 Figure 5. Optical views of die corners. Mag. 80x.

24 METAL 2 SLOT Figure 6. Optical views illustrating a slotted bus line and mask revision numbers. Mag. 400x.

25 EDGE OF PASSIVATION SUBSTRATE Mag. 1200x EDGE OF PASSIVATION METAL 2 METAL 1 N+ Mag. 6400x Figure 7. SEM section views of the die edge seal.

26 PASSIVATION 1 PASSIVATION 2 METAL 2 METAL 1 W PLUG LOCOS POLY 1 GATE N+ S/D PASSIVATION 1 PASSIVATION 2 SOG METAL 2 METAL 1 W PLUG LOCOS N+ S/D POLY 1 GATE Figure 8. SEM section views illustrating general structure. Mag. 13,000x.

27 Mag. 4800x Mag. 9600x Figure 9. SEM views illustrating final passivation. 60.

28 PASSIVATION 2 PASSIVATION 1 METAL 2 INTERLEVEL DIELECTRIC METAL 1 Mag. 26,000x TIN CAP ALUMINUM 2 TiN BARRIER Mag. 52,000x Figure 10. SEM section views illustrating metal 2 line profiles.

29 Mag. 3250x METAL 2 Mag. 6500x VIAS Mag. 6500x METAL 2 Figure 11. Topological SEM views of metal 2 patterning. 0.

30 METAL 2 Mag. 12,400x TiN CAP ALUMINUM 2 Mag. 26,000x TiN BARRIER TiN BARRIER W PLUG Mag. 40,000x Figure 12. Perspective SEM views of metal 2 step coverage, barrier, and plug. 60.

31 PASSIVATION 2 SOG METAL 2 W PLUG Mag. 13,000x METAL 1 LOCOS POLY 1 METAL 2 INTERLEVEL DIELECTRIC W PLUG Mag. 26,000x METAL 1 METAL 2 W PLUG INTERLEVEL DIELECTRIC Mag. 26,000x SOG METAL 1 Figure 13. SEM section views of typical vias.

32 METAL 2 INTERLEVEL DIELECTRIC METAL 1 Mag. 26,000x TiN CAP ALUMINUM 1 TiN BARRIER Mag. 52,000x Figure 14. SEM section views of metal 1 line profiles.

33 CONTACT METAL 1 POLY METAL 1 VIA METAL 1 Figure 15. Topological SEM views of metal 1 patterning. Mag. 6500x, 0.

34 METAL 1 Mag. 6500x Mag. 10,000x TiN CAP ALUMINUM 1 Mag. 30,000x TiN BARRIER Figure 16. Perspective SEM views of metal 1 step coverage. 60.

35 TiN BARRIER Mag. 10,000x Si TiN BARRIER W PLUG Mag. 40,000x Figure 17. Perspective SEM views of metal 1 barrier and plugs. 60.

36 METAL 1 W PLUG POLY 1 LOCOS METAL 1 W PLUG Ti ADHESION LAYER LOCOS N+ METAL 1 W PLUG LOCOS P+ Figure 18. SEM section views illustrating typical metal 1 contacts. Mag. 26,000x.

37 Mag. 3200x Mag. 3200x POLY N+ P+ Mag. 6500x Figure 19. Topological SEM views of poly 1 patterning. 0.

38 POLY 1 Mag. 9000x POLY 1 GATE LOCOS DIFFUSION Mag. 40,000x Figure 20. Perspective SEM views of poly 1 coverage. 60.

39 PRE-METAL GLASS POLY 1 GATE N-channel N+ S/D REFLOW GLASS POLY 1 GATE P-channel P+ S/D SIDEWALL SPACER W SILICIDE POLY 1 glass etch GATE OXIDE Figure 21. SEM section views of typical transistors. Mag. 52,000x.

40 DENSIFIED OXIDE POLY 1 LOCOS GATE OXIDE Figure 22. SEM section view of typical birdsbeak. Mag. 52,000x. Mag. 800x P-WELL N- SUBSTRATE METAL 1 Mag. 6500x LOCOS P+ N+ P-WELL N- SUBSTRATE Figure 23. Section views illustrating well structure.

41 Mag. 800x BLOWN FUSE Mag. 800x INTACT FUSE LASER BLOWN FUSE Mag. 1600x Figure 24. Optical and SEM views of typical fuses.

42 PASSIVATION Mag. 4800x, 60 CUTOUT CUTOUT Mag. 6500x POLY 1 FUSE PASSIVATION METAL 2 POLY 2 METAL 1 Mag. 13,000x LOCOS POLY 1 FUSE Figure 25. Perspective and cross-section SEM views of typical fuses.

43 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, METAL 1 W PLUG NITRIDE PASSIVATION METAL 2 INTERLEVEL DIELECTRIC PRE-METAL GLASS GATE OXIDE N+ S/D P-WELL N SUBSTRATE GLASS PASSIVATION W SILICIDE POLY 1 SOG LOCAL OXIDE Orange = Nitride, Blue = Metal, Yellow = Oxide, Green = Poly, Red = Diffusion, and Gray = Substrate,,,,,,, P+ S/D Figure 26. Color cross section drawing illustrating device structure. DENSIFIED OXIDE N-WELL,,,,,,,,,,,, Analog Devices ADSP KS-160

44 metal 2 metal 1 poly Figure 27. Perspective SEM views of the SRAM cell array. Mag. 5000x, 60.

45 GND BIT BIT metal 2 PIGGYBACK WORD LINE GND metal 1 WORD GND BIT BIT poly Figure 28. Perspective SEM views of the SRAM cell array. Mag. 10,000x, 60.

46 POLY 2 RESISTOR INTERLEVEL CONTACT POLY 1 POLY 1 WORD LINE SELECT GATE POLY 2 POLY 1 Figure 29. Detailed SEM views of the SRAM cell structures (delayered). Mag. 42,000x, 60.

47 GND metal 2 BIT BIT PIGGYBACK WORD LINE GND metal 1 WORD LINE poly Figure 30. Topological SEM views of the SRAM cell array. Mag. 3200x, 0.

48 GND BIT BIT metal 2 PIGGYBACK WORD LINE GND BIT BIT metal 1 Figure 31. Detailed topological SEM views of an SRAM cell. Mag. 13,000x, 0.

49 4 GND V DD BIT 1 R1 3 BIT 2 R2 GND unlayered WORD R1 R2 BIT 1 2 BIT 3 4 Figure 32. Detailed topological SEM view and schematic of an SRAM cell. Mag. 13,000x, 0.

50 METAL 2 BIT LINE Mag. 13,000x METAL 1 LINK POLY 1 STORAGE GATE N+ S/D METAL 2 BIT LINE W PLUG METAL 1 LINK Mag. 20,000x POLY 2 W PLUG METAL 1 LINK POLY 1 SELECT GATE W PLUG Mag. 26,000x N+ S/D Figure 33. SEM section views of an SRAM cell (parallel to bit line).

51 POLY 2 PULL-UP RESISTOR POLY 1 STORAGE GATE Mag. 35,000x LOCOS GATE OXIDE POLY 2 POLY 1 Mag. 52,000x N+ S/D POLY 1 SELECT GATE Mag. 52,000x N+ S/D GATE OXIDE Figure 34. SEM section views of SRAM cell details (parallel to bit line).

52 METAL 2 BIT LINE BIT LINE CONTACT POLY 1 WORD / SELECT LINE Mag. 13,000x POLY 1 WORD / SELECT LINE LOCOS GATE OXIDE Mag. 26,000x Figure 35. SEM section views of the SRAM cell array (perpendicular to bit line).

53 intact unlayered Figure 36. Optical views of typical I/O circuitry. Mag. 400x.

54 Au EDGE OF PASSIVATION Mag. 3200x Au METAL 1 LOCOS POLY 1 Mag. 13,000x Figure 37. SEM section views illustrating wirebond interface.

55 SOG METAL 2 METAL 1 P+ S/D POLY 1 GATE Mag. 13,000x SOG METAL 1 POLY 1 GATE P+ S/D Mag. 26,000x Figure 38. SEM section views of P-channel I/O circuitry.

56 N- channel P-channel Figure 39. SEM section views illustrating guardbands at the edge of the I/O circuitry. Mag. 6500x.

Rockwell R RF to IF Down Converter

Rockwell R RF to IF Down Converter Construction Analysis Rockwell R6732-13 RF to IF Down Converter Report Number: SCA 9709-552 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780

More information

Lattice isplsi1032e CPLD

Lattice isplsi1032e CPLD Construction Analysis Lattice isplsi1032e CPLD Report Number: SCA 9612-522 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780 Fax: 602-948-1925

More information

Dallas Semicoductor DS80C320 Microcontroller

Dallas Semicoductor DS80C320 Microcontroller Construction Analysis Dallas Semicoductor DS80C320 Microcontroller Report Number: SCA 9702-525 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone:

More information

Hitachi A 64Mbit (8Mb x 8) Dynamic RAM

Hitachi A 64Mbit (8Mb x 8) Dynamic RAM Construction Analysis Hitachi 5165805A 64Mbit (8Mb x 8) Dynamic RAM Report Number: SCA 9712-565 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone:

More information

SGS-Thomson M17C1001 1Mb UVEPROM

SGS-Thomson M17C1001 1Mb UVEPROM Construction Analysis SGS-Thomson M17C1001 1Mb UVEPROM Report Number: SCA 9612-518 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780

More information

Intel Pentium Processor W/MMX

Intel Pentium Processor W/MMX Construction Analysis Intel Pentium Processor W/MMX Report Number: SCA 9706-540 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780 Fax:

More information

Motorola PC603R Microprocessor

Motorola PC603R Microprocessor Construction Analysis Motorola PC603R Microprocessor Report Number: SCA 9709-551 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax:

More information

National Semiconductor LM2672 Simple Switcher Voltage Regulator

National Semiconductor LM2672 Simple Switcher Voltage Regulator Construction Analysis National Semiconductor LM2672 Simple Switcher Voltage Regulator Report Number: SCA 9712-570 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale,

More information

Lecture 030 Integrated Circuit Technology - I (5/8/03) Page 030-1

Lecture 030 Integrated Circuit Technology - I (5/8/03) Page 030-1 Lecture 030 Integrated Circuit Technology - I (5/8/03) Page 030-1 LECTURE 030 INTEGRATED CIRCUIT TECHNOLOGY - I (References [7,8]) Objective The objective of this presentation is: 1.) Illustrate integrated

More information

CMOS Manufacturing Process

CMOS Manufacturing Process CMOS Manufacturing Process CMOS Process A Modern CMOS Process gate-oxide TiSi 2 AlCu Tungsten SiO 2 n+ p-well p-epi poly n-well p+ SiO 2 p+ Dual-Well Trench-Isolated CMOS Process Circuit Under Design V

More information

Manufacturing Process

Manufacturing Process Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Manufacturing Process July 30, 2002 1 CMOS Process 2 A Modern CMOS Process gate-oxide TiSi 2 AlCu Tungsten

More information

CMOS FABRICATION. n WELL PROCESS

CMOS FABRICATION. n WELL PROCESS CMOS FABRICATION n WELL PROCESS Step 1: Si Substrate Start with p- type substrate p substrate Step 2: Oxidation Exposing to high-purity oxygen and hydrogen at approx. 1000 o C in oxidation furnace SiO

More information

Lecture 200 BiCMOS Technology (12/12/01) Page 200-1

Lecture 200 BiCMOS Technology (12/12/01) Page 200-1 Lecture 200 BiCMOS Technology (12/12/01) Page 200-1 LECTURE 200 BICMOS TECHNOLOGY (READING: Text-Sec. 2.11) INTRODUCTION Objective Illustrate BiCMOS technology Outline Introduction Physical process illustration

More information

EE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects

EE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects EE 330 Lecture 9 IC Fabrication Technology Part II -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects Review from Last Time Etching Dry etch (anisotropic) SiO

More information

EE 560 FABRICATION OF MOS CIRCUITS. Kenneth R. Laker, University of Pennsylvania

EE 560 FABRICATION OF MOS CIRCUITS. Kenneth R. Laker, University of Pennsylvania 1 EE 560 FABRICATION OF MOS CIRCUITS 2 CMOS CHIP MANUFACTRING STEPS Substrate Wafer Wafer Fabrication (diffusion, oxidation, photomasking, ion implantation, thin film deposition, etc.) Finished Wafer Wafer

More information

Silicon Wafer Processing PAKAGING AND TEST

Silicon Wafer Processing PAKAGING AND TEST Silicon Wafer Processing PAKAGING AND TEST Parametrical test using test structures regularly distributed in the wafer Wafer die test marking defective dies dies separation die fixing (not marked as defective)

More information

EE 434 Lecture 9. IC Fabrication Technology

EE 434 Lecture 9. IC Fabrication Technology EE 434 Lecture 9 IC Fabrication Technology Quiz 7 The layout of a film resistor with electrodes A and B is shown. If the sheet resistance of the film is 40 /, determine the resistance between nodes A and

More information

Figure 2.3 (cont., p. 60) (e) Block diagram of Pentium 4 processor with 42 million transistors (2000). [Courtesy Intel Corporation.

Figure 2.3 (cont., p. 60) (e) Block diagram of Pentium 4 processor with 42 million transistors (2000). [Courtesy Intel Corporation. Figure 2.1 (p. 58) Basic fabrication steps in the silicon planar process: (a) oxide formation, (b) selective oxide removal, (c) deposition of dopant atoms on wafer, (d) diffusion of dopant atoms into exposed

More information

1 Thin-film applications to microelectronic technology

1 Thin-film applications to microelectronic technology 1 Thin-film applications to microelectronic technology 1.1 Introduction Layered thin-film structures are used in microelectronic, opto-electronic, flat panel display, and electronic packaging technologies.

More information

Fabrication and Layout

Fabrication and Layout Fabrication and Layout Kenneth Yun UC San Diego Adapted from EE271 notes, Stanford University Overview Semiconductor properties How chips are made Design rules for layout Reading Fabrication: W&E 3.1,

More information

Cost of Integrated Circuits

Cost of Integrated Circuits Cost of IC Design 1 Cost of Integrated Circuits NRE (Non-Recurrent Engineering) costs fixed design time and effort, mask generation independent of sales volume / number of products one-time cost factor

More information

FABRICATION of MOSFETs

FABRICATION of MOSFETs FABRICATION of MOSFETs CMOS fabrication sequence -p-type silicon substrate wafer -creation of n-well regions for pmos transistors, -impurity implantation into the substrate. -thick oxide is grown in the

More information

Semiconductor Manufacturing Technology. IC Fabrication Process Overview

Semiconductor Manufacturing Technology. IC Fabrication Process Overview Semiconductor Manufacturing Technology Michael Quirk & Julian Serda October 00 by Prentice Hall Chapter 9 IC Fabrication Process Overview /4 Objectives After studying the material in this chapter, you

More information

Fabrication and Layout

Fabrication and Layout ECEN454 Digital Integrated Circuit Design Fabrication and Layout ECEN 454 3.1 A Glimpse at MOS Device Polysilicon Aluminum ECEN 475 4.2 1 Material Classification Insulators Glass, diamond, silicon oxide

More information

Improvement of Laser Fuse Processing of Fine Pitch Link Structures for Advanced Memory Designs

Improvement of Laser Fuse Processing of Fine Pitch Link Structures for Advanced Memory Designs Improvement of Laser Fuse Processing of Fine Pitch Link Structures for Advanced Memory Designs Joohan Lee, Joseph J. Griffiths, and James Cordingley GSI Group Inc. 60 Fordham Rd. Wilmington, MA 01887 jlee@gsig.com

More information

VLSI INTRODUCTION P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT

VLSI INTRODUCTION P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT VLSI INTRODUCTION P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents UNIT I INTRODUCTION: Introduction to IC Technology MOS, PMOS, NMOS, CMOS & BiCMOS technologies. BASIC ELECTRICAL PROPERTIES : Basic Electrical

More information

TSV Processing and Wafer Stacking. Kathy Cook and Maggie Zoberbier, 3D Business Development

TSV Processing and Wafer Stacking. Kathy Cook and Maggie Zoberbier, 3D Business Development TSV Processing and Wafer Stacking Kathy Cook and Maggie Zoberbier, 3D Business Development Outline Why 3D Integration? TSV Process Variations Lithography Process Results Stacking Technology Wafer Bonding

More information

VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras

VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras Lecture - 33 Problems in LOCOS + Trench Isolation and Selective Epitaxy So, we are discussing

More information

Chapter 3 Silicon Device Fabrication Technology

Chapter 3 Silicon Device Fabrication Technology Chapter 3 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world) are manufactured every year. VLSI (Very Large Scale Integration) ULSI (Ultra Large Scale

More information

Lecture 22: Integrated circuit fabrication

Lecture 22: Integrated circuit fabrication Lecture 22: Integrated circuit fabrication Contents 1 Introduction 1 2 Layering 4 3 Patterning 7 4 Doping 8 4.1 Thermal diffusion......................... 10 4.2 Ion implantation.........................

More information

Lecture 2. Fabrication and Layout

Lecture 2. Fabrication and Layout Lecture 2 Fabrication and Layout Mark Horowitz Modified by Azita Emami Computer Systems Laboratory Stanford University azita@stanford.edu 1 Overview Reading W&E 3.1(scan), 3.2.1, 3.3.1 - Fabrication W&E

More information

Technology. Semiconductor Manufacturing. Hong Xiao INTRODUCTION TO SECOND EDITION SPIE PRESS

Technology. Semiconductor Manufacturing. Hong Xiao INTRODUCTION TO SECOND EDITION SPIE PRESS INTRODUCTION TO Semiconductor Manufacturing Technology SECOND EDITION Hong Xiao TECHNISCHE INFORMATIONSBiBUOTHEK UNIVERSITATSBIBLIOTHEK HANNOVER SPIE PRESS Bellingham,Washington USA Contents Preface to

More information

Isolation Technology. Dr. Lynn Fuller

Isolation Technology. Dr. Lynn Fuller ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Isolation Technology Dr. Lynn Fuller Motorola Professor 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Fax (585) 475-5041

More information

10 Manor Parkway, Suite C Salem, New Hampshire

10 Manor Parkway, Suite C Salem, New Hampshire Micro-Precision Technologies (MPT) is an independent manufacturer of hybrid integrated circuits, multichip modules, and high-precision thick film substrates for the military, medical, avionics, optoelectronics,

More information

KGC SCIENTIFIC Making of a Chip

KGC SCIENTIFIC  Making of a Chip KGC SCIENTIFIC www.kgcscientific.com Making of a Chip FROM THE SAND TO THE PACKAGE, A DIAGRAM TO UNDERSTAND HOW CPU IS MADE? Sand CPU CHAIN ANALYSIS OF SEMICONDUCTOR Material for manufacturing process

More information

HOMEWORK 4 and 5. March 15, Homework is due on Monday March 30, 2009 in Class. Answer the following questions from the Course Textbook:

HOMEWORK 4 and 5. March 15, Homework is due on Monday March 30, 2009 in Class. Answer the following questions from the Course Textbook: HOMEWORK 4 and 5 March 15, 2009 Homework is due on Monday March 30, 2009 in Class. Chapter 7 Answer the following questions from the Course Textbook: 7.2, 7.3, 7.4, 7.5, 7.6*, 7.7, 7.9*, 7.10*, 7.16, 7.17*,

More information

Nonplanar Metallization. Planar Metallization. Professor N Cheung, U.C. Berkeley

Nonplanar Metallization. Planar Metallization. Professor N Cheung, U.C. Berkeley Nonplanar Metallization Planar Metallization Passivation Metal 5 (copper) Metal 3 (copper) Interlevel dielectric (ILD) Via (tungsten) Metal 1 (copper) Tungsten Plug to Si Silicon Caps and Plugs oxide oxide

More information

VLSI Systems and Computer Architecture Lab

VLSI Systems and Computer Architecture Lab ΚΥΚΛΩΜΑΤΑ VLSI Πανεπιστήμιο Ιωαννίνων CMOS Technology Τμήμα Μηχανικών Η/Υ και Πληροφορικής 1 From the book: An Introduction ti to VLSI Process By: W. Maly ΚΥΚΛΩΜΑΤΑ VLSI Διάρθρωση 1. N well CMOS 2. Active

More information

Challenges and Future Directions of Laser Fuse Processing in Memory Repair

Challenges and Future Directions of Laser Fuse Processing in Memory Repair Challenges and Future Directions of Laser Fuse Processing in Memory Repair Bo Gu, * T. Coughlin, B. Maxwell, J. Griffiths, J. Lee, J. Cordingley, S. Johnson, E. Karagiannis, J. Ehrmann GSI Lumonics, Inc.

More information

Failure Modes in Wire bonded and Flip Chip Packages

Failure Modes in Wire bonded and Flip Chip Packages Failure Modes in Wire bonded and Flip Chip Packages Mumtaz Y. Bora Peregrine Semiconductor San Diego, Ca. 92121 mbora@psemi.com Abstract The growth of portable and wireless products is driving the miniaturization

More information

IMPACT OF MICROVIA-IN-PAD DESIGN ON VOID FORMATION

IMPACT OF MICROVIA-IN-PAD DESIGN ON VOID FORMATION IMPACT OF MICROVIA-IN-PAD DESIGN ON VOID FORMATION Frank Grano, Felix Bruno Huntsville, AL Dana Korf, Eamon O Keeffe San Jose, CA Cheryl Kelley Salem, NH Joint Paper by Sanmina-SCI Corporation EMS, GTS

More information

Is Now Part of To learn more about ON Semiconductor, please visit our website at

Is Now Part of To learn more about ON Semiconductor, please visit our website at Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC

More information

Customizing Processes for Hermetic Assembly Of Devices Designed for Plastic Packages (1 of 3)

Customizing Processes for Hermetic Assembly Of Devices Designed for Plastic Packages (1 of 3) Customizing Processes for Hermetic Assembly Of Devices Designed for Plastic Packages (1 of 3) Charlie C. Megia Golden Altos Corporation 402 South Hillview Drive, Milpitas, CA 95035 cmegia@goldenaltos.com

More information

Manufacturer Part Number. Module 2: CMOS FEOL Analysis

Manufacturer Part Number. Module 2: CMOS FEOL Analysis Manufacturer Part Number description Module 2: CMOS FEOL Analysis Manufacturer Device # 2 Some of the information is this report may be covered by patents, mask and/or copyright protection. This report

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 9/13/2007 Fabrication Technology Lecture 1 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world)

More information

CMOS Manufacturing process. Circuit designer. Design rule set. Process engineer. Set of optical masks. Fabrication process.

CMOS Manufacturing process. Circuit designer. Design rule set. Process engineer. Set of optical masks. Fabrication process. CMOS Manufacturing process Circuit design Set of optical masks Fabrication process Circuit designer Design rule set Process engineer All material: Chap. 2 of J. Rabaey, A. Chandrakasan, B. Nikolic, Digital

More information

Process Integration. NMOS Generic NMOS Process Flow. CMOS - The MOSIS Process Flow

Process Integration. NMOS Generic NMOS Process Flow. CMOS - The MOSIS Process Flow Process Integration Self-aligned Techniques LOCOS- self-aligned channel stop Self-aligned Source/Drain Lightly Doped Drain (LDD) Self-aligned silicide (SALICIDE) Self-aligned oxide gap MEMS Release Techniques

More information

Innovative MID Plating Solutions

Innovative MID Plating Solutions Innovative MID Plating Solutions High Reliability Wire Bond Technique for MIDs Jordan Kologe MacDermid Electronics Solutions jkologe@macdermid.com 1 MacDermid: Specialty Chemical Solutions Over 2000 Worldwide

More information

6.777J/2.732J Design and Fabrication of Microelectromechanical Devices Spring Term Solution to Problem Set 2 (16 pts)

6.777J/2.732J Design and Fabrication of Microelectromechanical Devices Spring Term Solution to Problem Set 2 (16 pts) 6.777J/2.732J Design and Fabrication of Microelectromechanical Devices Spring Term 2007 By Brian Taff (Adapted from work by Feras Eid) Solution to Problem Set 2 (16 pts) Issued: Lecture 4 Due: Lecture

More information

Lead-Free Solder Bump Technologies for Flip-Chip Packaging Applications

Lead-Free Solder Bump Technologies for Flip-Chip Packaging Applications Lead-Free Solder Bump Technologies for Flip-Chip Packaging Applications Zaheed S. Karim 1 and Jim Martin 2 1 Advanced Interconnect Technology Ltd. 1901 Sunley Centre, 9 Wing Yin Street, Tsuen Wan, Hong

More information

Lecture 19 Microfabrication 4/1/03 Prof. Andy Neureuther

Lecture 19 Microfabrication 4/1/03 Prof. Andy Neureuther EECS 40 Spring 2003 Lecture 19 Microfabrication 4/1/03 Prof. ndy Neureuther How are Integrated Circuits made? Silicon wafers Oxide formation by growth or deposition Other films Pattern transfer by lithography

More information

Semiconductor Technology

Semiconductor Technology Semiconductor Technology von A bis Z Metallization www.halbleiter.org Contents Contents List of Figures List of Tables II III 1 Metallization 1 1.1 Requirements on metallization........................

More information

ELEC 3908, Physical Electronics, Lecture 4. Basic Integrated Circuit Processing

ELEC 3908, Physical Electronics, Lecture 4. Basic Integrated Circuit Processing ELEC 3908, Physical Electronics, Lecture 4 Basic Integrated Circuit Processing Lecture Outline Details of the physical structure of devices will be very important in developing models for electrical behavior

More information

Metallization. Typical current density ~10 5 A/cm 2 Wires introduce parasitic resistance and capacitance

Metallization. Typical current density ~10 5 A/cm 2 Wires introduce parasitic resistance and capacitance Metallization Interconnects Typical current density ~10 5 A/cm 2 Wires introduce parasitic resistance and capacitance RC time delay Inter-Metal Dielectric -Prefer low dielectric constant to reduce capacitance

More information

2006 UPDATE METROLOGY

2006 UPDATE METROLOGY INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS METROLOGY THE ITRS DEVED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS PERTAINING TO INDIVIDUAL PRODUCTS

More information

Interconnects OUTLINE

Interconnects OUTLINE Interconnects 1 Interconnects OUTLINE 1. Overview of Metallization 2. Introduction to Deposition Methods 3. Interconnect Technology 4. Contact Technology 5. Refractory Metals and their Silicides Reading:

More information

Interconnects. Outline. Interconnect scaling issues Aluminum technology Copper technology. Properties of Interconnect Materials

Interconnects. Outline. Interconnect scaling issues Aluminum technology Copper technology. Properties of Interconnect Materials Interconnects Outline Interconnect scaling issues Aluminum technology Copper technology 1 Properties of Interconnect Materials Metals Silicides Barriers Material Thin film Melting resistivity point ( C)

More information

14. Designing with FineLine BGA Packages

14. Designing with FineLine BGA Packages 14. Designing with FineLine BGA Packages S51014-1.0 Chapter 14, Designing with FineLine BGA Packages, replaces AN 114: Designing with FineLine BGA Packages. Introduction As programmable logic devices (PLDs)

More information

Metallization. Typical current density ~105 A/cm2 Wires introduce parasitic resistance and capacitance

Metallization. Typical current density ~105 A/cm2 Wires introduce parasitic resistance and capacitance Metallization Interconnects Typical current density ~105 A/cm2 Wires introduce parasitic resistance and capacitance RC time delay Inter-Metal Dielectric -Prefer low dielectric constant to reduce capacitance

More information

EEC 118 Lecture #5: MOS Fabrication. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #5: MOS Fabrication. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 118 Lecture #5: MOS Fabrication Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 3 this week, report due next week HW 3 due this Friday at 4

More information

PROCESSING OF INTEGRATED CIRCUITS

PROCESSING OF INTEGRATED CIRCUITS PROCESSING OF INTEGRATED CIRCUITS Overview of IC Processing (Part I) Silicon Processing Lithography Layer Processes Use in IC Fabrication (Part II) Integrating the Fabrication Steps IC Packaging (Part

More information

Quality and Reliability Report

Quality and Reliability Report Quality and Reliability Report Product Qualification MASW-007921 2mm 8-Lead Plastic Package QTR-0148 M/A-COM Technology Solutions Inc. 100 Chelmsford Street Lowell, MA 01851 Tel: (978) 656-2500 Fax: (978)

More information

Wafer-level 3D integration technology

Wafer-level 3D integration technology Wafer-level 3D integration technology An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description

More information

Quality and Reliability Report

Quality and Reliability Report Quality and Reliability Report Product Qualification MAAM-008819 2mm 8-Lead PDFN Plastic Package QTR-0147 M/A-COM Technology Solutions Inc. 100 Chelmsford Street Lowell, MA 01851 Tel: (978) 656-2500 Fax:

More information

FABRICATION ENGINEERING MICRO- NANOSCALE ATTHE AND. Fourth Edition STEPHEN A. CAMPBELL. of Minnesota. University OXFORD UNIVERSITY PRESS

FABRICATION ENGINEERING MICRO- NANOSCALE ATTHE AND. Fourth Edition STEPHEN A. CAMPBELL. of Minnesota. University OXFORD UNIVERSITY PRESS AND FABRICATION ENGINEERING ATTHE MICRO- NANOSCALE Fourth Edition STEPHEN A. CAMPBELL University of Minnesota New York Oxford OXFORD UNIVERSITY PRESS CONTENTS Preface xiii prrt i OVERVIEW AND MATERIALS

More information

Fairchild Semiconductor Application Note January 2001 Revised September Using BGA Packages

Fairchild Semiconductor Application Note January 2001 Revised September Using BGA Packages Introduction AN-5026 Demanding space and weight requirements of personal computing and portable electronic equipment has led to many innovations in IC packaging. Combining the right interface and logic

More information

TMS320C6000 BGA Manufacturing Considerations

TMS320C6000 BGA Manufacturing Considerations TMS320C6000 BGA Manufacturing Considerations David Bell C6000 Applications Team Abstract When designing with a high-density BGA package, it is important to be aware of different techniques that aid in

More information

2.5D and 3D Semiconductor Package Technology: Evolution and Innovation

2.5D and 3D Semiconductor Package Technology: Evolution and Innovation 2.5D and 3D Semiconductor Package Technology: Evolution and Innovation Vern Solberg Solberg Technical Consulting Saratoga, California USA Abstract The electronics industry is experiencing a renaissance

More information

A modular process for integrating thick polysilicon MEMS devices with sub-micron CMOS

A modular process for integrating thick polysilicon MEMS devices with sub-micron CMOS A modular process for integrating thick polysilicon MEMS devices with sub-micron CMOS John Yasaitis a, Michael Judy a, Tim Brosnihan a, Peter Garone a, Nikolay Pokrovskiy a, Debbie Sniderman a,scottlimb

More information

Design for Flip-Chip and Chip-Size Package Technology

Design for Flip-Chip and Chip-Size Package Technology Design for Flip-Chip and Chip-Size Package Technology Vern Solberg Solberg Technology Consulting Madison, Wisconsin Abstract As new generations of electronic products emerge they often surpass the capability

More information

MOS Front-End. Field effect transistor

MOS Front-End. Field effect transistor MOS Front-End Back-end Transistor Contact Front-end p-well STI n-well Front-end-of-line includes substrate, isolation, wells, transistor, silicide Field effect transistor MOSFET: Metal-Oxide-Semiconductor

More information

Semiconductor Manufacturing Technology. Semiconductor Manufacturing Technology

Semiconductor Manufacturing Technology. Semiconductor Manufacturing Technology Semiconductor Manufacturing Technology Michael Quirk & Julian Serda October 2001 by Prentice Hall Chapter 11 Deposition Film Layers for an MSI Era NMOS Transistor Topside Nitride Pre-metal oxide Sidewall

More information

EE 330 Fall Ruden Michael. Al Kaabi Humaid. Archer Tyler. Hafeez Mustafa. Mullen Taylor. Thedens Peter. Cao Khoi.

EE 330 Fall Ruden Michael. Al Kaabi Humaid. Archer Tyler. Hafeez Mustafa. Mullen Taylor. Thedens Peter. Cao Khoi. 1 2 5 6 3 4 8 7 1 2 3 4 5 6 ROW EE 330 Fall 2017 9 10 Al Kaabi Humaid Alegria Francisco Allison Trenton Alva Caroline Archer Tyler Bahashwan Abdullah Betke Jarrett Chun Junho Davidson Caleb Faronbi Matthew

More information

System in Package: Identified Technology Needs from the 2004 inemi Roadmap

System in Package: Identified Technology Needs from the 2004 inemi Roadmap System in Package: Identified Technology Needs from the 2004 inemi Roadmap James Mark Bird Amkor Technology Inc System in package (SiP) technology has grown significantly in the past several years. It

More information

Silver Diffusion Bonding and Layer Transfer of Lithium Niobate to Silicon

Silver Diffusion Bonding and Layer Transfer of Lithium Niobate to Silicon Chapter 5 Silver Diffusion Bonding and Layer Transfer of Lithium Niobate to Silicon 5.1 Introduction In this chapter, we discuss a method of metallic bonding between two deposited silver layers. A diffusion

More information

Nano-Processing for High Voltage and High Power Devices. J. Parsey March 21, 2013

Nano-Processing for High Voltage and High Power Devices. J. Parsey March 21, 2013 Nano-Processing for High Voltage and High Power Devices J. Parsey March 21, 2013 Outline Background concepts Two nano ideas: New high voltage, high power FET device designs Application of nano-particles

More information

MIL-STD-883G METHOD VISUAL INSPECTION OF PASSIVE ELEMENTS

MIL-STD-883G METHOD VISUAL INSPECTION OF PASSIVE ELEMENTS VISUAL INSPECTION OF PASSIVE ELEMENTS 1. PURPOSE. The purpose of this test is to inspect passive elements used for microelectronic applications, including RF/microwave, for the visual defects described

More information

Modeling of Local Oxidation Processes

Modeling of Local Oxidation Processes Introduction Isolation Processes in the VLSI Technology Main Aspects of LOCOS simulation Athena Oxidation Models Several Examples of LOCOS structures Calibration of LOCOS effects using VWF Field Oxide

More information

Selection and Application of Board Level Underfill Materials

Selection and Application of Board Level Underfill Materials Selection and Application of Board Level Underfill Materials Developed by the Underfill Materials Design, Selection and Process Task Group (5-24f) of the Assembly and Joining Committee (5-20) of IPC Supersedes:

More information

Chips Face-up Panelization Approach For Fan-out Packaging

Chips Face-up Panelization Approach For Fan-out Packaging Chips Face-up Panelization Approach For Fan-out Packaging Oct. 15, 2015 B. Rogers, D. Sanchez, C. Bishop, C. Sandstrom, C. Scanlan, TOlson T. REV A Background on FOWLP Fan-Out Wafer Level Packaging o Chips

More information

Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate

Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate Development of Sidewalls Passivating Films Sidewalls get inert species deposited on them with plasma etch Creates

More information

Ultra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes

Ultra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes Ultra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes Andrew Strandjord, Thorsten Teutsch, and Jing Li Pac Tech USA Packaging Technologies, Inc. Santa Clara, CA USA 95050 Thomas Oppert, and

More information

EE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009

EE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009 Suggested Reading EE40 Lec 22 IC Fabrication Technology Prof. Nathan Cheung 11/19/2009 300mm Fab Tour http://www-03.ibm.com/technology/manufacturing/technology_tour_300mm_foundry.html Overview of IC Technology

More information

Surface micromachining and Process flow part 1

Surface micromachining and Process flow part 1 Surface micromachining and Process flow part 1 Identify the basic steps of a generic surface micromachining process Identify the critical requirements needed to create a MEMS using surface micromachining

More information

Lecture 7 CMOS MEMS. CMOS MEMS Processes. CMOS MEMS Processes. Why CMOS-MEMS? Agenda: CMOS MEMS: Fabrication. MEMS structures can be made

Lecture 7 CMOS MEMS. CMOS MEMS Processes. CMOS MEMS Processes. Why CMOS-MEMS? Agenda: CMOS MEMS: Fabrication. MEMS structures can be made EEL6935 Advanced MEMS (Spring 2005) Instructor: Dr. Huikai Xie CMOS MEMS Agenda: Lecture 7 CMOS MEMS: Fabrication Pre-CMOS Intra-CMOS Post-CMOS Deposition Etching Why CMOS-MEMS? Smart on-chip CMOS circuitry

More information

surface. As heat and ultrasonic energy soften the wire and pad metallization the bonding tool deforms the bonding wire against the bond pad and forms

surface. As heat and ultrasonic energy soften the wire and pad metallization the bonding tool deforms the bonding wire against the bond pad and forms EVALUATION OF WIRE BONDING PERFORMANCE, PROCESS CONDITIONS, AND METALLURGICAL INTEGRITY OF CHIP ON BOARD WIRE BONDS Daniel T. Rooney, Ph.D., DeePak Nager, David Geiger, and Dongkai Shanguan, Ph.D. Flextronics

More information

Challenges for Embedded Device Technologies for Package Level Integration

Challenges for Embedded Device Technologies for Package Level Integration Challenges for Embedded Device Technologies for Package Level Integration Kevin Cannon, Steve Riches Tribus-D Ltd Guangbin Dou, Andrew Holmes Imperial College London Embedded Die Technology IMAPS-UK/NMI

More information

Design and Assembly Process Implementation of 3D Components

Design and Assembly Process Implementation of 3D Components IPC-7091 Design and Assembly Process Implementation of 3D Components Developed by the 3-D Electronic Packages Subcommittee (B-11) of the Packaged Electronic Components Committee (B-10) of IPC Users of

More information

Freescale Semiconductor Tape Ball Grid Array (TBGA) Overview

Freescale Semiconductor Tape Ball Grid Array (TBGA) Overview Freescale Semiconductor Tape Ball Grid Array (TBGA) Overview Revision 0 2006 Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the

More information

Packaging Commercial CMOS Chips for Lab on a Chip Integration

Packaging Commercial CMOS Chips for Lab on a Chip Integration Supporting Information for Packaging Commercial CMOS Chips for Lab on a Chip Integration by Timir Datta-Chaudhuri, Pamela Abshire, and Elisabeth Smela Biocompatibility Although the supplier s instructions

More information

Ion Implantation Most modern devices doped using ion implanters Ionize gas sources (single +, 2+ or 3+ ionization) Accelerate dopant ions to very

Ion Implantation Most modern devices doped using ion implanters Ionize gas sources (single +, 2+ or 3+ ionization) Accelerate dopant ions to very Ion Implantation Most modern devices doped using ion implanters Ionize gas sources (single +, 2+ or 3+ ionization) Accelerate dopant ions to very high voltages (10-600 KeV) Use analyzer to selection charge/mass

More information

FOR OFFICIAL USE ONLY

FOR OFFICIAL USE ONLY REVISION RECORD REV DESCRIPTION DATE 0 INITIAL RELEASE 10/05/10 CAUTION: ELECTROSTATIC DISCHARGE SENSITIVE PART REVISION PAGE NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 INDEX REVISION 0 0 0 0 0 0 0 0 0 0

More information

IMPLEMENTATION OF A FULLY MOLDED FAN-OUT PACKAGING TECHNOLOGY

IMPLEMENTATION OF A FULLY MOLDED FAN-OUT PACKAGING TECHNOLOGY IMPLEMENTATION OF A FULLY MOLDED FAN-OUT PACKAGING TECHNOLOGY B. Rogers, C. Scanlan, and T. Olson Deca Technologies, Inc. Tempe, AZ USA boyd.rogers@decatechnologies.com ABSTRACT Fan-Out Wafer-Level Packaging

More information

Development of System in Package

Development of System in Package Development of System in Package In recent years, there has been a demand to offer increasingly enhanced performance for a SiP that implements downsized and lower-profile chips at lower cost. This article

More information

Historical Development. Babbage s second computer. Before the digital age

Historical Development. Babbage s second computer. Before the digital age Historical Development To fully appreciate the computers of today, it is helpful to understand how things got the way they are The evolution of computing machinery has taken place over several centuries

More information

PerformanceProfile. Initial Tests Demonstrate Improved Yield. Introduction

PerformanceProfile. Initial Tests Demonstrate Improved Yield. Introduction PerformanceProfile Replacing Hydroxyl-amine-based Chemistries with Semi-aqueous-based Cleaning Formulations Generates Improved Yields in Post-etch Metal and Oxide Residue Removal by: Mustapha, Nik Senior

More information

Close supply chain collaboration enables easy implementation of chip embedded power SiP

Close supply chain collaboration enables easy implementation of chip embedded power SiP Close supply chain collaboration enables easy implementation of chip embedded power SiP Gerald Weidinger, R&D Project Leader, AT&S AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Fabriksgasse13

More information

2015 EE410-LOCOS 0.5µm Poly CMOS Process Run Card Lot ID:

2015 EE410-LOCOS 0.5µm Poly CMOS Process Run Card Lot ID: STEP 0.00 - PHOTOMASK #0- ZERO LEVEL MARKS Starting materials is n-type silicon (5-10 ohm-cm). Add four test wafers labeled T1-T4. T1 and T2 will travel with the device wafers and get all of the processing

More information

Radiation Tolerant Isolation Technology

Radiation Tolerant Isolation Technology Radiation Tolerant Isolation Technology Background The following contains a brief description of isolation technologies used for radiation hardened integrated circuits. The technologies mentioned are junction

More information