I. INTRODUCTION. Horyeong Lee 1, Meng Li 1, Jungwoo Oh 2, and Hi-Deok Lee 1,* Schottky diode, effective Schottky barrier height, n- channel MOSFETs

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1 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.1, FEBRUARY, A Study of the Dependence of Effective Schottky Barrier Height in Ni Silicide/n-Si on the Thickness of the Antimony Interlayer for High Performance n-channel MOSFETs Horyeong Lee 1, Meng Li 1, Jungwoo Oh 2, and Hi-Deok Lee 1,* Abstract In this paper, the effective electron Schottky barrier height (Ф Bn ) of the Ni silicide/nsilicon (100) interface was studied in accordance with different thicknesses of the antimony (Sb) interlayer for high performance n-channel MOSFETs. The Sb interlayers, varying its thickness from 2 nm to 10 nm, were deposited by radio frequency (RF) sputtering on lightly doped n-type Si (100), followed by the in situ deposition of Ni/TiN (15/10 nm). It is found that the sample with a thicker Sb interlayer shows stronger ohmic characteristics than the control sample without the Sb interlayer. These results show that the effective Ф Bn is considerably lowered by the influence of the Sb interlayer. However, the current level difference between Schottky diodes fabricated with Sb/Ni/TiN (8/15/10 nm) and Sb/Ni/TiN (10/15/10 nm) structures is almost same. Therefore, considering the process time and cost, it can be said that the optimal thickness of the Sb interlayer is 8 nm. The effective Ф Bn of ev was achieved for the Schottky diode with Sb/Ni/TiN (8/15/10 nm) structure. Therefore, this technology is suitable for high performance n-channel MOSFETs. Index Terms Nckel silicide, antimony interlayer, Manuscript received Aug. 25, 2014; accepted Nov. 13, 2014 A part of this work was presented in Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Kanazawa in Japan, July Dep. Electronics Engineering, Chungnam National Univ., Daejeon, Korea. 2 Dep. School of Integrated Technology, Yonsei Univ., Incheon, Korea * hdlee@cnu.ac.kr, Tel : Schottky diode, effective Schottky barrier height, n- channel MOSFETs I. INTRODUCTION Over the last several decades, metal oxide semiconductor field effect transistors (MOSFETs) have been continuously scaled down to improve device performance and to reduce the device cost per unit wafer area. As the channel length of MOSFETs has been scaled down to sub-0.1 μm, the ultra-shallow source/drain (S/D) junction depth has been required to suppress short channel effects (SCEs) [1-3]. However, ultra-shallow S/D junction increases the sheet resistance (R sh ), which can degrade device performance [4]. To solve this problem, silicides have been used to reduce R sh in the S/D regions [5, 6]. Nickel silicide (NiSi) is one of the candidates, which has recently gained great attention. NiSi has a low resistivity (14-16 μω-cm) and consumes less silicon than other silicides like titanium silicide (TiSi 2 ) and cobalt silicide (CoSi 2 ) [7, 8]. Therefore, it is suitable in ultra-shallow S/D junctions. However, the relative contribution of contact resistance (R c ) to S/D series resistance (R series ) has significantly increased as devices have undergone extreme scaling [3, 9]. Thus, decreasing R c has become one of the issues for high performance MOSFETs. R c at the silicide/silicon (Si) interface has been reported to be closely related to the effective Schottky barrier height (Ф B ) [3]. For this reason, it is also important to reduce the effective Ф B at the silicide/si interface in S/D regions. In this paper, we describe a method to reduce the

2 42 HORYEONG LEE et al : A STUDY OF THE DEPENDENCE OF EFFECTIVE SCHOTTKY BARRIER HEIGHT IN NI SILICIDE/N-SI ON n-si wafer (100) TiN Ni Sb Cleaning ( HF:H 2 O (1:100) ) Thermal Oxidation ( 100 nm ) SiO 2 SiO 2 Patterning - Photolithography to form square-shaped patterns - Etching of SiO 2 ( BHF ) n-si (100) (a) Deposition of Metal Layers ( RF sputter ) - Ni/TiN ( 15/10 nm ) - Sb/Ni/TiN ( 2/15/10 nm ) - Sb/Ni/TiN ( 4/15/10 nm ) - Sb/Ni/TiN ( 6/15/10 nm ) - Sb/Ni/TiN ( 8/15/10 nm ) - Sb/Ni/TiN ( 10/15/10 nm ) Silicidation ( RTA : 400 o C, 60 sec ) Selective Wet Etching - H 2 SO 4 :H 2 O 2 (4:1) : 90 o C, 15 min Back-side Al Deposition ( RF sputter ) Fig. 1. Process flow of Schottky diode fabrication to analyze and extract effective Ф Bn. effective electron Schottky barrier height (Ф Bn ) at the NiSi/n-Si(100) interface using an antimony (Sb) interlayer. From the current-voltage (I-V) characteristics of the fabricated Schottky diode, the dependence of the effective Ф Bn on Sb interlayer thickness was analyzed. The activation energy measurement method was used to extract a very low effective Ф Bn. An effective Ф Bn reduction mechanism was investigated for Ni silicide formed on n-si with Sb segregation. II. EXPERIMENT To analyze effective Ф Bn, Schottky diodes were fabricated in the process flow summarized in Fig. 1. Lightly doped n-type Si (100) wafers with a resistivity of 8-28 Ω-cm were used for the experiment. 100 nm thick silicon oxide (SiO 2 ) was grown by thermal oxidation at 1000 o C for 2 hours after cleaning using diluted hydrofluoric solution to remove native oxide. To form square diode patterns, photolithography was followed by SiO 2 wet etching. A buffered HF (NH 4 F:HF=6:1) wet etching was used to remove 100 nm of thermal SiO 2. After patterning, Sb of various thicknesses (2, 4, 6, 8 and 10 nm) was deposited using radio frequency (RF) sputtering, followed by in situ deposition of Ni/TiN SiO 2 SiO 2 NiSi Segregated Sb n-si (100) (b) Al back side (100 nm) Fig. 2. (a) As-deposited layer structure before silicidation, (b) Expected layer structure after silicidation and selective wet etching, followed by aluminum (Al) deposition on the back side. (15/10 nm) (see Fig. 2(a)). Ni/TiN without the Sb interlayer was also deposited as the control sample. Titanium nitride (TiN) was used as a capping layer in this experiment. After silicidation by rapid thermal annealing (RTA) at 400 o C for 60 sec to form NiSi, a selective wet etching was carried out to remove the unreacted metal and TiN capping layer with a sulfuric acid solution (H 2 SO 4 :H 2 O 2 =4:1) at 90 o C for 15 min (see Fig. 2(b)). As a last process step, 100 nm thick aluminum (Al) film was deposited by RF sputtering to form the back side electrode. The I-V measurements were performed using an Agilent 4155C to analyze the Schottky diode I-V characteristics. To extract the very low effective Ф Bn, the activation energy measurement method was used. Field emission scanning electron microscopy (FE-SEM) and X-ray diffraction (XRD) were used to analyze how well the Ni silicide was formed. Secondary ion mass spectroscopy (SIMS) was carried out to examine the distribution of Sb after silicidation. III. RESULTS AND DISCUSSION Before fabricating the Schottky diodes, rapid thermal annealing (RTA) windows were plotted to find the best silicidation condition for all samples as shown in Fig. 3. To identify RTA windows, the Ni/TiN and Sb/Ni/TiN were deposited on lightly doped n-si by RF sputtering

3 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.1, FEBRUARY, (b) (a) [ Units : nm ] Ni/TiN(15/10) Sb/Ni/TiN(2/15/10) Sb/Ni/TiN(4/15/10) Sb/Ni/TiN(6/15/10) Sb/Ni/TiN(8/15/10) Sb/Ni/TiN(10/15/10) 100 nm 30 Ni/TiN(15/10nm) Sb/Ni/TiN(2/15/10nm) (c) (d) Sb/Ni/TiN(4/15/10nm) Sb/Ni/TiN(6/15/10nm) (e) (f) Sb/Ni/TiN(8/15/10nm) Sb/Ni/TiN(10/15/10nm) Fig. 4. FE-SEM cross-sectional images of Ni silicide (a) Ni/TiN, (b)-(f) Sb/Ni/TiN with s split of Sb thickness. Nickel Silicide (NiSi) (112) RTA 400 oc, 60 sec (301) like the Schottky diode samples. Then RTA for silicidation was carried out at oC for 60 sec, followed by selective wet etching with a sulfuric acid solution. For all fabricated test samples, Rsh was determined by a four-point probe measurement method and plotted as a function of silicidation temperature. The reference Ni/TiN (15/10 nm) structure maintained a low Rsh in throughout the silicidation temperature range. We can see similar characteristics in Sb/Ni/TiN structures with a 2 and 4 nm Sb interlayer. However, The Rsh of Sb/Ni/TiN structures with the 6, 8 and 10 nm Sb interlayer abruptly increased at 600oC. Because all samples maintained low Rsh at 400oC, Ni silicide was formed at 400oC for 60 sec to fabricate Schottky diodes. The morphological analysis of Ni silicide formed at a 400oC, 60 sec condition was performed using FE-SEM as shown in Fig. 4. All samples show good interface characteristics without agglomeration. From these results, we can speculate that Ni silicide is uniformly formed at this silicidation condition although the Sb interlayer exists at the Ni silicide/n-si interface. The resistivity of Ni mono-silicide (NiSi) is about 1520 μω-cm, while the resistivity of Ni di-silicide (NiSi2) is about 3 times higher than that of Ni mono-silicide [10, 11]. Therefore, it is important to form NiSi, not NiSi2. In Fig. 5, we can see that all XRD peaks correspond to the Ni mono-silicide phase. In other words, all Ni silicides formed by the Ni/TiN (15/10 nm) and Sb/Ni/TiN (8/15/10 nm) structures have the Ni mono-silicide phase. Although their intensities show a little difference, the (121) (103) Fig. 3. RTA window plots of Rsh as a function of silicidation temperature. (111) (hkl) As Dep. 300 o RTA Temperature [ C] (200) 0 Intensity (a. u.) Sheet Resistance [Ohm/Sq.] Ni/TiN (15/10 nm) Sb/Ni/TiN (8/15/10 nm) θ (o) Fig. 5. XRD analysis to confirm the formation of Ni monosilicide (NiSi). peaks of the Ni silicides formed by the two structures represent the same crystal-orientation. From these results, it was found that Sb interlayer does not substantially affect the formation of Ni mono-silicide with low resistivity. Fig. 6 shows the I-V characteristics of Schottky diodes fabricated by the process flow as shown Fig. 1. All measurements were performed at room temperature. In the control sample without the Sb interlayer, typical

4 44 HORYEONG LEE et al : A STUDY OF THE DEPENDENCE OF EFFECTIVE SCHOTTKY BARRIER HEIGHT IN NI SILICIDE/N-SI ON Current Density [A/cm 2 ] Sb/Ni/TiN(6/15/10nm) Sb/Ni/TiN(4/15/10nm) Sb/Ni/TiN(2/15/10nm) Ni/TiN(15/10nm) NiSi/n-Si(100) Reverse Bias Sb/Ni/TiN(8/15/10nm) Sb/Ni/TiN(10/15/10nm) [ Units : nm ] Ni/TiN(15/10) Sb/Ni/TiN(2/15/10) Sb/Ni/TiN(4/15/10) Sb/Ni/TiN(6/15/10) Sb/Ni/TiN(8/15/10) Sb/Ni/TiN(10/15/10) Forward Bias Applied Voltage [V] Fig. 6. The current-voltage (I-V) characteristics of the fabricated Schottky diodes. Table 1. Current density of the fabricated Schottky diodes at -1 V and 1 V Schottky diode characteristic is observed, indicating that the effective Ф Bn is high. The effective Ф Bn of the control sample is about 0.58 ev, which is extracted from the I-V curve in Fig. 6 using the thermionic equation for Schottky diodes [12]. In contrast, the samples with the Sb interlayer show higher current than the control sample, especially in reverse bias region. As the Sb interlayer becomes thicker, the current level of the samples with the Sb interlayer increases and the differences between the forward and reverse currents become comparable as if ohmic contact is formed as shown in Table 1. These results show that the effective Ф Bn is significantly lower than that in the control sample. But the current level difference between Schottky diodes fabricated with Sb/Ni/TiN (8/15/10 nm) and Sb/Ni/TiN (10/15/10 nm) structures is almost the same. That is, it can be said that the reduction of the effective Ф Bn becomes saturated at the thickness of 8 nm. Therefore, considering the process time and cost, it can be concluded that the optimal value of the Sb interlayer thickness is 8 nm. To extract the effective Ф Bn, the activation energy I F /T 2 [A/K 2 ] 10-8 V F = 0.08V V F = 0.10V V F = 0.02V V F = 0.04V V F = 0.06V measurement method was used for the Sb/Ni/TiN structure with 8 nm Sb interlayer. Fig. 7 shows the activation energy characteristics measured in a temperature range from 113 to 173 K at different forward voltages (0.02 to 0.1 V). The effective Ф Bn was extracted from the slopes of the curves using Eq. (1) [12], 1000/T [K -1 ] Fig. 7. Activation energy plots to extract low effective Ф Bn of the Schottky diode fabricated using Sb/Ni/TiN structure with an 8 nm Sb interlayer. Si, Ni Intensity [counts/sec] NiSi/n-Si interface Ni 10 2 Si Sb 10 1 Ni Sb Depth [nm] = Sb concentration [cm -3 ] Fig. 8. SIMS depth profile of Sb in the Schottky diode fabricated using Sb/Ni/TiN(8/15/10 nm) structure to confirm Sb segregation at the Ni silicide/n-si interface. where I F is the forward current, V F is the forward bias voltage, A is the electrically active area, A * is the effective Richardson constant, q is the electronic charge and k is the Boltzmann's constant. The extracted average effective electron Ф Bn value is about ev. This value is significantly lower than that of Schottky diodes Si (1)

5 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.1, FEBRUARY, without the Sb interlayer. SIMS analysis was carried out to check the distribution of Sb. Fig. 8 shows the SIMS depth profile of Sb in the Schottky diode with 8 nm Sb interlayer. The Sb concentration represents peak point which indicates Sb segregation at the Ni silicide/n-si interface. SIMS data also shows that the Sb interlayer does not suppress the formation of Ni silicide. This result is consistent with FE-SEM data in Fig. 4 and XRD data in Fig. 5. From the SIMS analysis, we can speculate that the considerable reduction in the effective Ф Bn in samples with the Sb interlayer is due to the Sb segregation at the Ni silicide/n-si interface. S. M. Koh et al. [13, 14] contend that impurities such as sulfur (S) and tellurium (Te) acting as donors generate the shallow donor-type trap level a little below the conduction band in Si. These shallow donor-type traps are generated by the segregation of impurities such as S and Te at the Ni silicide/n-si interface, leading to the sharp band bending of Si, which reduces the effective Ф Bn. It has been reported that Sb generates a donor-type trap level at ev below the conduction band in Si [12, 15]. Consequently, the donor-type trap levels due to Sb segregation at the Ni silicide/n-si interface generate positive charges on the Si side of the interface. These positive charges then induce negative charges of equal magnitude (interfacial dipoles) on the Ni silicide side of the interface, generating an electric field [13, 14, 16, 17]. This electric field leads to the sharp band bending of Si, which reduces the electron barrier width. The narrower electron barrier increases the probability of electron tunneling, resulting in a lower effective Ф Bn. Further investigations and experiments are needed to demonstrate the definitive mechanism of reducing effective Ф Bn due to Sb segregation. IV. CONCLUSIONS To reduce the effective Ф Bn at the NiSi/n-Si interface, Sb interlayer was introduced using RF magnetron sputtering. It was found that the samples with the Sb interlayer show more ohmic characteristics than the control sample without Sb interlayer. This effect increases as the Sb interlayer becomes thicker. From these results, we can speculate that the effective Ф Bn is reduced considerably due to the influence of Sb interlayer. The current level difference between Schottky diodes with Sb/Ni/TiN (8/15/10 nm) and Sb/Ni/TiN (10/15/10 nm) structures is almost same. Therefore, considering the process time and cost, it can be said that the optimal value of the Sb interlayer thickness is 8 nm. A low effective Ф Bn of ev was achieved for the Sb-segregated sample using the activation-energy measurement method. This reduction in effective Ф Bn is due to the formation of interfacial dipoles generated by Sb segregation at the Ni silicide/n-si interface, which increases the probability of electron tunneling.. ACKNOWLEDGMENTS This research was supported in part by the MOTIE(Ministry of Trade, Industry & Energy (G ) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. This research was also supported in part by Basic Science Research Program through the National Research Foundation of Korea(NRF) funded by the Ministry of Education( ) and in part by Nano Material Technology Development Program through the National Research Foundation of Korea(NRF) funded by the Ministry of Science, ICT and Future Planning( ). Authors acknowledge Dr. Sang Geul Lee at the Korea Basic Science Institution (KBSI) in Daegu for useful discussion and taking the XRD data. REFERENCES [1] H. Noda, et al, Threshold Voltage Controlled 0.1- μm MOSFET Utilizing Inversion Layer as Extreme Shallow Source/Drain, IEEE International Electron Devices Meeting, pp , Dec, [2] A. Amerasekera, et al, Correlating Drain Junction Scaling, Salicide Thickness, and Lateral NPN Behavior, with the ESD/EOS Performance of a 0.25 μm CMOS Process, IEEE International Electron Devices Meeting, pp , Dec, [3] S. D. Kim, et al, Advanced model and analysis of series resistance for CMOS scaling into nanometer regime, IEEE Transactions on Electron Devices, Vol. 49, No. 3, pp , Mar, 2002.

6 46 HORYEONG LEE et al : A STUDY OF THE DEPENDENCE OF EFFECTIVE SCHOTTKY BARRIER HEIGHT IN NI SILICIDE/N-SI ON [4] S. Shishiguchi, et al, Boron Implanted Shallow Junction Formation by High-Temperature/ Short- Time/High-Ramping-Rate(400 o C/sec) RTA, Symposium on VLSI Technology, pp , Jun, [5] R. T. P. Lee, et al, Novel Nickel-Alloy Silicides for Source/Drain Contact Resistance Reduction in N-Channel Multiple-Gate Transistors with Sub- 35nm Gate Length, IEEE International Electron Devices Meeting, pp. 1-4, Dec, [6] T. Morimoto, et al, Self-Aligned Nickel-Mono- Silicide Technology for High-Speed Deep Submicrometer Logic CMOS ULSI, IEEE Transactions on Electron Devices, Vol. 42, No. 5, pp , May, [7] H. Iwai, et al, NiSi salicide technology for scaled CMOS, Microelectronic Engineering, Vol. 60, No. 1-2, pp , Jan, [8] T. J. Kang, et al, Reduction of Sheet Resistance and Low-Thermal-Budget Relaxation of Stress Gradients in Polysilicon Microcantilever Beams Using Nickel-Silicides, Journal of Microelctromechanical Systems, Vol. 16, No. 2, pp , Apr, [9] S. D. Kim, et al, An Integrated Methodology for Accurate Extraction of S/D Series Resistance Components in Nanoscale MOSFETs, IEEE International Electron Devices Meeting, pp , Dec, [10] S. Franssila, Introduction to Microfabrication, Wiley, [11] D. Deduytsche, An in situ study of the stability of thin Ni-silicide layers, Ghent University, a doctoral dissertation, [12] S. M. Sze, et al, Physics of Semiconductor Devices, Wiley-Interscience, Third Edition, [13] S. M. Koh, et al, Contact-Resistance Reduction for Strained n-finfets With Silicon-Carbon Source/Drain and Platinum-Based Silicide Contacts Featuring Tellurium Implantation and Segregation, IEEE Transactions on Electron Devices, Vol. 58, No. 11, pp , Nov, [14] S. M. Koh, et al, Contact Technology for Strained nfinfets With Silicon-Carbon Source/Drain Stressors Featuring Sulfur Implant and Segregation, IEEE Transactions on Electron Devices, Vol. 59, No. 4, pp , Apr, [15] D. K. Wilson, et al, Electron Spin Resonance Experiments on Donors in Silicon. III. Investigation of Excited States by the Application of Uniaxial Stress and Their Importance in Relaxation Process, Physical Review, Vol. 124, No. 4, pp , Nov, [16] Y. Tong, et al, Selenium Segregation for Effective Schottky Barrier Height Reduction in NiGe/n-Ge Contacts, IEEE Electron Device Letters, Vol. 33, No. 6, pp , Jun, [17] Z. Zhang, et al, Schottky-Barrier Height Tuning by Means of Ion Implantation Into Preformed Silicide Films Followed by Drive-In Anneal, IEEE Electron Device Letters, Vol. 28, No. 7, pp , Jul, Horyeong Lee received a B.S. degree in electronics engineering in 2013, and is currently working toward an M.S. degree in the Department of Electronics Engineering from the Chungnam National University, Daejeon, Korea. His research interests include nickel silicide, high-k material, Schottky barrier MOSFETs, high efficient silicon solar cells and contact resistance reduction. Meng Li was born in China in He received a B.S. degree in electronics engineering from Mokwon University, Daejeon, Korea, in He is currently working toward the M.S. degree in the Department of Electronics Engineering, Chungnam National University, Daejeon, Korea. His research interests include nickel silicide and Schottky barrier MOSFETs as well as high efficient silicon solar cells.

7 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.1, FEBRUARY, Jungwoo Oh is an assistant professor at Yonsei University in the school of integrated technology (Incheon Korea). He worked as a project engineer with the Front End Processes Division at SEMATECH (Austin, TX USA), investigating nanoscale CMOS devices and assessing potential alternative material properties to replace silicon for nextgeneration CMOS technology. At the SEMATECH consortium, he works with leading semiconductor manufacturers and state government to solve common manufacturing problems by leveraging resources. Dr. Oh holds a doctorate in materials science and engineering from the University of Texas at Austin. His Ph.D. research was in the area of germanium-silicon-based CMOS photonics. He also earned a master s degree in materials science and engineering from POSTECH and a bachelor s degree from Yonsei University. Hi-Deok Lee received B.S., M.S., and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1990, 1992, and 1996, respectively. In 1993, he joined the LG Semicon Company, Ltd. (currently SK Hynix Semiconductor Ltd.), Cheongju, Chungbuk, Korea, where he has been involved in the development of μm, 0.25-μm, and 0.18-μm CMOS technologies, respectively. He was also responsible for the development of 0.15-μm and 0.13-μm CMOS technologies. Since 2001, he has been with Chungnam National University, Daejeon, Korea, with the Department of Electronics Engineering. From 2006 to 2008, he was with the University of Texas, Austin, and SEMATECH, Austin, as a Visiting Scholar. His research interests are in the areas of nanoscale CMOS technology and its reliability physics, silicide technology, and Test Element Group design. His research interests also include development of high performance analog MOSFETs and high voltage MOSFETs, analysis of their noise and reliability characteristics. Dr. Lee is a member of the Institute of Electronics Engineers of Korea. He received the Excellent Professor Award from Chungnam National University in 2001 and 2004.