Implications of Stress Migration and Voiding in Cu Damascene Interconnections

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1 Implications of Stress Migration and Voiding in Cu Damascene Interconnections E. T. Ogawa and J. W. McPherson Texas Instruments, Inc. Dallas, TX USA 22 Topical Research Conference (TRC) on Reliability, The University of Texas at Austin, J. J. Pickle Research Campus Wednesday, October 3, 22, Austin, TX 1

2 Acknowledgements T. - C. Chiu K. J. Dickerson and J. C. Ondrusek M. K. Jain and T. D. Bonifield J. A. Rosal L. Y. Tsung W. R. McKee 2

3 Purpose Understand stress-induced voiding phenomena in Cu interconnects and how it is different from Al-based interconnects. Characterize stress-induced voiding under vias for wide Cu interconnects and propose a mechanism of damage formation. Identify areas for future research. 3

4 Outline Introduction Observations Physical Picture Time Evolution Design-in Reliability Future Work Conclusion 4

5 INTRODUCTION Ogawa/McPherson 5

Short History on SIV ALUMINUM Ref: J. McPherson and C. Dunn, Journal of Vacuum Science and Technology B, 1321 (1987). Stress-induced Void (SIV) formation Wearout mechanism first reported in 1984.

6 Short History on SIV ALUMINUM Ref: J. McPherson and C. Dunn, Journal of Vacuum Science and Technology B, 1321 (1987). Stress-induced Void (SIV) formation Wearout mechanism first reported in Occurs in narrow Al lines (< 4 µm). Driving Force: High hydrostatic stress (σ H ) levels by CTE mismatch between metal and rigid dielectrics (SiO 2 and Si 3 N 4 ). Damage Mode: Voids nucleated at grain boundaries in high stress locations such as line edges or topographical steps. Voiding can continue growth until circuit discontinuity results. 6

7 Stress (MPa) Stress (MPa) µm Al (1. wt.% Cu) -2 σ H vs T Temperature ( C).25 µm Cu/TEOS 1 σ 8 x σ 6 y σ 4 z 2-2 σ H vs T Temperature ( C) Thermal Stresses σ x σ y σ z.5 µm Al (1. wt.% Cu) σ x σ y σ z σ H vs T Temperature ( C).4 µm Cu/TEOS σ H vs T σ x σ y σ z Temperature ( C) 1. µm Al (1. wt.% Cu) σ H vs T σ H vs T σ x σ y σ z Temperature ( C) 1. µm Cu/TEOS σ x σ y σ z Temperature ( C) Al: More SIV with decreasing line width. Cu: SIV relatively independent of line width. Refs: PhD. Theses, U. Texas at Austin; J. Kasturirangan (1995); Y. Du, (21); I.-S. Yeo (1994); S.-H. Rhee(21). 7

8 Al vs. Cu in IC Technology W M1 TiN GB Ti M2 ILD SiNx V1 M1 DB GB M2 ILD Property Al Cu CTE (ppm/k) Young's modulus (GPa) 7 11 Poisson Ratio GB Activation Energy (ev) Deposition Method PVD ECD Materials properties suggest less SIV with Cu for the same transport mechanism. 8

9 Bake Test Experiment Van der Pauw (VDP) Via-fed Narrow Lead M2 M1 V1 M2 V1 Lead Lengths >> 3 µm M1 Lead Lengths >> 3 µm Via size:.18x.18 µm 2 ; Lead widths: 3 µm. M2 Via size:.18x.18 µm 2 ; Lead widths: ~.18 µm. Process Information: No post-ecd anneal prior to encapsulation. Bake Test Conditions: Resistance measurements at, 168, 336, and 5 hrs. Test temperatures: 1, 15, 2, 25 C. 9

10 OBSERVATIONS Ogawa/McPherson 1

11 Physical Damage Formation M2 VDP Test Structure Void formed under via. Bake time > 1 hrs at 15 C. V1 183 nm Void size ~.1 µm 3. No evidence of SIV damage found with vias to narrow metal leads. M1 Voiding is thus more prevalent with vias placed over wide metal leads. REF: E. T. Ogawa, et al., 4 th International Reliability Physics Symposium (IRPS), Dallas, TX 22, pp

12 VDP Structure Void Formation Kinetics Relative % of Failing Sites (48 total) OPEN >1% >5% >2% >1% >5% 8% 1 C 15 C 2 C 25 C 7% 6% 5% 4% 3% 2% 1% % 168 hrs 336 hrs 5 hrs 168 hrs 336 hrs 5 hrs 168 hrs 336 hrs 5 hrs 168 hrs 336 hrs 5 hrs 12

13 McPherson & Dunn, Relative Creep Rate Creep/Voiding Rate Model SM Model where : N : R 3.2, M-D Equation ( T Q R > 5%, 168 hrs 19 C T ) ev, N Temperature ( C) Exp( T T Q ) k T B 27 C 13

14 SM Effective Activation Energy Model Activation Energy (ev) Q eff = where Q : N N Q k B 3.2, T ( ) T T Q 2.74 ev, T 19 C Temperature ( C) 27 o C 14

15 PHYSICAL PICTURE Ogawa/McPherson 15

16 Confined Grain Growth Leading to SIV Grain growth produces excess vacancies. Barrier and capping layers trap vacancies. Stress gradients develop underneath via. Vacancies follow stress gradients. σ + σ - σ - σ - σ + σ + 16

17 Excess Void Volume Generated by Grain Growth 1 V GB (s,ds) (µm) s (µm) Void Volume generated assuming grain size doubling. V GB (s,ds) = Total Void Volume generated by GB elimination; s initial grain size; ds grain boundary width =.5 µm. 17

18 Active Diffusion Volume M1 2 x D VIA1 w wide L wide >> x D Active Diffusion Volume (ADV) is defined by a given bake temperature and time. ADV is limited by interconnect geometry, diffusion length, and stress-gradient region. Wide lines have greater number of vacancies to cause SIV. 18

19 Vacancy Reduction Relative Fail Rate 1.5 Cu without Post-ECD anneal Cu with post-ecd anneal 1 2 Baking Time at 15 C (hrs) Post-ECD anneal reduces the number of available vacancies for SIV after encapsulation. 19

20 Finite Element Analysis Width direction M2 M1 Height V1 Length direction Via center Via edge Hydrostatic Tensile Stress, σ H at 2 C, T σ = = 25 C. Width Direction σ H, Unit: MPa 2

21 Void Nucleation M2 V1 ~ 18 nm Nucleation site is in agreement with FEA result. M1 Early Stages of Voiding. 21

22 Physical Picture Summary M2 SiNx ILD M1 σ + Barrier V1 σ - σ - σ + δ I Vacancy supersaturation at grain boundaries. Vacancy diffusion to metal/nitride interface. Interfacial diffusion to via. 22

23 TIME EVOLUTION Ogawa/McPherson 23

24 Time Evolution of SIV-induced Resistance Change.7 Metal 1 is unannealed. Relative Resistance Change Time (hrs) Most individual traces show resistance saturation within testing period. A subset of traces show evidence of an incubation time. Saturation resistance also varies widely. 24

Resistance Saturation M1 V1 ~ 18 nm M2 VOID 1. Stress Relaxation: Void Evolution Physics: A. Stress concentration & vacancy migration void nucleation & growth Incubation Time, τ I. B.

25 Resistance Saturation M1 V1 ~ 18 nm M2 VOID 1. Stress Relaxation: Void Evolution Physics: A. Stress concentration & vacancy migration void nucleation & growth Incubation Time, τ I. B. Void nucleation and growth stress relaxation. C. Stress relaxation resistance saturation, τ S. 2. Stress Relief by Void Formation: 3. Resistance Rise: R R R σ(t) = σ σ exp ( t τ ) σ(t) = 1 exp σ σ σ S ( t τ ) S σ(t) VOID SIZE (t) VOID SIZE = θ ( t τ ) { 1 exp[ ( t τ ) τ ]} I I S 25

26 DESIGN-IN RELIABILITY Ogawa/McPherson 26

27 Effect of Interconnect Volumetric Scale w narrow =.3 µm L,narrow >> x VIA1 GB M1 M1 2 x GB VIA1 w wide x GB Active Diffusion Volume L,wide >> x GB V GG,Void, narrow = µ m 3, V GG,Void, wide = µ m 3, Recall that 2 V Void 1. 1 µ m 3 Increased reliability of narrow leads over wide ones implies the importance of interconnect design to robust backend reliability. Ogawa/McPherson 27

28 Locally Redundant Vias (a) 2 x D (b) 2 x D L sep >> x D 2 x D M1 Locally Redundant VIA1 R c VIA1 w wide M1 VIA1 w wide Isolated Redundant VIA1 L,wide >> x D (a) Via pair placed within the active diffusion volume L 1,wide >> x D (b) Redundant vias that are separated farther than a diffusion length, x D. Active diffusion volume picture provides a formalism for redundant placement (or equivalent approaches). Redundancy performed within the active diffusion volume provides additional reliability benefit. Ogawa/McPherson 28

29 FUTURE RESEARCH OPPORTUN ITIES & CONCLUSIONS Ogawa/McPherson 29

30 Future Research & Outstanding Issues SIV nucleation and growth role of stress and stress gradients, microstructure, interfaces. Microscopic models time-dependent stress relief, via-size dependence, incubation. Interface characterization and modification Impurity additions, surface treatments. New materials research - Low-k intermetal dielectrics, etch stop barriers, and diffusion barriers. 3

31 Conclusions Stress-induced void can occur and is most severe at vias connected to wide Cu metal leads. Vacancy supersaturation can occur due to confined grain growth. The active diffusion volume defines the extent of vacancy migration. Voiding first nucleates at the via perimeter. Kinetics suggest that grain boundary and interface mechanisms are important. Time evolution analysis indicates that a resistance saturation occurs and is a consequence of stress relaxation. Design-in reliability can have a very positive impact on SIV robustness. 31

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