3DIC Integration with TSV Current Progress and Future Outlook

Transcription

1 3DIC Integration with TSV Current Progress and Future Outlook Shan Gao, Dim-Lee Kwong Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research) Singapore 9 September,

2 Overview Introduction 3DIC integration and main application Products to be commercialized Technologies and key challenges for 3DIC with TSV Current progress in 3D TSV development Outlook

3 Why 3DIC? - Pre-positioning Strategy for More than Moore High Density Memory Low Power Logic Power Regulator Sensors High Speed Memory High Performance Logic Radio Photonics I/O 2-D Integration High Density memory Photonics High Speed Memory High Perf. Logic Low Power Logic Sensors Power Reg. Radio Discrete 3-D Integration ENABLER

4 3D TSV Application Status

5 3D TSV Market Drivers

6 3D TSV Packaging Market Forecast Logic + memory application to drive >30% of the 3D TSV packaging market by 2015 CIS, MEMS, SENSOR to drive 30% of market share Memory + Memory stacking combined DRAM & NAND drive 20%

7 3D IC Technology Development in IME TSV Fabrication Wafer Thinning Cu-Cu Wafer Bonding Wafer Level RDL 3D IC Structure C2W/C2C Bonding Micro-bumping Substrate Modeling & Characterization Mechanical simulation for low stress Thermal simulation for low chip temperature Electrical simulation for Signal Integrity (SI), Power Integrity (PI) Electrical test, Reliability test and FMEA Development of Materials Temporary bonding/debonding adhesive Plating chemicals for high AR (>10) TSV filling CMP slurries for high removal rate (5µm/min) Low curing temperature dielectric (< 180ºC) Small gap wafer level underfills (<10µm) Low stress/warpage wafer level encapsulants

8 3D TSV Integration Process Flow Via First (TSV Interposer) Si TSV Photo TSV ETCH TSV CLEAN TSV CVD TSV PVD TSV ECP TSV CMP FEOL BEOL Via Middle (Logic, Memory) Si FEOL TSV Photo TSV ETCH TSV CLEAN TSV CVD TSV PVD TSV ECP TSV CMP BEOL RDL & BUMP BOND & THIN BS VIA REVEAL BS RDL/BUMP Via Last (B2T) (CIS, Memory) Si FEOL BEOL BOND & THIN TSV PHOTO TSV ETCH TSV CLEAN TSV LTCVD CONTACT ETCH TSV PVD TSV ECP DEBOND CHIP STACK ASSY & TEST

9 TSV Fabrication Process Key challenges: Conformal dielectric step coverage and Barrier / Cu seed step coverage Void free electroplating, Cu Protrusion Via etching Dielectric Layer Barrier/Seed/Cu Filling Cu CMP Description Dielectric coverage Barrier metal and seed step coverage Electro plated via Wafer / TSV thickness Established in IME ~10% for AR10 ~5% for AR10 Ø5um/AR10, 15um pitch 50um On going Research: Via size 2um/AR10, < 10um pitch

10 TSV Fabrication Process Challenges

11 Process Challengess Cu Protrusion Cu protrusion (hundreds to thousands Å) may attack M1 and ILD layer Double CMP and Heat Treatment method have been reported for viamiddle process but these are typically high temperature processes Low temperature ILD process for Cu BEOL can minimize Cu protrusion for interposer application process development needed

12 Interconnection Cu-Cu Wafer Bonding Need carrier wafer for chip bonding Lower density integration On going Research: Cu Cu W2W bonding: Temperature 300 o C, Pitch 15um No need carrier wafer High density integration Work only between 1 st and 2 nd wafer bonding only, the 3 rd wafer stack back to Face to back

13 Interconnection - Fine Pitch Micro-Bump Key challenges: Low bonding temperature, Fine pitch and High reliability Si Chip Si chip Micro bump IMC based interconnection Cu pillar + Thin solder layer Description Bonding Temperature Bump material Bump Pitch Micro bump 180 C Cu pillar with lead free solder 260 C Specification AuInSn, InSn 25um On going Research: Composite joint for C2C, C2W bonding, Bump Pitch: 15um

14 Thin Wafer Handling - Temporally Bonding/Debonding BSI Thermal plastic adhesive TMAT Mechanically released adhesive 3M Laser released adhesive TOK Chemical released adhesive

15 Chip Stacking Process Key challenges: Multiple chip stacking with low stand off interconnection Low warpage wafer level encapsulation Wafer Level Underfilling Base Wafer Chuck C2C & C2W Bonding Base Wafer Wafer Level Molding Description Bonding method (C2W, C2C) Stand off Low Temperature Solder (180 C) Cu pillar with leadfree solder (260 C) Specification On going Research: C2W bonding : 10 chips Interconnection: RDLless and Bumpless Micro joint Thermo compression 5um 15um

16 Reliability Challenges Stress concentration, Cracks around TSVs IMC, fatigue failure of microbumps Moisture induced delamination, corrosion Substrate Hot Spot in Chip & Thermal Management Electromigration in Microbumps & TSVs

17 Sensor Chip Design For Reliability R 1 ' y [ 1 00] y[ 1 10] ' x [ 010] x[ 110] R 4 R 3 R 2 Stress sensor for process development Comb & Triple Tracks Sensor for moisture ingress & corrosion N++ P + implant N++ P + implant n-well n-well p substrate Thermal chip design Crack sensor chip design

18 Integrated Cooling Solution Heat Exchanger Mini Pump Fluidic adaptor Silicon carrier PCB Avg. Chip Temperature ( C) Chip with 400 Bumps ( Measured Data) Chip with 2500 Bumps ( Simulation Data) Avg Cooling Liquid Temp Chip Heat Dissipation (W/cm2) Micro Channels Seal ring Fluidic Inlet TSV Electrical I/O Integrated single or two phase liquid cooling for high power chips in 3DIC Chip carrier with fluidic and electrical paths by C2C bonding 3D electrical and fluidic interconnection using silicon interposer On going Research: Two Phase Boiling Cooling

19 Singapore 3D TSV Consortium 1 st Year Phase 1 (18 months) 2 nd Year 3 rd Year Phase 2 (18 months) Design & Modeling Studies Process & Reliability studies Identify & establishment 300mm line through consortium efforts Process & Characterization studies on 300mm wafer Application: Mobile Devices One Logic Chip & Six Memory Chips Consortium Deliverables: Phase 1: Design Guidelines & Process Development Phase 2: Full Functional Device Demonstration

20 IME 3DIC Development Roadmap Design, Simulation & Characterization Sensor + Mixed Signal Sensor + Memory + FPGA PMIC + Memory + RFIC TSV Fabrication Thermo-Mechanical simulation Dynamic two-phase flow simulation High freq. (up to 80GHz) TSV Electrical Characterization (Φ<2um, D<20um) Sub-micron Via Φ1um, D10um Via Last Φ5um, D50um Via Middle Φ2um, D20um Wafer Handling & Thinning 12 20um thickness 12 10um thickness 8 50um thickness 12 50um thickness Wafer Level RDL & Micro-bumping Line/Space: 15um/15um Line/Space: 10um/10um CuInSn solder: 180 C, Size: 8um, Pitch: 15um 3D Stacking (C2C, C2W, W2W) W2W Cu-Cu Bonding (Pad size: 5um, pitch: 10um, Bonding temp.: <200 C) C2C/C2W bonding with solder (10 chips)

21 3DIC Product Development Challenges Infrastructure availability and supply chain I/O standardization between interfaces Thermal management and interconnect reliability Shift in the Design/Test method paradigm and system co design

22 Thank you for your attention!