Semiconductor Device Fabrication

Transcription

1 5 May 2003 Review Homework 6 Semiconductor Device Fabrication William Shockley, 1945 The network before the internet Bell Labs established a group to develop a semiconductor replacement for the vacuum tube. The group led by William Shockley, succeeded in creating an amplifying circuit utilizing a pointcontact "transfer resistance" device that later became known as a transistor. By 1954 the transistor was an essential component of the telephone system. The first Transistor 1

2 Robert Noyce, 1959 Robert Noyce of Fairchild had the idea to evaporate a thin metal layer over discrete circuits. The metal layer connected down to the junctions through the holes in the silicon dioxide and was then etched into a pattern to interconnect the circuit. Robert, Gordon Moore and went on to create a new economy. read Hooking Up, by Tom Woolfe. Vacuum Technologies Killer App : Semiconductor processing 2

3 Current State-of-the-Art manufacturing: 300 mm wafers Properties of Silicon A Semiconductor (1 of only 4) Slightly Reactive (required vacuum processing) easily doped (highly diffusive) EXCEPT when a barrier layer is present Abundant and easy to purify Modern Alchemy 3

4 Features that can be fabricated in Silicon Transistors Resistors Diodes (regular and LED) Capacitors Micromechanical Structures (MEMS) 4

5 Photo resist Patterning Ion Implantation to non-resist covered surfaces 5

6 Deep Ultraviolet Lithography Exposure through the Reticle 6

7 Bake and Develop A Modern Semiconductor Vacuum Process Tool Front End Buffer Load Lock Robot Handler Process Modules 7

8 Robot Handler & Process Modules Inside Process Module 8

9 Process Modules involving Vacuum Technology Plasma Etching Chemical Vapor Deposition (CVD) Oxides and Nitrides of Silicon Ion Implantation Epitaxial and Anneal (RTP) Physical Vapor Deposition (PVD) Inspection (Scanning Electron Microscope) Etch Cluster Tool Example: Applied Materials P5000 consists of four, independently controlled etch Chamber modules which surround a central handler. Chambers A, B, and C are Magnetically- Enhanced Reactive Ion Etch (MERIE) systems, each equipped with optical endpoint detection to allow for more customized etching. The chamber configuration and system software allow control over a wide range of process parameters. Chamber A: metals (Al/Si, Ti, or TiW) Chamber B: oxides and nitrides; Chamber C: silicon and polysilicon; Chamber D: passivation and strip. Features: Compatible with 4" wafers. Helium backside cooling on Chamber A-C 9

10 Issues with Etch Elastomer Degradation (especially dynamic seals) Consumable costs Collateral Wafer Damage Particle shed rate MTBM, MTTR Chemical Vapor Deposition (CVD) Example: Silane for Polysilicon deposition Plasma generation, high Temperatures Deposition rate ~500 mtorr using silane (SiH4). Deposition temperature is ~620C for polysilicon and ~560C for amorphous silicon. The deposition rate is ~125A/minute. Base 1x10-5 Torr Challenges: Deposition Rate Uniformity MTBM (Mean Time between Maintenance), MTTC (Mean time to clean). 10

11 To separate conducting areas from one another, a layer of insulator (Glass) is grown by exposing the silicon surface to high temperature steam. Growth be suppressed with a nitride mask Oxides and Nitrides The neutral silicon is converted to a negative or positive conductor by the process of ion implantation. Dopant atoms are ionized and then accelerated by an electric field until they impinge on the silicon surface, where they embed themselves. During subsequent thermal treatment, the dopants redistribute Vacuum level 1x10-7 Torr Ion Implantation 11

12 RTP and Anneal High Temperatures (900 C) at wafer surface Repair damage caused from Ion Implantation Drive (diffusion) implanted dopants into the substrate Challenges: Wafer Uniformity, contamination Pressures x10-6 Torr Interconnects & Metal Plugs After the transistors are built in the silicon, they must be interconnected using metal layers above the silicon substrate. First an insulating glass layer is deposited, then contact holes are cut into the glass layer down to the silicon. Metal is deposited on top of the glass, connecting to the devices through the contact holes. 12

13 Physical Vapor Deposition (sputtering, Evaporation) Inspection Important for process qualification, yield management, ongoing quality assurance 13

14 Per Wafer Defect Density, Yield tools for Managing Defects: Clean rooms and Minienvironments 14

15 From Wafer to device Intel Pentium IV Chip with 47 Million Transistors 15

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