12.2 Silicon Solar Cells

Transcription

1 12.2 Silicon Solar Cells High Efficiency Crystalline Solar Cells Fabrication of large area (5 inch X 5 inch) crystalline silicon solar cells (S. Saravanan, Karthick Murukesan, Balraj Arunachalam, Mallikarjunachari, Sandeep Kumbhar): Process optimisation on Boron doped mono and mono like silicon wafers (p-type) of thickness 180±20 m with bulk resistivity of cm and the carrier life time in the range of s were carried out for fabricating high efficiency silicon solar cells. Mono like wafers are made by seeded directional crystallization using black casting techniques and contain large areas of mono crystalline silicon and peripheral areas of multi crystalline silicon. These are cost competitive compared to mono wafers, however the electrical performance is slightly higher than the multi wafers and comparable to mono wafers. Process optimisation has been approached in all the processes and still the optimisation is ongoing. The efficiency trend of the all the process trials are shown in Fig. 1. Fig. 1: Efficiency trend of the process trials. A clear improvement in the performance has been achieved over a short period of time using several of the unit processes reported earlier. Fig. 2: IV Characteristics of the cell with Fig. 3: External quantum efficiency and efficiency of 15.72%. reflectance of the cell with efficiency of 15.72%. 1

2 The best efficiency observed for mono like and mono silicon solar cells are 15.93% and 15.72% respectively. The IV characteristics and EQE of the mono silicon solar cell of efficiency 15.72% is shown in Fig. 2 and Fig. 3. Further process optimisations for fabricating high efficiency silicon solar cells are underway and the target improvements for the coming quarter are listed below Improving the uniformity of the diffusion process to obtain a uniform sheet resistance in the range of /sq across the wafer. Optimization of the SiN film to improve the overall quantum efficiency. Optimisation of the co-firing process to reduce wafer bow. Al2O3 for surface passivation: Aluminum oxide is an emerging material for the passivation of p-type crystalline silicon surfaces. We had been evaluating pulsed-dc sputtering process for the deposition of this film and several encouraging results were obtained and reported in the previous reports. In addition we have recently started investigating solution processed Al 2O3 for this purpose. This technique promises a cheaper process compared to any other technique presently being explored for the deposition of Al2O3 for solar cell passivation. Results from both these attempts are reported below. Al2O3 deposited by pulsed-dc supttering (Meenakshi Bhaisare): For an implementation of Aluminum oxide (AlOx) film on solar cells, the film must show properties like high temperature thermal stability as required during a contact - firing process. The high temperature firing step is required for an industrial screen - printed solar cells to activate the contacts, typically at temperature ~ 850 oc for few seconds. In this report we implemented the stack of AlOx film capped with SiNx film, which is reported to result in improving the thermal stability, for surface passivation of p - type crystalline silicon. In this experiment AlOx film (~ 20 nm) is deposited by pulsed DC (p - DC) reactive sputtering technique and SiNx film (~ 75 nm) deposited by inductive coupled plasma (ICP) - CVD technique. For the surface passivation qualification of the stack structure, SiNx film deposited directly on AlOx film which was annealed in N2 + O2 ambient in 79:21 ratios to mimic dry air at 520 C. The film stack was deposited on both sides of p-type FZ wafer with ρ of 1- Ω. cm. Fig. 4(a) shows the effective minority carrier life-time (τeff), measured by Sinton Life-time tester. Fig. 4(b) shows the effective surface recombination velocity (S eff) extracted from life-time by assuming τbulk ~. AlOx/p-Si AlOx/p-Si -3 ICP- SiNx/ AlOx/p-Si ICP- SiNx/ AlOx/p-Si Seff (cm. s-1) eff (s) n (cm-3) n (cm-3) 16 Fig. 4: (a) Effective minority carrier life-time (τeff) and (b) surface recombination velocity (Seff) measured on p-type FZ wafer. The τeff obtained for AlOx film alone is higher than that for ICP- SiN x/alox/p-si stack, as shown in Fig. 4(a) and hence the S eff is higher for stack structure. The degradation in the 2

3 passivation quality for stack structure may be due to the fact that the negative Q f for stack structure is lower than AlOx film alone, as mentioned in previous report. The negative Qf these samples shown the values saturating to ~ cm-2, which leads to a degradation of minority carrier life time on p type silicon surface because of a low impact of field - effect passivation. On the other hand value of Dit for these samples, shown slight improvement after SiNx deposition for stack structure. In the context of solar cell surface passivation, especially the surface of highly doped emitter, improvement in D it is more desirable due to the chemical nature of the passivation on such surfaces. A complete investigation would include the implementation of Al2O3 on solar cells or equivalent structures and it is underway. Al2O3 deposited by solution processing (Kalaivani S.): Aluminium nitrate nonahydrate (99.997% purity) has been dissolved in 2-methoxyethanol (99.99% purity) with a concentration of 0.2M, that forms a transparent clear solution. The alumina sol-gel is spray coated and subjected to heat treatment at 400 oc for 5 minutes to evaporate the solvent. Two RCA cleaned, p-type, CZ <0> Si wafers with resistivity of 4 7 -cm is used as the substrate for the experiments. The thin layer of Al2O3 is deposited on the wafer by spray coating process using N2 gas and the film is subjected to hot plate annealing of 400 C for 5 minutes. By varying the time of spray the film thickness has been controlled. nm film is deposited on one wafer (Sample A) and another wafer (sample B) is deposited with 19 nm of Al2O3 film by varying the time of spraying. Table (1) shows the Ellipsometry results of both the samples. It is seen that the film thickness uniformity improves with thickness of the film. Table 1: Ellipsometry results of the thickness measurements of spray coated Al2O3. Wafer A Wafer B Position Thickness (nm) Refractive Index Thickness (nm) Refractive Index Center (1) Left (2) Right (3) Top (4) Bottom (5) The process is being further optimized for thickness uniformity improvements Low Temperature Oxy-nitride for Surface Passivation of Silicon Solar Cells (Sandeep S. S.): Crystalline silicon solar cells were fabricated on 125 x 125 mm quasi Mono wafers of resistivity, 1 3 Ω-cm, using commercial screen printing technology. Phosphorus diffusion was carried out in a diffusion furnace using POCl 3 as the source. Sheet resistance was measured using a four probe system and it was found to be ~ 65Ω/sq. After removal of phosphosilicate glass in diluted HF solution, thin silicon oxy-nitride films were grown in N 2O ambient at 380oC. The growth time was varied from 5 to 40 mins to grow films of different thickness. The film composition was studied using X-ray photoelectron spectroscopy and FTIR spectroscopy. Silicon nitride film of ~80 nm was deposited on the silicon oxy-nitride film. A sample without any silicon oxy-nitride film was used as the reference sample for the 3

4 experiments. Screen printed silver was used as the front contact and screen printed Aluminum was used as the back contact. Contact firing process was carried out at 850 oc in N2+O2 ambient in a rapid thermal annealing chamber. The solar cell characteristics are measured under one sun illumination using AM 1.5G spectrum on a AAA rated solar cell simulator. The spectral response of the solar cell was studied using a Quantum efficiency measurement system. Fig. 5: (a) FTIR curve for varying film growth Fig. 5: (b). XPS N1s spectrum for a film times in N2O ambient. grown for 5 mins in PECVD Fig. 5 (a) shows the FTIR spectrum for the plasma grown films in N 2O ambient in a PECVD chamber for varying plasma exposure times. Similar to the remote plasma system, the films grown in PECVD chamber also showed interstitial peaks at 15 cm -1. The film grown for 5 mins showed the strongest interstitial peak, while the films grown for larger time started exhibiting a strong shoulder corresponding to the Si-O-Si stretching mode vibrations at 68 cm-1, similar to films grown in remote plasma system. The variation in film composition with plasma exposure time was investigated using XPS. Fig. 5(b) shows the smoothened N1s spectrum for the film grown in plasma for 5 min, confirming that the film is a silicon oxynitride. Fig. 6: (a) I-V curve for Solar Cells with Fig. 6: (b) IQE for solar cells with various various front surface passivation stacks front surface passivation stacks From the solar cell characteristics, it was observed that with increasing film growth times, the open circuit voltage (Voc) increased from 589 mv for the cells with a stack of SiO xny (5mins)/SiNv:H as front surface passivation layer to 602 mv for a front surface passivation stack of SiOxNy (40mins)/SiNv:H. In comparision, the reference cell fabricated with SiNv:H as the front surface passivation layer had a V oc of 596 mv. Additionally, it was observed from the spectral response that the blue response improved for all solar cells with plasma grown oxy-nitride in comparison to the reference solar cell, as shown in Fig. 6(b). From the results obtained, it could be concluded that a better solar cell performance is obtained as the 4

5 interstitial oxygen content within the plasma grown silicon oxy-nitride film starts coming down. Development of Bilayer Silicon Nitride Film: In order to lower the reflectance and to improve the quality of surface passivation, a bilayer stack of a silicon rich (SiNr:H)/stoichiometric (SiNs:H) silicon nitride is proposed. The impact of varying the bottom layer film composition on the reflectance and the minority carrier lifetime was investigated. The films were deposited on p-type CZ textured wafers, with double sided phosphorus diffusion to emulate the emitter conditions in a solar cell. In our experiments, the Si rich layer deposition was carried out for 1 min, while the capping stoichiometric SiNs:H deposition was carried out for 5:30mins. Ammonia flow as kept constant throughout the experiments, and temperature of deposition was 380oC, and chamber pressure was kept at 650mT. Fig. 7: (a) Reflectance curves for varying Fig. 7: (b) Weighted average (Wav) reflectance silane dilution of SiNr:H film showing lower reflectance for increasing silane conc. of SiNr:H As can be seen in Fig. 7 (a), (b) the reflectance of the film decreases when the silane concentration of the bottom layer is increased. In all cases, the capping silicon nitride film remained the same. It was also observed, that the minority carrier lifetime increased with increasing silane concentration as can be seen in Fig. 8 (a). The lifetime was measured on textured CZ wafers, with phosphorus diffused on both sides. From the above results it may be safely concluded that the film is not only good in terms of low reflectance, but can also result in improved surface passivation quality. Fig. 8: (a) of 15 cm-3 for Fig. 8: (b) Reflectance curves showing lower increasing silane conc. of SiNr:H reflectance for increasing RF power used for SiNr:H deposition 5

6 Upon increasing the RF power of the bottom layer, it was observed that there was a further decrease in the reflectance of the stack. As the RF power increased from 20W to 50 W, the weighted average reflectance came down from ~ 2% to ~ 1.6%. Upon increasing the RF power further from 50W to 0W, no further improvement in reflectance was observed. Upon closely observing the reflectance curve shown in Fig. 8 (b), it can be seen that for the films deposited with 50W and 0W power, two minima can be observed. It was also observed that the minority carrier lifetime decreased from 350 µs to 160 µs as the RF power of the SiNr:H deposition was increased from 20W to 0W, as shown in Fig. 9 (b). It can thus be concluded that, upon increasing the RF power, the deposition rate of the film may have increased, resulting in a larger thickness for the SiNr:H layer. This may have resulted in a decrease in reflectance, which was a direct result of two minima which was seen in Fig. 8 (b). However, the increase in RF power also lead to a lower lifetime, which maybe the result of an increased surface damage at higher RF power. Fig. 9: (a) Lower Wav reflectance for increasing RF power used for SiNr:H deposition (b) of 15 cm-3 increasing RF power used for SiNr:H deposition D Junctions (Student: Som Mondal): The Glow Discharge Mass Spectroscopy (GDMS) and Electron Beam Induced Current (EBIC) measurement done in earlier case shows that significantly deep junction is formed. Sample preparation has been done using a new set of parameters of the laser which is expected to give higher junction depth. Sample preparation has been done using khz of repetition rate of laser and different pulse lengths ranging µs. In earlier case the values for the same parameters were 8.3 khz and a fixed pulsed length of 9.5 µs. For depth profiling analysis, samples have been sent for Plasma Profiling Time of Flight Mass Spectroscopy and we are awaiting the results. Samples for EBIC are prepared and will be done in due course of time Novel technology for contact formation using temperature sensitive paste (Sastry): A novel design for patterning of AR coatings using mechanical structure is designed. Also, using EDM wires the patterning mechanism is performed. Very fine finger widths are obtained using EDM wires. Wide variety of EDM wires are used to pattern range from 300 μm. Using this design, continuous fingers could not be printed due to wire alignment. Continuity in a printed line is required for the patterning of solar cells. For this, a new set up is designed. A spool of EDM wire is kept in the top left wheel in the design. From this, the wire passes to the bottom left wheel and paste container. Sufficient amount of etch paste is kept in the paste container. 0.5mm diameter nozzle is kept outside the paste container through which, the wire comes out and passes through bottom right wheel. Top right wheel is the end position for the wire which will drive all the wheels using electric motor with rpm. Paste containing wire 6

7 comes out of the container will be used for printing lines on solar cell. Exactly below the paste contained wire, the solar cell with pre heated condition is kept and using z-axis the wire is kept in contact with the solar cell. Paste contained wire contacts the solar cell and paste is transferred to it in continuous line form. Ultimately this is heated to 390 C. Again, the driving motor will pull the wire from the spool for the next printing. After single print, using x- axis in 3d stage, the cell is moved to next printing position accurately. Hence, continuous lines are printed with equal distance of separation on the solar cell. The cell is in heated condition until all the lines are printed on it. The process sequence for printing is moving down the z-axis for contacting solar cell, moving up the z-axis, moving spool of printed wire by driving motor for next printing, moving x-axis for next print line. In this process, the zaxis may be sufficient of greater than required. To optimize this, the exact value is to be calculated by varying different positions. With a fixed velocity (50 mm/sec), all the lines are printed with same conditions using 40 μm molybdenum EDM wire. The cell is pre heated to 390 C. Once, the cell is printed with required number of fingers, it is rotated in 90 C for the bus bar printing. The bus bar is also implemented once the finger lines are continuous. Printed cells are cleaned and observed for the thickness. Minimum finger width obtained is at 80 μm. Further process of metallization is underway. With the contact angle and initial conditions the simulation studies are carried out using Ansys software. For the initial calculations, some conditions are pre assumed. The simulation result gives contact angle of glass substrate with etch paste is at On the other hand, the experimental value of glass substrate measurement gives average 83. Hence, both are matching. With these conditions, only etch paste and molybdenum wire simulations are under progress Ni/Cu metallization for front contact (Mehul Raval): Complete solar cell with Ni-Cu-Sn front side metallization stack with efficiency > 15% were fabricated with characterization of background plating. Solar cells of size 4cm x 4cm processed till Al back contacts were used for fabricating complete cells. The front ARC was patterned using solar etch paste with line openings in range of 80-0 µm. An optimized electroless nickel alkaline bath with temperature in the range of C was used for deposition of thin nickel seed layer. Samples were annealed at 400 C in a tube-furnace with N2 ambient for nickel silicide formation. Subsequently, Cu-Sn plating was done for thickening the grid lines. Light I-V measurements were performed under standard test conditions, while dark I-V measurements were performed for local ideality factor variation analysis. SEM analysis was done to observe background plating on the front-side of solar cell. Fig. shows the illuminated I-V of the best cell. Higher value of J 02 and reduced shunt resistance were the reason for a reduced fill factor which can be improved further by appropriate precautions during the metallization process. Background plated deposits with size in the range of 2-5 µm are observed as shown in Fig. 11. Deposits with larger size of 15 µm are also observed which tend to coalesce, forming chain like structures. EDS analysis at the background plated region-silicon interface indicated presence of nickel and phosphorus, confirming their deposition from the electroless nickel bath. To understand the apparent junction recombination mechanism better, local ideality factor variation is observed for the fabricated cells. Fig. 12 shows the dark I-V data and m versus voltage plot for few of the fabricated cells. As can be observed for screen-printed cells, the first hump around 0.2V is due to an exponential factor of 2 corresponding to junction recombination and edge combination, which tends to dominate for smaller cells. The addition 7

8 hump observed at around 0.4V for Ni-Cu based contacts may be attributed to localized schottky contacts resulting from isolated metal-silicon interfaces introduced due to background plating. Incorporation of resistance limited recombination component to the standard two-diode model will explain background plating related losses more correctly for such cells. Fig. : Lighted I-V of best cell with Ni-Cu Fig. 11. Background plated areas with based front side metallization. particle size of around 2 to 5.5 µm. Fig. 12: (a) Dark I-V data of fabricated Ni-Cu based cells and conventional screen-printed cell as reference (b) ideality factor m versus voltage variation from dark I-V of the respective cells Plasmonics for Photovoltaic Application (Hemant Kumar Singh): We have shown in earlier report that we are able to minimize the reflection from sandwiching the Ag ultra thin film which results in better trapping of light and hence reduced reflection in UV-Vis region. However in the IR region this shows still relatively higher reflection. In order to get better broadband ( nm) anti reflection property from sandwiched structure, we optimized further the dielectric-metal-dielectric sandwiched structure. Here we used Ag ultra thin film sandwiched in SiNx top and bottom layer on p-type Si substrate. The device geometry used for fabrication is shown in Fig. 13 (a). Fig. 13 (b) shows the cross sectional SEM image of the best sample based on dielectric-metal-dielectric (D-M-D) plasmonic ARC structure. 8

9 Fig. 13: (a) Device geometry under study (Si-SiNx-Ag-SiNx) (b) Cross sectional image of best sample based on dielectric-metal-dielectric (D-M-D) plasmonic ARC structure. It is observed that for such multilayer geometry, 80 nm bottom and top SiN x layer with 8 nm of Ag ultra thin film intermediate layer, the weighted reflectance (WR) is minimum for broad wavelength range 300 nm nm. It is calculated around 8.1 % which is 41 % lesser than standard 80 nm SiNx based ARC geometry which is in the range of 13.8 %. Also for this, the anti-reflection property in infrared wavelength region is much better than previously fabricated device structure. The total reflectance plot is shown in Fig. 14(a) for Si/SiNx(80nm) and the best sample Si/SiNx/Ag-UTF/SiNx (Plasmonic ARC D-M-D structure). Fig. 14(b) shows the weighted total reflectance bar plot for standard 80 nm based ARC structure i.e. Si/SiNx(80nm) and the best sample Si/SiNx/Ag-UTF/SiNx (Plasmonic ARC D-M-D structure). It is clear from the Fig. 14(b), the D-M-D structure improves the antireflection property both in UV-Vis as well as infrared wavelength range. For 80 nm SiN x based D-M-D structure the TWR for UV-Vis wavelength range was.1 % compared to 13 % for standard 80 nm SiNx based ARC structure. Also the most reasonable improvement is seen in infrared wavelength range while maintaining the lower reflection in UV-Vis wavelength range as TWR as low as 5.5 % is observed for IR range (700nm -1200nm) which was 14.7 % for standard 80 nm SiNx based ARC structure. Fig: 14: (a) Total reflectance plot for Si/SiN x(80nm) and the best sample Si/SiNx/AgUTF/SiNx (Plasmonic ARC D-M-D structure) (b) Weighted total reflectance (TWR) bar plot for standard 80 nm based ARC structure i.e. Si/SiNx(80nm) and the best sample Si/SiNx/AgUTF/SiNx (Plasmonic ARC D-M-D structure). Back colour bar represents the calculated TWR for wavelength range 300 nm nm; Red colour bar represents the calculated TWR for wavelength range 300 nm -700 nm (UV-Vis range); Blue colour bar represents the calculated TWR for wavelength range 700 nm nm (Infrared range). 9

10 We expect for further improvement in the broadband ARC property for such dielectric-metaldielectric structure and also our next target is to incorporate this plasmonic ARC in actual solar cell and see the relative performance improvement. For this, the work is in progress. In summary we have shown till now the best anti-reflection property using dielectric-metaldielectric structure on non-textured Si substrate with weighed total reflectance of 8.1 % for broad wavelength range 300 nm nm which is 41 % lesser than standard 80 nm SiN x based ARC structure on non-textured Si substrate Slicing of silicon wafers for PV applications using Wire Electric Discharge Machining (We-EDM) (Kamesh Joshi): During the past 3 months, the following activities were undertaken: 1. Installation of newly purchased wire-edm machine. Wire EDM machine of Accutex-300i was installed in the lab. 2. Commencement of the machine and training. The training of the machine was done about the NC code generation and cutting. First hand trials was done on different materials like steel, aluminum, titanium and brass. 3. Cutting of silicon ingots to find the optimum parameters for the cutting. Cutting wire: a. Material: Brass b. Diameter: 250, 0 µm. c. Polarity: Positive Cutting parameters: The cutting parameters are adjusted such that while cutting the breakage of wire and wafers does not happen and the target was to achieve the minimum wafer thickness. a. For 250 µm wire S.No Cutting Parameter Value Unit 1 Current Ampere 2 Pulse on time Micro-second 3 Pulse off time 9-15 Micro-second 4 Open Voltage 74 Volts 5 Servo voltage 45 Volts 6 Water pressure 8 Kg/cm2 7 Wire feed rate 35 mm/s Note: The mentioned values of the parameters were only for the wire of 250 µm. The minimum wafer size obtained was 800 µm. b. For 0 µm wire S.No Cutting Parameter Value Unit 1 Current Ampere 2 Pulse on time 0.35 Micro-second 3 Pulse off time 7.0 Micro-second 4 Open Voltage 68 Volts 5 Servo voltage 42 Volts 6 Water pressure 4 Kg/cm2 7 Wire feed rate 92 mm/s Note: The minimum wafer size obtained was 150 µm.

11 To find the slicing speed of the cutting of silicon wafer as a function of wafer thickness and slicing area and study its sub-surface damage, the following experiments were carried out: 1. Trial experiments to find minimum wafer thickness by variation of the cutting parameters like voltage, current, pulse on time, pulse off time, flushing pressure and wire tension. 2. To find slicing speed of silicon wafer based on the different cutting parameters. The following observations were made from the experiments: 1. With the increase in input cutting energy the slicing speed was observed to be increased. 2. At high cutting energy, obtained wafer thickness was also high and at lower cutting energies thinner wafers were obtained. 11