inemi Project Report on Process Development of BiSn-Based Low-Temperature Solder Pastes

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1 inemi Project Report on Process Development of BiSn-Based Low-Temperature Solder Pastes Raiyo Aspandiar Intel Corporation 1

2 Co-authors Name Company Name Company Haley Fu inemi, China Scott Mokler Intel Corp, Oregon, USA Jimmy Chen Flex Corp, Zhuhai, China Jagadeesh Radhakrishnan Intel Corp, California, USA Shunfeng Cheng Intel Corp, Oregon, USA Morgana Ribas Alpha Assembly Systems, India Qin Chen Eunow, Suzhou, China Brook Sandy-Smith Indium Corp, New York, USA Richard Coyle Nokia, New Jersey, USA Kok Kwan Tang Intel Corp, Kulim, Malaysia Sophia Feng Celestica, Dongguan, China Greg Wu Wistron, Hsinchu, Taiwan Mark Krmpotich Microsoft Corp, Washington, USA Anny Zhang Indium Corp, Washington, USA Ron Lasky Indium Corp, New Hampshire, USA Wilson Zhen Lenovo, Shenzhen, China 2

3 Outline Motivation for Low Temperature Solders inemi Low Temperature Solder Processing and Reliability (LTSPR) Project Info List of Solder Pastes Evaluated and Reasons why Component and Board Test Vehicles Process Evaluations Printability / Reflow Profiles / Solder Joint Defects / Rework / SIR Summary and Next Steps Q & A 3

4 Motivation for Low Temperature Solder (LTS) Reflow Faster Technology Scaling Energy & Emissions Process & Materials 1.5 I/O Density Pkg X-Y Reduced Emissions saves 57 metric tons of CO 2 per oven/year Wave Solder Elimination Reduced Electricity Saves > $8,500/oven/year SKL-Y 20x16.5x0.91mm LTS Enables System Manufacturing to Keep Pace with Moore s Law Solder Material Cost Reduction 5 Motivation spans multiple areas 4

5 Volume % of Solder Paste for Board Assembly Low Temperature Solder Paste s % Share of the Total Volume of Solder Paste Used for Board Assembly Source: inemi 2017 Roadmap Low Temperature Solder Pastes Year Increasing trend forecast in Low Temperature Solder paste Usage starting

6 Low Temperature Solders Enter Text There are a variety of compositions and melting ranges for Potential Low Temperature Solders in Electronics Manufacturing Medium Temperature Solders [SnAgCu+Bi,In] melt in the 210 to 220C range Low Temperature Solders [Bi/Sn/X, X=Ag,Cu,Ni] melt in the 139 to 175C range Bi-Sn system solders selected for LTSPR Project o Significantly larger processing and economic benefits than Medium Temperature Solders 6

7 inemi LTSPR Project Participants 22 Participants Mix of o EMS/ODMs o OEMs o Suppliers o Universities Binghamton University 7

8 inemi LTSPR Project Phases and Timeline Team Formation and SOW Ratification Materials Selection and Process Development Mechanical Shock Testing and Evaluation Temperature Cycling and other Reliabiliy Evaluations Manufacturing Validation of Product Board

9 Module Major issue with BiSn based Solders o Brittleness of Solder Joints formed using BiSn solder paste Bi causes joint hardening and is prone to brittle fractures under mechanical shock and drop forces BGA Solder Joint Example SAC region Bi-mixed region Mechanical Shock or Drop Fracture Through / above IMC Bi region of solder joint crack Bi region of Mixed BGA solder joint crack PCB Land Cracking in the solder and along the solder/imc interface Bismuth is inherently more brittle than Tin 9

10 Paths to Reduce BiSn Solder Joint Embrittlement Ductile Bi-Sn Metallurgy Resin Reinforcement At Package level Corner Glue Ductile BiSn based Region Resin Applied around the corners of Package and cured either during or post reflow soldering At Solder Joint Level Cured Resin Various alternative strategies chosen by solder paste suppliers to modify the solder metallurgy for reduction in brittleness of mixed SAC-BiSn solder joints Resin added in the solder paste cures during reflow soldering process Such resin containing pastes are called Joint Reinforcement Pastes (JRP) Both Paths considered for INEMI LTSPR Project 10

11 Code # Name Solder Pastes Evaluated Paste Category Board Assembly Site Liquidus Temp, C D197 Raja Kunyit SAC 1, D166 Balik Pulau Bi-Sn D165 Chee Chee Baseline D160 Teka D158 Kan You D200 Black Thorn D175 Red Prawn Ductile Bi-Sn D164 Red Flesh D24 Sultan D163 Horlor D159 Golden Pillow JRP Resin D145 Beserah Bi-Sn Based D123 Chanee Distribution with Four Categories 5 Ductile Bi-Sn Metallurgy pastes 4 Resin Reinforced Bi-Sn pastes 3 Bi-Sn baseline pastes (0%, 0.4%, 1%Ag) 1 SAC paste to serve as current technology baseline 11

12 6 inches Board Test Vehicle Design and Components 7 inches Designation Description Qnty PCB FC BGA LGA CPU Socket LGA CPU Socket QFN 6 x7 x0.040, 8 layers, OSP surface finish 16x24mm, 0.4mm nominal pitch, SAC405 solder spheres 2066 pins, Bi-Sn-Ag solder spheres 2066 pins, SAC305 solder spheres 10x10mm, center ground pad, 72 terminations, 0.5mm pitch, Daisy Chain 1 N/A 2 Yes 1 No 1 No 2 Yes QFP100L 14x14mm, 0.5mm pitch 2 Yes QFP208L 28x28mm, 0.5mm pitch 2 Yes Chip Cap 0402 Pad design with 20 Yes Chip Cap /6/8/12 mils body to 20 Yes Chip Cap body spacing 20 Yes Switch Tactile switch with SMT and THM pins 2 No DDR4 THM Connector 1 No USB3 THM Connector 1 No 1.0 mm thick, 8 layers, OSP Surface finish 12

13 Stencil Printing Evaluation Goal: To compare printing efficiency of the four solder paste categories Stencil Materials: Laser Etch Stainless Steel stencils and Squeegees No paste transfer enhancement Equipment Parameters Set Up: As specified by paste supplier, but tweaked during process development Measurement: Printed Paste Volume for 10 th print after set up Analysis: Transfer Efficiency and Coefficient of Variation for each area ratio Results of pastes in each category lumped together Data from stencil apertures with the three smallest Area Ratios presented Stencil Aperture Component Area Ratio for Lands Chip FC BGA 0.59 Chip

14 Transfer Efficiency of Four Solder Paste Categories Trends Observed %TE decreases markedly with decrease in Area Ratio No significant decrease in %TE for the four categories down to 0.59 Area Ratio At Lowest Area Ratio of 0.5, JRP Resin reinforced pastes are significantly worse than the other three Resin impact is felt at the lowest area Ratio stencil apertures 14

15 Coefficient of Variation of Four Solder Paste Categories Trends Observed Coefficient of Variation increase significantly from 0.59 to 0.5 stencil aperture area ratios JRP Resin reinforced solder paste has the higher coefficient of variation at the lowest area ratio aperture evaluated As in the case of the Transfer Efficiency, the impact of resin contained in JRP solder pastes is felt at the lowest area Ratio stencil apertures 15

16 Typical Reflow Soldering Profiles -- For Each Category of Solder Paste -- Reflow Soldering Profile Zone Reflow Profile Property Comparison Between Paste Categories Initial Ramp Ramp Rate SAC is significantly lower Soak Temperature SAC significant higher Time No significant difference Peak Reflow Temperature SAC is significant higher JRP resin is significant lower Reflow JRP Resin is significant higher Time above Bi-Sn baseline is significant Liquidus lower Cool Down Cooling Rate No significant difference Significant Differences in Key Solder Reflow Profile Categories for the four categories of Solder Pastes Studied 16

17 Dye & Pry Cross-sections Partial Wetting Solder joints Defects -- All for FCBGA component when using JRP Resin Pastes -- D145 - Beserah D123 - Chanee D159 Golden Pillow Partial wetting Void near T3 interface Separation at T3 interface IMC present Cured resin D123 - Chanee Partial wetting of PCB Land These defects can arise due to premature gelling of the resin before the solder powder in the paste has melted and wetted the SAC solder spheres on the package The initial Ramp Rate of the reflow profile is critical in the formation of this defect 17

18 Temperature, C Partial Wetting Defects Potential Mechanism Reflow Temperature Plateau Solder Joint Formation Resin Curing Phase Time above Liquidus/ Resin Curing Time, secs Trapezoidal Shape to the profile Critical parameters: Initial Ramp Rate, Reflow Temperature Plateau and Time Above Liquidus/ Resin Curing time Initial Ramp Rate is very important Solder Paste has to melt, wet the lands and the solder ball BEFORE the resin starts to gel and its decrease its viscosity in its cure progression Time, seconds If ramp rate is slow, resin will gel and cure before the solder joint has fully formed and lead to partial wetting 18

19 Hot Tearing Defects for FCBGA Solder Joints D200 (Black Thorn) Hot Tearing Observations All defective solder joints were under the Silicon Die Shadow D165 (Cheh Chee) For D200 Solder Paste, the defect occurred o at the PCB Land to Solder Interface o D200 solder alloy had ~15% Bismuth content in solder, with a large pasty range D158 (Kan You) D160 (Teka) For the other three solder pastes (D165, D158, D160) the defect Occurred at the Package Substrate to Solder Interface Bismuth stratification observed at this interface These three solder paste gave the highest level of bismuth mixing in the solder joints 19

20 GOOD SOLDER JOINTS FOR VARIOUS COMPONENTS Paste Category 0402 Chip FCBGA SKT R4 (SAC Sphere) SKT R4 (BiSnAg Sphere) QFN Termination QFN Ground Pad DDR4 P-i-P THM Bi-Sn Baseline Ductile Bi-Sn JRP Resin 20

21 Scoring Table for Each Rework Process Attribute B Attribute Part removal Score Suction + High force, cannot be removed Suction + High force, to pry and removed Suction + Medium force to pry and remove Suction + low force to pry and remove Removes on tool suction alone C Amount of material left >75% 50%-75% 25-50% 10-25% 0-10% D No. of pads damaged >9 6~9 3~6 1~2 0 E No. of traces damaged >9 6~9 3~6 1~2 0 G Time for flux or resin residue removal >10mins 10mins 8mins 5mins 3mins H Time for solder wicking >10mins 10mins 8mins 5mins 3mins I Solder mask damage Significant damage (>15% area of site) Damage to 10~ 15% area Damage to 5~ 10% area Damage to <5% area No damage J Ergo Behavior Not Possible High Force Medium Force Low Force Minimal Force For each Component Reworked an assessment of the ease of rework was made by assigning a score to that particular rework attribute based on the scoring guidelines in table above Scores of 10 are the best and highest attainable Scores between 9 and 5 are termed moderate Scores below 4 are termed low 21

22 Rework Assessment Scores for Each Attribute Downtrend Downtrend No Effect for JRP Resin Pastes No damage to traces with low temperature solders Lower Scores for JRP Resin Lower Scores for JRP Resin Significantly Less Damage for low temp pastes Weak trend G - Time for flux (or resin) residue removal When compared to the higher melting SAC solder joints, the lower melting temperature of the solder joints formed with Bi-Sn solder pastes facilitates easier part removal and site redress. Reduces Incidences of solder mask and trace damage When using resin-reinforced low-temperature JRP solder pastes, the presence of cured resin for solder joints formed results in a longer site redress process. 22

23 SIR measurements for All Pastes IPC-650 Method using IPC-B-24 coupons All measured SIR values above 1x10 8 ohms level, which is lower limit Three pastes had significantly lower values than their control boards 23

24 Summary inemi initiated the LTSRP project in 2015 to evaluate new Bi-Sn based solder pastes Phase 1 of this project was to evaluate the SMT processability of these new pastes Salient Results of this Phase 1 Evaluation are shown below Process / Property Solder Paste Type Bi-Sn Baseline Ductile Bi-Sn JRP resin Stencil Printability Equivalent to SAC even at <0.66 area ratio stencil apertures Worse at the lowest Area ratio (0.50) evaluated Ramp-Soak-Peak Topography Trapezoidal Topography Key Reflow Profile Parameters Initial Ramp Rate higher than SAC pastes but achievable in currently used ovens Soak Temperature lower than SAC No Soak Zone Reflow Temperature lower than SAC Reflow Temperature lowest Time above Liquidus (TAL) lower than SAC TAL longer than SAC 24

25 Process / Property Solder Joint Defects Rework (FCBGA and QFN) Surface Insulation Resistance (SIR) Summary (continued) Solder Paste Type Bi-Sn Baseline Ductile Bi-Sn JRP resin FCBGA: Hot Tearing under die shadow for some solder pastes due to interaction of Bi mixing in SAC ball, component substrate warpage and cooling rate during reflow soldering Easier part removal and site redress as well as reduction in solder mask and trace damage FCBGA and P-i-P THM: Partial Wetting due to premature resin curing Less damage to solder mask and trace but site Redress process takes longer due to cured resin All Solder Pastes met the 1 x10 8 value when tested using IPC-650 Method and B-24 coupons Mechanical Shock Robustness of PoP and FCBGA component solder joints formed with these solder pastes in ongoing ; Accelerated Temperature Cycling Evaluation is planned 25

26 Thank You! Acknowledgment The authors acknowledge the engagement, effort and contribution of the whole participating project team members: Intel, Celestica, Wistron, IBM, Lenovo, Nokia, Flex, ist, Indium, Senju, Alpha, Interflux, Eunow, Shinko, Nihon Superior, Heraeus, Dell, Keysight, Abbott, Microsoft, Binghamton Univerisity and Purdue University. We also appreciate the in-kind contribution of materials, components and PCBs to our project study from ASE, FIT, Lotes, Molex, Tripod, ITEQ, Tamura, Panasonic and Yincae. 26

27 27

28 BACK UP 28

29 SIR Measurement Method IPC-650 Method Experimental Parameters IPC-B-24 Coupon Temperature, C Humidity, % RH Bias, Volt Frequency of Measurement, Mins Total Duration of Measurements, Hours 40 (+/- 1) 90 (+/- 3) Each Solder Paste Supplier Prepared the Coupons themselves for their solder paste At least 2 Control Coupons and 3 Coupons with Solder Pastes applied per Solder paste Evaluated SIR Test run and Measurements done at an independent testing house 4 nets 29

30 SIR, Ohms (Log Scale) SIR vs Time Measurements for Three Solder Pastes Paste Code Paste Category SIR Trend beyond 50 hours Balik Pulau Bi-Sn Baseline Up Chanee JRP Resin Down Teka Bi-Sn Baseline Down These three pastes had significantly lower SIR values for the coupons applied with solder paste when compared to the control coupons But All measured values were above 1x 10 8 Ohms lower limit Limit Measurement Time, Hours 30

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